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* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | llvm-svn: 179544
* Fix a typo in comment.Jim Grosbach2013-04-151-1/+1
| | | | llvm-svn: 179542
* Make the host endianness check an integer constant expression.Rafael Espindola2013-04-155-10/+10
| | | | | | | | | | | | | | | I will remove the isBigEndianHost function once I update clang. The ifdef logic is designed to * not use configure/cmake to avoid breaking -arch i686 -arch ppc. * default to little endian * be as small as possible It looks like sys/endian.h is the preferred header on most modern BSD systems, but it is better to change this in a followup patch as machine/endian.h is available on FreeBSD, OpenBSD, NetBSD and OS X. llvm-svn: 179527
* Replace uses of the deprecated std::auto_ptr with OwningPtr.Andy Gibbs2013-04-151-23/+22
| | | | | | This is a rework of the broken parts in r179373 which were subsequently reverted in r179374 due to incompatibility with C++98 compilers. This version should be ok under C++98. llvm-svn: 179520
* Add an option -vectorize-slp-aggressive for running the BB vectorizer. Make ↵Nadav Rotem2013-04-151-1/+12
| | | | | | -fslp-vectorize run the slp-vectorizer. llvm-svn: 179508
* Rename the slp-vectorizer clang/llvm flags. No functionality change.Nadav Rotem2013-04-151-3/+3
| | | | llvm-svn: 179505
* SLPVectorizer: Add support for vectorizing trees that start at compare ↵Nadav Rotem2013-04-151-21/+40
| | | | | | instructions. llvm-svn: 179504
* Mark all PPC comparison instructions as not having side effectsHal Finkel2013-04-152-20/+28
| | | | | | | | | | Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. llvm-svn: 179502
* Fix PPC64 CR spill location for callee-saved registersHal Finkel2013-04-152-35/+50
| | | | | | | | | | | | | | | | This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). llvm-svn: 179500
* Use object file specific section type for initial text sectionNico Rieck2013-04-142-12/+3
| | | | llvm-svn: 179494
* Reorders two transforms that collide with each otherDavid Majnemer2013-04-141-8/+8
| | | | | | | | | | | | | | | | | | | | | | One performs: (X == 13 | X == 14) -> X-13 <u 2 The other: (A == C1 || A == C2) -> (A & ~(C1 ^ C2)) == C1 The problem is that there are certain values of C1 and C2 that trigger both transforms but the first one blocks out the second, this generates suboptimal code. Reordering the transforms should be better in every case and allows us to do interesting stuff like turn: %shr = lshr i32 %X, 4 %and = and i32 %shr, 15 %add = add i32 %and, -14 %tobool = icmp ne i32 %add, 0 into: %and = and i32 %X, 240 %tobool = icmp ne i32 %and, 224 llvm-svn: 179493
* Miscellaneous cleanups for VecUtils.hBenjamin Kramer2013-04-141-9/+6
| | | | llvm-svn: 179483
* SLP: Document the scalarization cost method.Nadav Rotem2013-04-141-3/+10
| | | | llvm-svn: 179479
* Document the decision to assume that the cost of floats is twice as much as ↵Nadav Rotem2013-04-141-1/+3
| | | | | | integers. llvm-svn: 179478
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-144-7/+8
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* SLPVectorizer: Add support for trees that don't start at binary operators, ↵Nadav Rotem2013-04-143-7/+25
| | | | | | and add the cost of extracting values from the roots of the tree. llvm-svn: 179475
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-141-6/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen2013-04-141-16/+34
| | | | | | | 64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. llvm-svn: 179472
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-142-26/+36
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* SLPVectorizer: add initial support for reduction variable vectorization.Nadav Rotem2013-04-143-7/+95
| | | | llvm-svn: 179470
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-4/+2
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-143-14/+95
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriatelyHal Finkel2013-04-133-15/+16
| | | | | | | | | | | | Leaving MFCR has having unmodeled side effects is not enough to prevent unwanted instruction reordering post-RA. We could probably apply a stronger barrier attribute, but there is a better way: Add all (not just the first) CR to be spilled as live-in to the entry block, and add all CRs to the MFCR instruction as implicitly killed. Unfortunately, I don't have a small test case. llvm-svn: 179465
* Define SPARC code models.Jakob Stoklund Olesen2013-04-132-4/+32
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen2013-04-131-3/+4
| | | | | | | It doesn't seem like anybody is checking types this late in isel, so no test case. llvm-svn: 179462
* GlobalDCE: Fix an oversight in my last commit that could lead to crashes.Benjamin Kramer2013-04-131-2/+2
| | | | | | There is a Constant with non-constant operands: blockaddress. llvm-svn: 179460
* Fix a scalability issue with complex ConstantExprs.Benjamin Kramer2013-04-133-25/+52
| | | | | | | | | | | | | | | This is basically the same fix in three different places. We use a set to avoid walking the whole tree of a big ConstantExprs multiple times. For example: (select cmp, (add big_expr 1), (add big_expr 2)) We don't want to visit big_expr twice here, it may consist of thousands of nodes. The testcase exercises this by creating an insanely large ConstantExprs out of a loop. It's questionable if the optimizer should ever create those, but this can be triggered with real C code. Fixes PR15714. llvm-svn: 179458
* Spill and restore PPC CR registers using the FP when we have oneHal Finkel2013-04-131-6/+14
| | | | | | | | | | For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). llvm-svn: 179457
* MI-Sched: DEBUG formatting.Andrew Trick2013-04-131-14/+22
| | | | llvm-svn: 179452
* MI-Sched cleanup. If an instruction has no valid sched class, do not attempt ↵Andrew Trick2013-04-131-0/+2
| | | | | | to check for a variant. llvm-svn: 179451
* X86 machine model: reduce SandyBridge and Haswell ILPWindow.Andrew Trick2013-04-132-2/+2
| | | | | | | | | | | | | | | The initial values were arbitrary. I want them to be more conservative. This represents the number of latency cycles hidden by OOO execution. In practice, I think it should be within a small factor of the complex floating point operation latency so the scheduler can make some attempt to hide latency even for smallish blocks. These are by no means the best values, just a starting point for tuning heuristics. Some benchmarks such as TSVC run faster with this lower value for SandyBridge. I haven't run anything on Haswell, but it's shouldn't be 2x SB. llvm-svn: 179450
* MI-Sched: schedule physreg copies.Andrew Trick2013-04-132-1/+76
| | | | | | | | | | | The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. llvm-svn: 179449
* Catch another case where SD fails to propagate node order.Andrew Trick2013-04-131-1/+4
| | | | | | | | | | I need to handle this for the test case in my following scheduler commit. Work is already under way to redesign the mechanism for node order propagation because this case by case approach is unmaintainable. llvm-svn: 179448
* [mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka2013-04-134-172/+174
| | | | | | | | lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. llvm-svn: 179444
* Finish templating MachObjectFile over endianness.Rafael Espindola2013-04-131-417/+15
| | | | | | | We are now able to handle big endian macho files in llvm-readobject. Thanks to David Fang for providing the object files. llvm-svn: 179440
* [mips] Reapply r179420 and r179421.Akira Hatanaka2013-04-134-11/+41
| | | | llvm-svn: 179434
* [mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka2013-04-131-0/+5
| | | | llvm-svn: 179433
* [ms-inline asm] Simplify the logic by using parsePrimaryExpr. No functionalChad Rosier2013-04-121-1/+1
| | | | | | | change intended. Test case previously added in r178568. Part of rdar://13611297 llvm-svn: 179425
* Revert r179420 and r179421.Akira Hatanaka2013-04-124-41/+11
| | | | llvm-svn: 179422
* [mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka2013-04-123-6/+15
| | | | | | instructions. llvm-svn: 179421
* [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka2013-04-122-5/+26
| | | | llvm-svn: 179420
* Revert r179409 because it caused some warnings and some of the build bots fail.Nadav Rotem2013-04-121-277/+44
| | | | llvm-svn: 179418
* InstCombine: Check the operand types before merging fcmp ord & fcmp ord.Benjamin Kramer2013-04-121-0/+3
| | | | | | Fixes PR15737. llvm-svn: 179417
* SLPVectorizer: add support for vectorization of diamond shaped trees. We now ↵Nadav Rotem2013-04-122-46/+254
| | | | | | perform a preliminary traversal of the graph to collect values with multiple users and check where the users came from. llvm-svn: 179414
* CostModel: increase the default cost of supported floating point operations ↵Nadav Rotem2013-04-121-4/+7
| | | | | | from 1 to two. Fixed a few tests that changes because now the cost of one insert + a vector operation on two doubles is lower than two scalar operations on doubles. llvm-svn: 179413
* Add debug prints.Nadav Rotem2013-04-121-1/+5
| | | | llvm-svn: 179412
* Add support for additional vector instructions in the interpreter.Nadav Rotem2013-04-121-44/+277
| | | | | | patch by Veselov, Yuri <Yuri.Veselov@intel.com>. llvm-svn: 179409
* [ms-inline asm] Move this logic into a static function as it's only applicableChad Rosier2013-04-121-63/+67
| | | | | | when parsing MS-style inline assembly. No functional change intended. llvm-svn: 179407
* [ms-inline asm] Address the FIXME for ImmDisp before brackets. ThisChad Rosier2013-04-121-18/+29
| | | | | | | | is a follow on to r179393 and r179399. Test case to be added on the clang side. Part of rdar://13453209 llvm-svn: 179403
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