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* MAP_FILE is the default. We don't need to add it.Rafael Espindola2014-12-121-3/+0
| | | | llvm-svn: 224144
* More code format fix from r224133, NFCSteven Wu2014-12-121-2/+1
| | | | llvm-svn: 224140
* Remove silly left over from the Windows resize_file implementation.Rafael Espindola2014-12-121-1/+0
| | | | | | | I didn't notice the problem first because on a non debug build the CRT was just exiting the process without any message. llvm-svn: 224139
* Move the resize file feature from mapped_file_region to the only user.Rafael Espindola2014-12-122-13/+5
| | | | | | This removes a duplicated stat on every file that llvm-ar looks at. llvm-svn: 224138
* Pass a FD to resise_file and add a testcase.Rafael Espindola2014-12-122-17/+6
| | | | | | I will add a real use in another commit. llvm-svn: 224136
* Remove unused feature. NFC.Rafael Espindola2014-12-121-7/+1
| | | | llvm-svn: 224135
* Restructure code from r224097. NFCSteven Wu2014-12-121-12/+12
| | | | llvm-svn: 224133
* [AVX512] Enabling bit logic loweringRobert Khasanov2014-12-122-0/+9
| | | | | | Added lowering tests. llvm-svn: 224132
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-123-9/+17
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [AVX512] Enabling MIN/MAX lowering.Robert Khasanov2014-12-122-4/+19
| | | | | | Added lowering tests. llvm-svn: 224127
* Reapply "[MachineScheduler] Fix for PR21807: minor code difference building ↵Andrea Di Biagio2014-12-121-1/+3
| | | | | | | | | | | with/without -g." This reapplies r224118 with a fix for test 'misched-code-difference-with-debug.ll'. That test was failing on some buildbots because it was x86 specific but it was missing a target triple. Added an explicit triple to test misched-code-difference-with-debug.ll. llvm-svn: 224126
* [Reassociate] Use dbgs() instead of errs().Chad Rosier2014-12-121-2/+2
| | | | llvm-svn: 224125
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-124-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* [AVX512] Minor fix in lowering pattern for broadcast intrustions.Robert Khasanov2014-12-121-6/+5
| | | | | | No functional change. llvm-svn: 224122
* Revert: [MachineScheduler] Fix for PR21807: minor code difference building ↵Andrea Di Biagio2014-12-121-3/+1
| | | | | | | | with/without -g. Test 'misched-code-difference-with-debug.ll' was failing on some buildbots. llvm-svn: 224121
* This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling ↵Suyog Sarda2014-12-121-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into vector of loads, and vectorizes it. Test case : float hadd(float* a) { return (a[0] + a[1]) + (a[2] + a[3]); } AArch64 assembly before patch : ldp s0, s1, [x0] ldp s2, s3, [x0, #8] fadd s0, s0, s1 fadd s1, s2, s3 fadd s0, s0, s1 ret AArch64 assembly after patch : ldp d0, d1, [x0] fadd v0.2s, v0.2s, v1.2s faddp s0, v0.2s ret Reviewed Link : http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141208/248531.html llvm-svn: 224119
* [MachineScheduler] Fix for PR21807: minor code difference building ↵Andrea Di Biagio2014-12-121-1/+3
| | | | | | | | | | | | | | | | | with/without -g. This patch fixes the issue reported as PR21807. There was a minor difference in the generated code depending on the -g flag. The cause was that with -g the machine scheduler used a different scheduling strategy. This decision was based on the number of instructions in a schedule region and included debug instructions in that count. This patch fixes the issue in MISched and provides a test. Patch by Russell Gallop! llvm-svn: 224118
* Emit Tag_ABI_FP_16bit_format build attribute.Charlie Turner2014-12-121-0/+7
| | | | | | | | | | | | | The __fp16 type is unconditionally exposed. Since -mfp16-format is not yet supported, there is not a user switch to change this behaviour. This build attribute should capture the default behaviour of the compiler, which is to expose the IEEE 754 version of __fp16. When -mfp16-format is emitted, that will be the way to control the value of this build attribute. Change-Id: I8a46641ff0fd2ef8ad0af5f482a6d1af2ac3f6b0 llvm-svn: 224115
* A fix for PR21176. Ekaterina Romanova2014-12-121-0/+12
| | | | | | | | | | | DW_OP_const <const> doesn't describe a constant value, but a value at a constant address. The proper way to describe a constant value is DW_OP_constu <const>, DW_OP_stack_value. Added DW_OP_stack_value to the stack. Marked incorrect-variable-debugloc1.ll to xfail for PowerPC64, while the the failure (PR21881) is being investigated. llvm-svn: 224098
* Fix another infinite loop in InstCombineSteven Wu2014-12-121-9/+12
| | | | | | | | | | | | | | | Summary: InstCombine infinite-loops for the testcase added It is because InstCombine is generating instructions that can be optimized by itself. Fix by not optimizing frem if the optimized type is the same as original type. rdar://problem/19150820 Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D6634 llvm-svn: 224097
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-124-50/+60
| | | | | | | | The returned operand needs to be permuted for the unordered compares. Also fix incorrectly producing fmin_legacy / fmax_legacy for f64, which don't exist. llvm-svn: 224094
* R600/SI: fmin/fmax_legacy are not associativeMatt Arsenault2014-12-121-2/+2
| | | | llvm-svn: 224093
* R600/SI: Don't promote f32 select to i32Matt Arsenault2014-12-122-2/+5
| | | | | | | | This is nice for the instruction patterns, but it complicates min / max matching. The select doesn't have the correct type and would require looking through the bitcasts for the real float operands. llvm-svn: 224092
* Bitcode: Add missing "Remove in 4.0" commentsDuncan P. N. Exon Smith2014-12-121-0/+2
| | | | llvm-svn: 224090
* Document that PassManager::add() may delete the pass right away.Matthias Braun2014-12-121-17/+2
| | | | | | | | Also remove redundant documentation: - doxygen will copy documentation to overriden methods. - Use \copydoc on PIMPL classes instead of replicating the text. llvm-svn: 224089
* Comment and minor code cleanup for GCStrategy (NFC)Philip Reames2014-12-121-13/+0
| | | | | | Updating comments to reflect the current state of the world after my recent changes to ownership structure and generally better describe what a GCStrategy is and how it works. llvm-svn: 224086
* Add target hook for whether it is profitable to reduce load widthsMatt Arsenault2014-12-123-0/+29
| | | | | | | | Add an option to disable optimization to shrink truncated larger type loads to smaller type loads. On SI this prevents using scalar load instructions in some cases, since there are no scalar extloads. llvm-svn: 224084
* remove function names from comments; NFCSanjay Patel2014-12-111-29/+23
| | | | llvm-svn: 224080
* R600/SI: Handle physical registers in getOpRegClassMatt Arsenault2014-12-111-2/+7
| | | | llvm-svn: 224079
* R600/SI: Don't verify constant bus usage of flag opsMatt Arsenault2014-12-111-2/+10
| | | | | | | | | | | | This was checking if pseudo-operands like the source modifiers were using the constant bus, which happens to work because the values these all can be happen to be valid inline immediates. This fixes a later commit which starts checking the register class of the operands. llvm-svn: 224078
* Bitcode: Use unsigned char to record MDStringsDuncan P. N. Exon Smith2014-12-111-1/+1
| | | | | | | | | | `MDString`s can have arbitrary characters in them. Prevent an assertion that fired in `BitcodeWriter` because of sign extension by copying the characters into the record as `unsigned char`s. Based on a patch by Keno Fischer; fixes PR21882. llvm-svn: 224077
* return without temporary; NFCSanjay Patel2014-12-111-4/+1
| | | | llvm-svn: 224076
* Enable MachineVerifier in debug mode for X86, ARM, AArch64, Mips.Matthias Braun2014-12-114-20/+20
| | | | llvm-svn: 224075
* [X86] Add a temporary testcase for PR21876/r223996.Ahmed Bougacha2014-12-111-0/+1
| | | | llvm-svn: 224074
* Bitcode: Add METADATA_NODE and METADATA_VALUEDuncan P. N. Exon Smith2014-12-113-38/+31
| | | | | | | | | | | | | | | | This reflects the typelessness of `Metadata` in the bitcode format, removing types from all metadata operands. `METADATA_VALUE` represents a `ValueAsMetadata`, and always has two fields: the type and the value. `METADATA_NODE` represents an `MDNode`, and unlike `METADATA_OLD_NODE`, doesn't store types. It stores operands at their ID+1 so that `0` can reference `nullptr` operands. Part of PR21532. llvm-svn: 224073
* [PowerPC] Better lowering for add/or of a FrameIndexHal Finkel2014-12-112-30/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we have an add (or an or that is really an add), where one operand is a FrameIndex and the other operand is a small constant, we can combine the lowering of the FrameIndex (which is lowered as an add of the FI and a zero offset) with the constant operand. Amusingly, this is an old potential improvement entry from lib/Target/PowerPC/README.txt which had never been resolved. In short, we used to lower: %X = alloca { i32, i32 } %Y = getelementptr {i32,i32}* %X, i32 0, i32 1 ret i32* %Y as: addi 3, 1, -8 ori 3, 3, 4 blr and now we produce: addi 3, 1, -4 blr which is much more sensible. llvm-svn: 224071
* Bitcode: Add `OLD_` prefix to metadata node recordsDuncan P. N. Exon Smith2014-12-112-5/+5
| | | | | | | | I'm about to change these, so move the old ones out of the way. Part of PR21532. llvm-svn: 224070
* R600/SI: Use unordered equal instructionsMatt Arsenault2014-12-112-6/+2
| | | | llvm-svn: 224067
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-113-18/+9
| | | | | | | This saves a second compare and an and / or by using the unordered comparison instructions. llvm-svn: 224066
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-114-10/+19
| | | | llvm-svn: 224065
* [ASan] Change fake stack and local variables handling.Alexey Samsonov2014-12-111-44/+104
| | | | | | | | | | | | | | | | | | | | | | | | | This commit changes the way we get fake stack from ASan runtime (to find use-after-return errors) and the way we represent local variables: - __asan_stack_malloc function now returns pointer to newly allocated fake stack frame, or NULL if frame cannot be allocated. It doesn't take pointer to real stack as an input argument, it is calculated inside the runtime. - __asan_stack_free function doesn't take pointer to real stack as an input argument. Now this function is never called if fake stack frame wasn't allocated. - __asan_init version is bumped to reflect changes in the ABI. - new flag "-asan-stack-dynamic-alloca" allows to store all the function local variables in a dynamic alloca, instead of the static one. It reduces the stack space usage in use-after-return mode (dynamic alloca will not be called if the local variables are stored in a fake stack), and improves the debug info quality for local variables (they will not be described relatively to %rbp/%rsp, which are assumed to be clobbered by function calls). This flag is turned off by default for now, but I plan to turn it on after more testing. llvm-svn: 224062
* CodeGen: Stop using LeakDetector for MachineInstrDuncan P. N. Exon Smith2014-12-111-4/+0
| | | | | | | | | | | | Since `MachineInstr` is required to have a trivial destructor, it cannot remove itself from `LeakDetection`. Remove the calls. As it happens, this requirement is because `MachineFunction` allocates all `MachineInstr`s in a custom allocator; when the `MachineFunction` is destroyed they're dropped of the edge. There's no benefit to detecting leaks. llvm-svn: 224061
* IR: Store MDNodes in a separate LeakDetector containerDuncan P. N. Exon Smith2014-12-112-1/+19
| | | | | | | | | | | | | | | | This gives us better leak detection messages, like `Value` has. This also has the side effect of papering over a problem where `MachineInstr`s are added as garbage to the leak detector and then deleted without being removed. If `MDNode::getTemporary()` allocates an `MDNodeFwdDecl` in the same spot, the leak detector asserts. By separating `MDNode`s into their own container we lose that assertion. Since `MachineInstr` is required to have a trivial destructor, its usage of `LeakDetector` at all is pretty suspect. I'll be sending a patch soon to strip that out. llvm-svn: 224060
* [CodeGen] Add print and verify pass after each MachineFunctionPass by defaultMatthias Braun2014-12-1113-232/+175
| | | | | | | | | | | | | | | | | | | Previously print+verify passes were added in a very unsystematic way, which is annoying when debugging as you miss intermediate steps and allows bugs to stay unnotice when no verification is performed. To make this change practical I added the possibility to explicitely disable verification. I used this option on all places where no verification was performed previously (because alot of places actually don't pass the MachineVerifier). In the long term these problems should be fixed properly and verification enabled after each pass. I'll enable some more verification in subsequent commits. This is the 2nd attempt at this after realizing that PassManager::add() may actually delete the pass. llvm-svn: 224059
* AsmParser: Don't crash on an ill-formed MDNodeVectorDavid Majnemer2014-12-111-2/+2
| | | | llvm-svn: 224056
* [InstCombine][X86] Improved folding of calls to Intrinsic::x86_sse4a_insertqi.Andrea Di Biagio2014-12-111-1/+16
| | | | | | | | | | | | | | | | | | This patch teaches the instruction combiner how to fold a call to 'insertqi' if the 'length field' (3rd operand) is set to zero, and if the sum between field 'length' and 'bit index' (4th operand) is bigger than 64. From the AMD64 Architecture Programmer's Manual: 1. If the sum of the bit index + length field is greater than 64, then the results are undefined; 2. A value of zero in the field length is defined as a length of 64. This patch improves the existing combining logic for intrinsic 'insertqi' adding extra checks to address both point 1. and point 2. Differential Revision: http://reviews.llvm.org/D6583 llvm-svn: 224054
* AsmParser: Don't crash on an ill-formed MDNodeVectorDavid Majnemer2014-12-111-2/+2
| | | | llvm-svn: 224053
* Remove a convoluted way of calling close by moving the call to the only caller.Rafael Espindola2014-12-114-87/+24
| | | | | | As a bonus we can actually check the return value. llvm-svn: 224046
* This reverts commit r224043 and r224042.Rafael Espindola2014-12-1113-152/+212
| | | | | | check-llvm was failing. llvm-svn: 224045
* Silence static analyzer warnings in LLVMSupport.Michael Ilseman2014-12-112-0/+4
| | | | | | | The static analyzer catches a few potential bugs in LLVMSupport. Add in asserts to silence the warnings. llvm-svn: 224044
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