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* R600/SI: Add check for amdgcn triple forgotten in r225276.Tom Stellard2015-01-071-2/+3
| | | | llvm-svn: 225331
* Analysis: Reformulate WillNotOverflowUnsignedAdd for reusabilityDavid Majnemer2015-01-074-45/+41
| | | | | | | | WillNotOverflowUnsignedAdd's smarts will live in ValueTracking as computeOverflowForUnsignedAdd. It now returns a tri-state result: never overflows, always overflows and sometimes overflows. llvm-svn: 225329
* InstCombine: Just a small tidy-upDavid Majnemer2015-01-071-3/+2
| | | | llvm-svn: 225328
* [PowerPC] Transform a README.txt entry into a FIXMEHal Finkel2015-01-072-14/+9
| | | | | | | | | | Remove the README.txt entry regarding register allocation of CR logical ops, and replace it with a FIXME in PPCInstrInfo.td. The text in the README.txt was not really accurate, and thanks goes to Pat Haugen (and Bill Schmidt) from IBM for clarifying what was intended and highlighting the relevant text in the ISA specification. llvm-svn: 225325
* Revert r224935 "Refactor duplicated code. No intended functionality change."Lang Hames2015-01-0610-67/+87
| | | | | | | | This is affecting the behavior of some ObjC++ / AArch64 test cases on Darwin. Reverting to get the bots green while I track down the source of the changed behavior. llvm-svn: 225311
* R600/SI: Add combine for isinfinite patternMatt Arsenault2015-01-062-0/+57
| | | | llvm-svn: 225310
* R600/SI: Pattern match isinf to v_cmp_class instructionsMatt Arsenault2015-01-062-0/+34
| | | | llvm-svn: 225307
* R600/SI: Add basic DAG combines for fp_classMatt Arsenault2015-01-062-1/+50
| | | | llvm-svn: 225306
* R600/SI: Add class intrinsicMatt Arsenault2015-01-067-5/+82
| | | | llvm-svn: 225305
* Change the .ll syntax for comdats and add a syntactic sugar.Rafael Espindola2015-01-063-18/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make comdats always explicit in the IR, we decided to make the syntax a bit more compact for the case of a GlobalObject in a comdat with the same name. Just dropping the $name causes problems for @foo = globabl i32 0, comdat $bar = comdat ... and declare void @foo() comdat $bar = comdat ... So the syntax is changed to @g1 = globabl i32 0, comdat($c1) @g2 = globabl i32 0, comdat and declare void @foo() comdat($c1) declare void @foo() comdat llvm-svn: 225302
* [PowerPC] Reuse a load operand in int->fp conversionsHal Finkel2015-01-063-41/+142
| | | | | | | | | | | | | | | | | | | | | | | int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
* [Hexagon] Adding compound jump encodings.Colin LeMahieu2015-01-062-0/+266
| | | | llvm-svn: 225291
* R600/SI: Insert s_waitcnt before s_barrier instructions.Tom Stellard2015-01-061-1/+5
| | | | | | | This ensures that all memory operations are complete when all threads reach the barrier. llvm-svn: 225290
* R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaitsTom Stellard2015-01-061-0/+23
| | | | | | | | | | | | In DS write instructions, the address operand comes before the value operand(s) which is reversed from every other instruction type. The SIInsertWait assumed that the first use for each instruction was the value, so for DS write it was protecting the address operand with s_waitcnt instructions when it should have been protecting the value operand. llvm-svn: 225289
* Revert "Reapply: Teach SROA how to update debug info for fragmented variables."Adrian Prantl2015-01-061-60/+8
| | | | | | | | | because of a tsan buildbot failure. This reverts commit 225272. Fix should be coming soon. llvm-svn: 225288
* [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, ↵Colin LeMahieu2015-01-063-1/+101
| | | | | | dcfetch. llvm-svn: 225283
* This patch teaches IndVarSimplify to add nuw and nsw to certain kindsSanjoy Das2015-01-061-0/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of operations that provably don't overflow. For example, we can prove %civ.inc below does not sign-overflow. With this change, IndVarSimplify changes %civ.inc to an add nsw. define i32 @foo(i32* %array, i32* %length_ptr, i32 %init) { entry: %length = load i32* %length_ptr, !range !0 %len.sub.1 = sub i32 %length, 1 %upper = icmp slt i32 %init, %len.sub.1 br i1 %upper, label %loop, label %exit loop: %civ = phi i32 [ %init, %entry ], [ %civ.inc, %latch ] %civ.inc = add i32 %civ, 1 %cmp = icmp slt i32 %civ.inc, %length br i1 %cmp, label %latch, label %break latch: store i32 0, i32* %array %check = icmp slt i32 %civ.inc, %len.sub.1 br i1 %check, label %loop, label %break break: ret i32 %civ.inc exit: ret i32 42 } Differential Revision: http://reviews.llvm.org/D6748 llvm-svn: 225282
* [Hexagon] Adding encoding information for absolute address loads.Colin LeMahieu2015-01-061-124/+186
| | | | llvm-svn: 225279
* SelectionDAGBuilder: move constant initialization out of loopMehdi Amini2015-01-061-15/+19
| | | | | | | | | | No semantic change intended. Reviewers: resistor Differential Revision: http://reviews.llvm.org/D6834 llvm-svn: 225278
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-068-1/+46
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* Triple: Add amdgcn tripleTom Stellard2015-01-061-1/+8
| | | | | | | This will be used for AMD GPUs with the Graphics Core Next architecture, which are currently using by the r600 triple. llvm-svn: 225276
* R600/SI: Remove MachineFunction dump from AsmPrinterTom Stellard2015-01-061-17/+12
| | | | | | | The dump was dependent on a feature string, which meant that it couldn't be disabled or enable on a per compile basis. llvm-svn: 225275
* [CodeGenPrepare] Improved logic to speculate calls to cttz/ctlz.Andrea Di Biagio2015-01-061-6/+35
| | | | | | | | | | | | | | | | | | | | | This patch improves the logic added at revision 224899 (see review D6728) that teaches the backend when it is profitable to speculate calls to cttz/ctlz. The original algorithm conservatively avoided speculating more than one instruction from a basic block in a control flow grap modelling an if-statement. In particular, the only allowed instruction (excluding the terminator) was a call to cttz/ctlz. However, there are cases where we could be less conservative and still be able to speculate a call to cttz/ctlz. With this patch, CodeGenPrepare now tries to speculate a cttz/ctlz if the result is zero extended/truncated in the same basic block, and the zext/trunc instruction is "free" for the target. Added new test cases to CodeGen/X86/cttz-ctlz.ll Differential Revision: http://reviews.llvm.org/D6853 llvm-svn: 225274
* Reapply: Teach SROA how to update debug info for fragmented variables.Adrian Prantl2015-01-061-8/+60
| | | | | | | | | | This also rolls in the changes discussed in http://reviews.llvm.org/D6766. Defers migrating the debug info for new allocas until after all partitions are created. Thanks to Chandler for reviewing! llvm-svn: 225272
* Don't loop endlessly for MachO files with 0 ncmdsFilipe Cabecinhas2015-01-061-0/+3
| | | | llvm-svn: 225271
* [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing ↵Colin LeMahieu2015-01-061-2/+2
| | | | | | Uses [GP] maintains existing behavior. llvm-svn: 225270
* Implement a very basic colored syntax highlighting for llvm-dwarfdump.Adrian Prantl2015-01-065-21/+112
| | | | | | | | | | The color scheme is the same as the one used by the colorize dwarfdump script on Darwin. A new --color option can be used to forcibly turn color on or off. http://reviews.llvm.org/D6852 llvm-svn: 225269
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-065-239/+347
| | | | llvm-svn: 225267
* [ARM] Cleanup so_imm* tblgen defintionsAsiri Rathnayake2015-01-062-109/+43
| | | | | | | | | | | No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
* Convert fcmp with 0.0 from casted integers to icmpMatt Arsenault2015-01-061-4/+34
| | | | | | | | | | | | | | | | | | | This is already handled in general when it is known the conversion can't lose bits with smaller integer types casted into wider floating point types. This pattern happens somewhat often in GPU programs that cast workitem intrinsics to float, which are often compared with 0. Specifically handle the special case of compares with zero which should also be known to not lose information. I had a more general version of this which allows equality compares if the casted float is exactly representable in the integer, but I'm not 100% confident that is always correct. Also fold cases that aren't integers to true / false. llvm-svn: 225265
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-064-7/+40
| | | | | | Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
* InstCombine: Bitcast call arguments from/to pointer/integer typeDavid Majnemer2015-01-061-4/+13
| | | | | | | Try harder to get rid of bitcast'd calls by ptrtoint/inttoptr'ing arguments and return values when DataLayout says it is safe to do so. llvm-svn: 225254
* [X86] Make isel select the 2-byte register form of INC/DEC even in ↵Craig Topper2015-01-065-126/+78
| | | | | | | | non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering. Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness. llvm-svn: 225252
* [PowerPC] Remove old README.txt entry regarding struct passingHal Finkel2015-01-061-8/+0
| | | | | | | Because of how Clang represents structs as arrays (at least on non-Darwin platforms), and what SROA does, etc. this is no longer a problem. llvm-svn: 225251
* X86: Don't make illegal GOTTPOFF relocationsDavid Majnemer2015-01-062-0/+17
| | | | | | | | | | | | | "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF relocation target a movq or addq instruction. Prohibit the truncation of such loads to movl or addl. This fixes PR22083. Differential Revision: http://reviews.llvm.org/D6839 llvm-svn: 225250
* [PowerPC] Add some missing names in getTargetNodeNameHal Finkel2015-01-061-0/+7
| | | | | | These are used for debugging output; NFC. llvm-svn: 225249
* [PowerPC] Improve int_to_fp(fp_to_int(x)) combiningHal Finkel2015-01-062-30/+74
| | | | | | | | | The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
* [PM] Add a utility pass template that synthesizes the invalidation ofChandler Carruth2015-01-062-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | a specific analysis result. This is quite handy to test things, and will also likely be very useful for debugging issues. You could narrow down pass validation failures by walking these invalidate pass runs up and down the pass pipeline, etc. I've added support to the pass pipeline parsing to be able to create one of these for any analysis pass desired. Just adding this class uncovered one latent bug where the AnalysisManager CRTP base class had a hard-coded Module type rather than using IRUnitT. I've also added tests for invalidation and caching of analyses in a basic way across all the pass managers. These in turn uncovered two more bugs where we failed to correctly invalidate an analysis -- its results were invalidated but the key for re-running the pass was never cleared and so it was never re-run. Quite nasty. I'm very glad to debug this here rather than with a full system. Also, yes, the naming here is horrid. I'm going to update some of the names to be slightly less awful shortly. But really, I've no "good" ideas for naming. I'll be satisfied if I can get it to "not bad". llvm-svn: 225246
* [X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. ↵Craig Topper2015-01-061-2/+2
| | | | | | We always select the 8-bit size and let the assembler backend relax to the larger size. llvm-svn: 225243
* [X86] Make isel select the shorter form of jump instructions instead of the ↵Craig Topper2015-01-068-120/+97
| | | | | | | | long form. The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT. llvm-svn: 225242
* [PM] Add a collection of no-op analysis passes and switch the new passChandler Carruth2015-01-061-1/+4
| | | | | | | | | | | | manager tests to use them and be significantly more comprehensive. This, naturally, uncovered a bug where the CGSCC pass manager wasn't printing analyses when they were run. The only remaining core manipulator is I think an invalidate pass similar to the require pass. That'll be next. =] llvm-svn: 225240
* Remove dead variable.Eric Christopher2015-01-062-2/+1
| | | | llvm-svn: 225233
* Use the same call off of the TargetMachine rather than the subtarget.Eric Christopher2015-01-061-1/+1
| | | | llvm-svn: 225232
* Rewrite the Mips16HardFloat pass to avoid using the Subtarget.Eric Christopher2015-01-064-26/+18
| | | | llvm-svn: 225231
* Revert r225048: It broke ObjC on AArch64.Lang Hames2015-01-0612-152/+228
| | | | | | I've filed http://llvm.org/PR22100 to track this issue. llvm-svn: 225228
* Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.Brad Smith2015-01-061-5/+0
| | | | llvm-svn: 225227
* IR: Don't drop MDNode uniquing on null operandsDuncan P. N. Exon Smith2015-01-051-7/+2
| | | | | | | | | | Now that `LLVMContextImpl` can call `MDNode::dropAllReferences()` to prevent teardown madness, stop dropping uniquing just because an operand drops to null. Part of PR21532. llvm-svn: 225223
* Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"Duncan P. N. Exon Smith2015-01-052-2/+4
| | | | | | | | | This reverts commit r225213. It's failing on multiple buildbots [1][2]. [1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032 [2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/ llvm-svn: 225222
* [PowerPC] Remove old README.txt entryHal Finkel2015-01-051-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We no longer generate horrible code for the stated function: void f(signed char *a, _Bool b, _Bool c) { signed char t = 0; if (b) t = *a; if (c) *a = t; } for which we now generate: .L.f: andi. 5, 5, 1 cmpldi 1, 4, 0 li 5, 0 beq 1, .LBB0_2 lbz 5, 0(3) .LBB0_2: # %if.end bclr 4, 1, 0 stb 5, 0(3) blr so we don't need the README.txt entry. llvm-svn: 225217
* [X86][SSE] lowerVectorShuffleAsByteShift tidyupSimon Pilgrim2015-01-051-21/+14
| | | | | | Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead. llvm-svn: 225216
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