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* [ARM] Remove dead assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found by the Clang static analyzer. llvm-svn: 224586
* use -0.0 when creating an fneg instructionSanjay Patel2014-12-191-1/+1
| | | | | | | | | | | | | | | | | | | Backends recognize (-0.0 - X) as the canonical form for fneg and produce better code. Eg, ppc64 with 0.0: lis r2, ha16(LCPI0_0) lfs f0, lo16(LCPI0_0)(r2) fsubs f1, f0, f1 blr vs. -0.0: fneg f1, f1 blr Differential Revision: http://reviews.llvm.org/D6723 llvm-svn: 224583
* Revert "[InstCombine] Fix visitSwitchInst to use right operand types for sub ↵Bruno Cardoso Lopes2014-12-191-4/+2
| | | | | | | | | | | | | cstexpr" Reverts commit r224574 to appease buildbots: The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. llvm-svn: 224576
* [InstCombine] Fix visitSwitchInst to use right operand types for sub cstexprBruno Cardoso Lopes2014-12-191-2/+4
| | | | | | | | | | | | | The visitSwitchInst generates SUB constant expressions to recompute the switch condition. When truncating the condition to a smaller type, SUB expressions should use the previous type (before trunc) for both operands. This fixes an assertion crash. Differential Revision: http://reviews.llvm.org/D6644 rdar://problem/19191835 llvm-svn: 224574
* Remove redundant assignment.Tilmann Scheller2014-12-191-1/+0
| | | | | | Found with the Clang static analyzer. llvm-svn: 224570
* Rename MapValue(Metadata*) to MapMetadata()Duncan P. N. Exon Smith2014-12-194-21/+21
| | | | | | | | Instead of reusing the name `MapValue()` when mapping `Metadata`, use `MapMetadata()`. The old name doesn't make much sense after the `Metadata`/`Value` split. llvm-svn: 224566
* [Object] Don't crash on empty export lists.Juergen Ributzka2014-12-191-1/+4
| | | | | | | | | | | | Summary: This fixes the exports iterator if the export list is empty. Reviewers: Bigcheese, kledzik Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6732 llvm-svn: 224563
* RegisterCoalescer: rewrite eliminateUndefCopy().Matthias Braun2014-12-191-29/+64
| | | | | | | | This also fixes problems with undef copies of subregisters. I can't attach a testcase for that as none of the targets in trunk has subregister liveness tracking enabled. llvm-svn: 224560
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-196-37/+138
| | | | llvm-svn: 224556
* Explain why LLVM is emitting a DW_AT_containing_type inside of a class.Adrian Prantl2014-12-191-0/+2
| | | | llvm-svn: 224555
* ConstantFold: Shifting undef by zero results in undefDavid Majnemer2014-12-181-0/+9
| | | | llvm-svn: 224553
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-186-134/+33
| | | | llvm-svn: 224552
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-186-33/+134
| | | | llvm-svn: 224550
* Add printing the LC_SUB_UMBRELLA load command with llvm-objdump’s ↵Kevin Enderby2014-12-181-0/+5
| | | | | | -private-headers. llvm-svn: 224548
* Instead of explicitely comparing both lowercase and uppercase variants.Roman Divacky2014-12-181-81/+1
| | | | | | | | | | .lower() the Name and compare only the lowecase. Removing 81 compares/lines of code. This changes the accepted string to be mixed lower/upper case but it should be ok. Discussed with Jim Grosbach. llvm-svn: 224547
* fix formatting; NFCSanjay Patel2014-12-181-8/+4
| | | | llvm-svn: 224542
* LiveIntervalAnalysis: Cleanup computeDeadValuesMatthias Braun2014-12-181-24/+33
| | | | | | | | | - This also fixes a bug introduced in r223880 where values were not correctly marked as Dead anymore. - Cleanup computeDeadValues(): split up SubRange code variant, simplify arguments. llvm-svn: 224538
* Add printing the LC_SUB_FRAMEWORK load command with llvm-objdump’s ↵Kevin Enderby2014-12-181-0/+4
| | | | | | -private-headers. llvm-svn: 224534
* Add missing implementation of 'sys::path::is_other' to the support library.Juergen Ributzka2014-12-181-0/+8
| | | | | | | The header claims that this function exists, but the linker wasn't too happy about it not being in the library. llvm-svn: 224527
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-181-4/+8
| | | | | | | | | Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 llvm-svn: 224524
* ARM: fix an off-by-one in the register list accessSaleem Abdulrasool2014-12-181-2/+2
| | | | | | | | | Fix an off-by-one access introduced in 224502 for push.w and pop.w with single register operands. Add test cases for both scenarios. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224521
* [AVX512] Enable FP arithmetic lowering for AVX512VL subsets.Robert Khasanov2014-12-184-2/+105
| | | | | | | Added RegOp2MemOpTable4 to transform 4th operand from register to memory in merge-masked versions of instructions. Added lowering tests. llvm-svn: 224516
* [Msan] Generalize instrumentation code to support FreeBSD mappingViktor Kutuzov2014-12-181-27/+106
| | | | | | Differential Revision: http://reviews.llvm.org/D6666 llvm-svn: 224514
* Fix Visual C++ error "'llvm::make_unique' : ambiguous call to overloaded ↵Yaron Keren2014-12-181-2/+2
| | | | | | function". llvm-svn: 224506
* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-181-15/+76
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* [SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and useChandler Carruth2014-12-181-1/+3
| | | | | | a lambda now that we have them. llvm-svn: 224500
* Modernize the getStreamedBitcodeModule interface a bit. NFC.Rafael Espindola2014-12-181-18/+14
| | | | llvm-svn: 224499
* [PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. ↵Craig Topper2014-12-181-12/+12
| | | | | | Only put the anonymous namespace around classes. NFC. llvm-svn: 224498
* [X86] Use correct opsize on indirect call and jump aliases.Craig Topper2014-12-181-4/+4
| | | | llvm-svn: 224497
* [X86] Don't use PS prefix on LDMXCSR/STMXCSR.Craig Topper2014-12-181-6/+8
| | | | | | Near as I can tell prefixes are ignored on these instructions except for a comment in the Intel docs about 0xf3. Binutils disassembler seems to ignore prefixes on these instructions. Our disassembler still doesn't distinguish PS and "no prefix" well enough for this to make a functional change, but it helps with experiments I'm doing on a potential new disassembler table builder. llvm-svn: 224496
* [X86] Remove unnecessary 'In64BitMode' predicate for instructions that ↵Craig Topper2014-12-181-14/+11
| | | | | | already indicate use of REX.W. llvm-svn: 224495
* Add a corresponding '@LOCAL' parse to match r224415.Justin Hibbits2014-12-181-0/+1
| | | | | | Pointed out by Jim Grosbach. llvm-svn: 224494
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-186-61/+84
| | | | | | | | | | | | | of the abi we should be using. For targets that don't use the option there's no change, otherwise this allows external users to set the ABI via string and avoid some of the -backend-option pain in clang. Use this option to move the ABI for the ARM port from the Subtarget to the TargetMachine and update the testcases accordingly since it's no longer valid to set via -mattr. llvm-svn: 224492
* Model ARM backend ABI selection after the front end code doing theEric Christopher2014-12-181-18/+34
| | | | | | | | | | | | | | same. This will change the "bare metal" ABI from APCS to AAPCS. The only difference between the front and back end code is that the code for Triple::GNU was added for environment. That will migrate to the front end shortly. Tests updated with the ABI they were originally testing in the case of bare metal (e.g. -mtriple armv7) or with a -gnu for arm-linux triples. llvm-svn: 224489
* Reapply "Linker: Drop superseded subprograms"Duncan P. N. Exon Smith2014-12-181-0/+54
| | | | | | | | | | | | | | | | | | | | This reverts commit r224416, reapplying r224389. The buildbots hadn't recovered after my revert, waiting until David reverted a couple of his commits. It looks like it was just bad timing (where we were both modifying code related to the same assertion). Trying again... Here's the original text: When a function gets replaced by `ModuleLinker`, drop superseded subprograms. This ensures that the "first" subprogram pointing at a function is the same one that `!dbg` references point at. This is a stop-gap fix for PR21910. Notably, this fixes Release+Asserts bootstraps that are currently asserting out in `LexicalScopes::initialize()` due to the explicit instantiations in `lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion. llvm-svn: 224487
* Add printing the LC_LINKER_OPTION load command with llvm-objdump’s ↵Kevin Enderby2014-12-182-6/+6
| | | | | | | | | | -private-headers. Also corrected the name of the load command to not end in an ’S’ as well as corrected the name of the MachO::linker_option_command struct and other places that had the word option as plural which did not match the Mac OS X headers. llvm-svn: 224485
* IR: Handle self-referencing DICompositeTypes in DIBuilderDuncan P. N. Exon Smith2014-12-181-0/+32
| | | | | | | | | | | | | | | | | | | | Add API to DIBuilder to handle self-referencing `DICompositeType`s. Self-references aren't expected in the debug info graph, and we take advantage of that by only calling `resolveCycles()` on nodes that were once forward declarations (otherwise, DIBuilder needs an expensive tracking reference to every unresolved node it creates, which in cyclic graphs is *all of them*). However, clang seems to create self-referencing `DICompositeType`s. Add API to manage this safely. The paired commit to clang will include the regression test. I'll make the `DICompositeType` API `private` in a follow-up to prevent misuse (I've separated that to prevent build failures from missing the clang commit). llvm-svn: 224482
* LTO: Lazy-load LTOModule in local contextsDuncan P. N. Exon Smith2014-12-171-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Start lazy-loading `LTOModule`s that own their contexts. These can only really be used for parsing symbols, so its unnecessary to ever materialize their functions. I looked into using `IRObjectFile::create()` and optionally calling `materializAllPermanently()` afterwards, but this turned out to be awkward. - The default target triple and data layout logic needs to happen *before* the call to `IRObjectFile::IRObjectFile()`, but after `Module` was created. - I tried passing a lambda in to do the module initialization, but this seemed to require threading the error message from `TargetRegistry::lookupTarget()` through `std::error_code`. - I also looked at setting `errMsg` directly from within the lambda, but this didn't look any better. (I guess there's a reason we weren't already using that function.) llvm-svn: 224466
* [sanitizer] allow -fsanitize-coverage=N w/ -fsanitize=leak, llvm partKostya Serebryany2014-12-171-4/+2
| | | | llvm-svn: 224463
* RegisterCoalescer: Fix stripCopies() picking up main range instead of ↵Matthias Braun2014-12-171-50/+78
| | | | | | | | | | subregister range This fixes a problem where stripCopies() would switch to values in the main liverange when it crossed a copy instruction. However when joining subranges we need to stay in the respective subregister ranges. llvm-svn: 224461
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-178-46/+126
| | | | llvm-svn: 224458
* [Hexagon] Reconfiguring register alternate names.Colin LeMahieu2014-12-171-13/+9
| | | | llvm-svn: 224455
* Enable the P8Model entryWill Schmidt2014-12-171-1/+1
| | | | | | | | This was missed last time around, for the P8 Instruction Scheduling changes (223257). This will hook the P8Model entry in so those changes will actually be used. llvm-svn: 224452
* ExecutionDepsFix: Correctly handle wide registers.Matthias Braun2014-12-171-70/+71
| | | | | | | | | | | | | | The ExecutionDepsFix previously mapped each register to 1 or zero registers of the register class it was called with and therefore simulating liveness for. This was problematic for cases involving wider registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx registers. In these cases the wide register would get mapped to the last matching D register, while it should have been all matching D registers. This commit changes the AliasMap to use a SmallVector to map registers to potentially multiple destination regclass registers. This is required to avoid regressions with subregister liveness tracking enabled. llvm-svn: 224447
* Random Number Generator Refactoring (removing from Module)JF Bastien2014-12-172-30/+32
| | | | | | | | | | This patch removes the RNG from Module. Passes should instead create a new RNG for their use as needed. Patch by Stephen Crane @rinon. Differential revision: http://reviews.llvm.org/D4377 llvm-svn: 224444
* [NVPTX] Fix bugs related to isSingleValueTypeJingyue Wu2014-12-171-13/+2
| | | | | | | | | | | | | | | | | | | | Summary: With isSingleValueType starting to treat vector types as single-value types, code that uses this interface needs to be updated. Test Plan: vector-global.ll nvcl-param-align.ll Reviewers: jholewinski Reviewed By: jholewinski Subscribers: llvm-commits, meheff, eliben, jholewinski Differential Revision: http://reviews.llvm.org/D6573 llvm-svn: 224440
* ARM: correct an off-by-one in an assertSaleem Abdulrasool2014-12-171-1/+4
| | | | | | | | The assert was off-by-one, resulting in failures for valid input. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224432
* [DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.Michael Kuperstein2014-12-173-11/+34
| | | | | | | | | | This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors. This fixes PR15872 and provides a partial fix for PR21711. Differential Revision: http://reviews.llvm.org/D6678 llvm-svn: 224429
* MipsABIInfo class is used in different libraries. Moving the files to ↵Vladimir Medic2014-12-175-2/+2
| | | | | | MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes. llvm-svn: 224427
* [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.Toma Tabacu2014-12-174-4/+28
| | | | | | | | | | | | | | | | | | | | Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
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