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* Add a hidden option to PHIElimination to split all critical edges. This isCameron Zwarich2013-02-121-4/+9
| | | | | | | particularly useful for catching issues with architectures that have exotic terminators like MIPS. llvm-svn: 174938
* Add blocks to the LiveIntervalAnalysis RegMaskBlocks array when splittingCameron Zwarich2013-02-121-2/+6
| | | | | | a critical edge. llvm-svn: 174936
* Fix the updating of LiveIntervals after splitting a critical edge. PHI operandCameron Zwarich2013-02-121-12/+3
| | | | | | | live ranges should always be extended, and the only successor that should be considered for extension of other ranges is the target of the split edge. llvm-svn: 174935
* Check type for legality before forming a select from loads.Pete Cooper2013-02-121-1/+3
| | | | | | | | Sorry for the lack of a test case. I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later. I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness. llvm-svn: 174934
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+33
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 llvm-svn: 174933
* Cost model: Add check for reverse shuffles to CostModel analysisArnold Schwaighofer2013-02-121-0/+18
| | | | | | | | | | Check for reverse shuffles in the CostModel analysis pass and query TargetTransform info accordingly. This allows us we can write test cases for reverse shuffles. radar://13171406 llvm-svn: 174932
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-1/+37
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* Update error message due to previous commit, r174926.Chad Rosier2013-02-121-1/+3
| | | | llvm-svn: 174927
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-14/+47
| | | | | | Part of rdar://12470373 llvm-svn: 174926
* DIBuilder: make the return type of createBasicType more specificDavid Blaikie2013-02-121-4/+4
| | | | llvm-svn: 174924
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-4/+2
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* BBVectorize: Don't over-search when building the dependency mapHal Finkel2013-02-111-2/+10
| | | | | | | | | | | | | When building the pairable-instruction dependency map, don't search past the last pairable instruction. For large blocks that have been divided into multiple instruction groups, searching past the last instruction in each group is very wasteful. This gives a 32% speedup on the csa.ll test case from PR15222 (when using 50 instructions in each group). No functionality change intended. llvm-svn: 174915
* BBVectorize: Omit unnecessary entries in PairableInstUsersHal Finkel2013-02-111-1/+3
| | | | | | | | | | | This map is queried only for instructions in pairs of pairable instructions; so make sure that only pairs of pairable instructions are added to the map. This gives a 3.5% speedup on the csa.ll test case from PR15222. No functionality change intended. llvm-svn: 174914
* [mips] Expand pseudo instructions before they are emitted inAkira Hatanaka2013-02-111-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | MipsCodeEmitter.cpp. JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not called when the old JIT is used. This fixes the following tests which have been failing on llvm-mips-linux builder: LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll LLVM :: ExecutionEngine__hello2.ll LLVM :: ExecutionEngine__stubs.ll LLVM :: ExecutionEngine__test-branch.ll LLVM :: ExecutionEngine__test-call.ll LLVM :: ExecutionEngine__test-common-symbols.ll LLVM :: ExecutionEngine__test-loadstore.ll LLVM :: ExecutionEngine__test-loop.ll llvm-svn: 174912
* Rename AttributeSets to AttributeGroups so that it's more meaningful.Bill Wendling2013-02-113-41/+41
| | | | llvm-svn: 174911
* Use a std::map so that we record the group ID.Bill Wendling2013-02-112-7/+8
| | | | llvm-svn: 174910
* [mips] Fix indentation.Akira Hatanaka2013-02-111-41/+39
| | | | llvm-svn: 174907
* Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> ↵Michael Ilseman2013-02-111-5/+16
| | | | | | bitcast X to ... llvm-svn: 174905
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
| | | | llvm-svn: 174901
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-4/+4
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* BBVectorize: Eliminate one more restricted linear searchHal Finkel2013-02-111-27/+31
| | | | | | | | | | This eliminates one more linear search over a range of std::multimap entries. This gives a 22% speedup on the csa.ll test case from PR15222. No functionality change intended. llvm-svn: 174893
* R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.Michel Danzer2013-02-111-15/+9
| | | | | | | | | | | | | The modifiers don't seem to have any effect with V_MOV_B32, supposedly it's meant to just move bits untouched. Fixes 46 piglit tests with radeonsi, though unfortunately 11 of those had just regressed because they started using the clamp modifier. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174890
* [asan] added a flag -mllvm asan-short-64bit-mapping-offset=1 (0 by default)Kostya Serebryany2013-02-111-2/+8
| | | | | | | | | | This flag makes asan use a small (<2G) offset for 64-bit asan shadow mapping. On x86_64 this saves us a register, thus achieving ~2/3 of the zero-base-offset's benefits in both performance and code size. Thanks Jakub Jelinek for the idea. llvm-svn: 174886
* AArch64: fix build on some MSVC versionsTim Northover2013-02-111-3/+3
| | | | | | | | | | | | | | | This does two things: It removes a call to abs() which may have "long long" parameter on Windows, which is not necessarily available in C++03. It also corrects the signedness of Amount, which was relying on implementation-defined conversions previously. Code was already tested (albeit in an implemnetation defined way) so no extra tests. llvm-svn: 174885
* AArch64: Simplify logic in deciding whether bfi is validTim Northover2013-02-111-6/+1
| | | | | | | | Previous code had a confusing comment which was mostly an implementation detail. This condition corresponds to "lsb up to register width" and "width not ridiculous". llvm-svn: 174877
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-112-18/+218
| | | | | | | | | This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. llvm-svn: 174871
* Add support for updating LiveIntervals to ↵Cameron Zwarich2013-02-112-1/+69
| | | | | | | | | | | | | | | MachineBasicBlock::SplitCriticalEdge(). This is currently a bit hairier than it needs to be, since depending on where the split block resides the end ListEntry of the split block may be the end ListEntry of the original block or a new entry. Some changes to the SlotIndexes updating should make it possible to eliminate the two cases here. This also isn't as optimized as it could be. In the future Liveinterval should probably get a flag that indicates whether the LiveInterval is within a single basic block. We could ignore all such intervals when splitting an edge. llvm-svn: 174870
* Update SlotIndexes after updateTerminator() possibly removes instructions. I amCameron Zwarich2013-02-111-0/+24
| | | | | | really trying to avoid piping SlotIndexes through to RemoveBranch() and friends. llvm-svn: 174869
* Add support for printing out the attribute groups.Bill Wendling2013-02-113-17/+88
| | | | | | | | | | | | This emits the attribute groups that are used by the functions. (It currently doesn't print out return type or parameter attributes within attribute groups.) Note: The functions still retrieve their attributes from the "old" bitcode format (using the deprecated 'Raw()' method). This means that string attributes within an attribute group will not show up during a disassembly. This will be addressed in a future commit. llvm-svn: 174867
* [tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany2013-02-117-3/+19
| | | | llvm-svn: 174864
* Revert "Rename LLVMContext diagnostic handler types and functions."Bob Wilson2013-02-114-23/+25
| | | | | | | | | This reverts my commit 171047. Now that I've removed my misguided attempt to support backend warnings, these diagnostics are only about inline assembly. It would take quite a bit more work to generalize them properly, so I'm just reverting this. llvm-svn: 174860
* BBVectorize: Remove the linear searches from pair connection searchingHal Finkel2013-02-111-24/+11
| | | | | | | | | This removes the last of the linear searches over ranges of std::multimap iterators, giving a 7% speedup on the doduc.bc input from PR15222. No functionality change intended. llvm-svn: 174859
* BBVectorize: Avoid linear searches within the load-move setHal Finkel2013-02-111-20/+30
| | | | | | | | | This is another cleanup aimed at eliminating linear searches in ranges of std::multimap. No functionality change intended. llvm-svn: 174858
* BBVectorize: isa/cast cleanup in getInstructionTypesHal Finkel2013-02-111-4/+4
| | | | | | | | | | Profiling suggests that getInstructionTypes is performance-sensitive, this cleans up some double-casting in that function in favor of using dyn_cast. No functionality change intended. llvm-svn: 174857
* BBVectorize: Make the bookkeeping to support full cycle checking less expensiveHal Finkel2013-02-111-14/+25
| | | | | | | | | | | By itself, this does not have much of an effect, but only because in the default configuration the full cycle checks are used only for small problem sizes. This is part of a general cleanup of uses of iteration over std::multimap ranges only for the purpose of checking membership. No functionality change intended. llvm-svn: 174856
* Currently, codegen may spent some time in SDISel passes even if an entireEvan Cheng2013-02-113-8/+114
| | | | | | | | | | | | | | function is successfully handled by fast-isel. That's because function arguments are *always* handled by SDISel. Introduce FastLowerArguments to allow each target to provide hook to handle formal argument lowering. As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It completely eliminates the need for SDISel for trivial functions. rdar://13163905 llvm-svn: 174855
* Remove unnecessary code.Evan Cheng2013-02-111-4/+0
| | | | llvm-svn: 174854
* Fix unnecessary removal of const through cast machineryDavid Blaikie2013-02-113-14/+14
| | | | | | | | I have some uncommitted changes to the cast code that catch this sort of thing at compile-time but I still need to do some other cleanup before I can enable it. llvm-svn: 174853
* Spelling correctionJoel Jones2013-02-101-1/+1
| | | | llvm-svn: 174852
* Fix the unused but nearly correct method SlotIndexes::insertMBBInMaps() and addCameron Zwarich2013-02-101-0/+14
| | | | | | | | support for updating SlotIndexes to MachineBasicBlock::SplitCriticalEdge(). This calls renumberIndexes() every time; it should be improved to only renumber locally. llvm-svn: 174851
* Abstract the liveness checking in PHIElimination::SplitPHIEdges() to supportCameron Zwarich2013-02-101-2/+37
| | | | | | both LiveVariables and LiveIntervals. llvm-svn: 174850
* Add support in the bitcode reader to read the attribute groups.Bill Wendling2013-02-102-0/+82
| | | | | | | | | This reads the attribute groups. It currently doesn't do anything with them. NOTE: In the commit to the bitcode writer, the format *may* change in the near future. Which means that this code would also change. llvm-svn: 174849
* The 'Raw' method cannot handle 'string' attributes. Don't even try.Bill Wendling2013-02-101-0/+4
| | | | llvm-svn: 174848
* Eat the alignment keyword if we're in an attribute group.Bill Wendling2013-02-101-0/+2
| | | | llvm-svn: 174846
* Add code for emitting the attribute groups.Bill Wendling2013-02-101-0/+53
| | | | | | | | | This is some initial code for emitting the attribute groups into the bitcode. NOTE: This format *may* change! Do not rely upon the attribute groups' bitcode not changing. llvm-svn: 174845
* Add support for attribute groups in the value enumerator.Bill Wendling2013-02-102-0/+24
| | | | | | | Attribute groups are essentially all AttributeSets which are used by the program. Enumerate them here. llvm-svn: 174844
* Test Commit - Remove some trailing whitespace in R600Instructions.tdVincent Lejeune2013-02-101-6/+6
| | | | llvm-svn: 174839
* Handle string attributes in the AttrBuilder.Bill Wendling2013-02-101-1/+5
| | | | llvm-svn: 174834
* Use a 'continue' here to stop from double lexing.Bill Wendling2013-02-101-1/+1
| | | | llvm-svn: 174833
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