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* [Hexagon] Use composition instead of inheritance from STL typesBenjamin Kramer2015-07-184-50/+27
| | | | | | | | The standard containers are not designed to be inherited from, as illustrated by the MSVC hacks for NodeOrdering. No functional change intended. llvm-svn: 242616
* [PM/AA] Remove the addEscapingUse update API that won't be easy toChandler Carruth2015-07-185-56/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | directly model in the new PM. This also was an incredibly brittle and expensive update API that was never fully utilized by all the passes that claimed to preserve AA, nor could it reasonably have been extended to all of them. Any number of places add uses of values. If we ever wanted to reliably instrument this, we would want a callback hook much like we have with ValueHandles, but doing this for every use addition seems *extremely* expensive in terms of compile time. The only user of this update mechanism is GlobalsModRef. The idea of using this to keep it up to date doesn't really work anyways as its analysis requires a symmetric analysis of two different memory locations. It would be very hard to make updates be sufficiently rigorous to *guarantee* symmetric analysis in this way, and it pretty certainly isn't true today. However, folks have been using GMR with this update for a long time and seem to not be hitting the issues. The reported issue that the update hook fixes isn't even a problem any more as other changes to GetUnderlyingObject worked around it, and that issue stemmed from *many* years ago. As a consequence, a prior patch provided a flag to control the unsafe behavior of GMR, and this patch removes the update mechanism that has questionable compile-time tradeoffs and is causing problems with moving to the new pass manager. Note the lack of test updates -- not one test in tree actually requires this update, even for a contrived case. All of this was extensively discussed on the dev list, this patch will just enact what that discussion decides on. I'm sending it for review in part to show what I'm planning, and in part to show the *amazing* amount of work this avoids. Every call to the AA here is something like three to six indirect function calls, which in the non-LTO pipeline never do any work! =[ Differential Revision: http://reviews.llvm.org/D11214 llvm-svn: 242605
* [libFuzzer] require the files and directories passed to the fuzzer to existKostya Serebryany2015-07-181-2/+8
| | | | llvm-svn: 242596
* [asan] Fix shadow mapping on Android/AArch64.Evgeniy Stepanov2015-07-171-4/+6
| | | | | | | | | Instrumentation and the runtime library were in disagreement about ASan shadow offset on Android/AArch64. This fixes a large number of existing tests on Android/AArch64. llvm-svn: 242595
* ARM: Enable MachineScheduler and disable PostRAScheduler for swift.Matthias Braun2015-07-173-1038/+14
| | | | | | | | | | | | | | | | | | | | | | | Reapply r242500 now that the swift schedmodel includes LDRLIT. This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 llvm-svn: 242588
* ARM: Add scheduling information for LDRLIT instructions to swift scheduling ↵Matthias Braun2015-07-171-0/+7
| | | | | | | | | | | model These pseudo instructions are only lowered after register allocation and are therefore still present when the machine scheduler runs. Add a run: line to a testcase that uses the uncommon flags necessary to actually produce a LDRLIT instruction on swift. llvm-svn: 242587
* [RAGreedy] Add an experimental deferred spilling feature.Quentin Colombet2015-07-171-6/+37
| | | | | | | | | | | | | | | | The idea of deferred spilling is to delay the insertion of spill code until the very end of the allocation. A "candidate" to spill variable might not required to be spilled because of other evictions that happened after this decision was taken. The spirit is similar to the optimistic coloring strategy implemented in Preston and Briggs graph coloring algorithm. For now, this feature is highly experimental. Although correct, it would require much more modification to properly model the effect of spilling. Anyway, this early patch helps prototyping this feature. Note: The test case cannot unfortunately be reduced and is probably fragile. llvm-svn: 242585
* MIR Parser: Allow the dollar characters in all of the identifier tokens.Alex Lorenz2015-07-171-1/+4
| | | | | | | | | | This commit modifies the machine instruction lexer so that it now accepts the '$' characters in identifier tokens. This change makes the syntax for unquoted global value tokens consistent with the syntax for the global idenfitier tokens in the LLVM's assembly language. llvm-svn: 242584
* AsmParser: Add a function to parse a standalone constant value.Alex Lorenz2015-07-173-0/+50
| | | | | | | | | | | | | | This commit extends the interface provided by the AsmParser library by adding a function that allows the user to parse a standalone contant value. This change is useful for MIR serialization, as it will allow the MIR Parser to parse the constant values in a machine constant pool. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10280 llvm-svn: 242579
* [asan] Add a comment explaining why non-instrumented allocas are moved.Kuba Brecka2015-07-171-0/+3
| | | | | | Addition to r242510. llvm-svn: 242561
* MergeFuncs: Transfer the function parameter attributes to the call siteArnold Schwaighofer2015-07-171-0/+1
| | | | | | rdar://21516488 llvm-svn: 242558
* Revert "ARM: Enable MachineScheduler and disable PostRAScheduler for swift."Adam Nemet2015-07-173-14/+1038
| | | | | | | | | This reverts commit r242500. It broke some internal tests and Matthias asked me to revert it while he is investigating. llvm-svn: 242553
* Use llvm_unreachable() instead of report_fatal_error() if the machine model ↵Matthias Braun2015-07-171-5/+3
| | | | | | | | | is incomplete This error is for developers only so it makes sense to abort and get a backtrace. llvm-svn: 242551
* [ARM] Use [SU]ABSDIFF nodes instead of intrinsics for VABD/VABAJames Molloy2015-07-172-8/+22
| | | | | | | No functional change, but it preps codegen for the future when SABSDIFF will start getting generated in anger. llvm-svn: 242546
* [AArch64] Use [SU]ABSDIFF nodes instead of intrinsics for ABD/ABAJames Molloy2015-07-172-26/+37
| | | | | | | No functional change, but it preps codegen for the future when SABSDIFF will start getting generated in anger. llvm-svn: 242545
* Use inbounds GEPs for memcpy and memset loweringEli Bendersky2015-07-171-8/+10
| | | | | | Follow-up on discussion in http://reviews.llvm.org/D11220 llvm-svn: 242542
* Add support for producing thin archives in llvm-lib.Rafael Espindola2015-07-172-1/+3
| | | | | | I will send an entry in docs/CommandGuide for review today. llvm-svn: 242533
* Edited the CPUNames table of TargetParserAlexandros Lamprineas2015-07-171-3/+1
| | | | | | | | | - Changed the default FPU of cortex-m4. - Removed "cortex-m4f" entry. Currently not supported. Change-Id: I73121e358aa9e7ba68eb001c2143df390ff2352a Phabricator: http://reviews.llvm.org/D11100 llvm-svn: 242528
* Make global aliases have symbol size equal to their typeJohn Brawn2015-07-171-0/+10
| | | | | | | | | | This is mainly for the benefit of GlobalMerge, so that an alias into a MergedGlobals variable has the same size as the original non-merged variable. Differential Revision: http://reviews.llvm.org/D10837 llvm-svn: 242520
* [PM/AA] Disable the core unsafe aspect of GlobalsModRef in the face ofChandler Carruth2015-07-171-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | basic changes to the IR such as folding pointers through PHIs, Selects, integer casts, store/load pairs, or outlining. This leaves the feature available behind a flag. This flag's default could be flipped if necessary, but the real-world performance impact of this particular feature of GMR may not be sufficiently significant for many folks to want to run the risk. Currently, the risk here is somewhat mitigated by half-hearted attempts to update GlobalsModRef when the rest of the optimizer changes something. However, I am currently trying to remove that update mechanism as it makes migrating the AA infrastructure to a form that can be readily shared between new and old pass managers very challenging. Without this update mechanism, it is possible that this still unlikely failure mode will start to trip people, and so I wanted to try to proactively avoid that. There is a lengthy discussion on the mailing list about why the core approach here is flawed, and likely would need to look totally different to be both reasonably effective and resilient to basic IR changes occuring. This patch is essentially the first of two which will enact the result of that discussion. The next patch will remove the current update mechanism. Thanks to lots of folks that helped look at this from different angles. Especial thanks to Michael Zolotukhin for doing some very prelimanary benchmarking of LTO without GlobalsModRef to get a rough idea of the impact we could be facing here. So far, it looks very small, but there are some concerns lingering from other benchmarking. The default here may get flipped if performance results end up pointing at this as a more significant issue. Also thanks to Pete and Gerolf for reviewing! Differential Revision: http://reviews.llvm.org/D11213 llvm-svn: 242512
* [asan] Fix invalid debug info for promotable allocasKuba Brecka2015-07-171-1/+7
| | | | | | | | | | Since r230724 ("Skip promotable allocas to improve performance at -O0"), there is a regression in the generated debug info for those non-instrumented variables. When inspecting such a variable's value in LLDB, you often get garbage instead of the actual value. ASan instrumentation is inserted before the creation of the non-instrumented alloca. The only allocas that are considered standard stack variables are the ones declared in the first basic-block, but the initial instrumentation setup in the function breaks that invariant. This patch makes sure uninstrumented allocas stay in the first BB. Differential Revision: http://reviews.llvm.org/D11179 llvm-svn: 242510
* AArch64: add comment missed out from earlier patch.Tim Northover2015-07-171-0/+4
| | | | | | Helps explain some of the background behind this bit of code. llvm-svn: 242503
* ARM: Enable MachineScheduler and disable PostRAScheduler for swift.Matthias Braun2015-07-173-1038/+14
| | | | | | | | | | | | | | | | | | | | | This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 llvm-svn: 242500
* Only do fmul (fadd x, x), c combine if the fadd only has one useMatt Arsenault2015-07-171-1/+3
| | | | | | This was increasing the instruction count if the fadd has multiple uses. llvm-svn: 242498
* Use small encodings for constants when possible.Rafael Espindola2015-07-171-3/+3
| | | | llvm-svn: 242493
* MIR Serialization: Serialize the frame setup machine instruction flag.Alex Lorenz2015-07-174-6/+15
| | | | llvm-svn: 242491
* MIR Serialization: Serialize the frame index machine operands.Alex Lorenz2015-07-166-20/+152
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242487
* Add new constructors for LoopInfo/DominatorTree/BFI/BPICong Hou2015-07-162-0/+12
| | | | | | | | | | | | | | | | | Those new constructors make it more natural to construct an object for a function. For example, previously to build a LoopInfo for a function, we need four statements: DominatorTree DT; LoopInfo LI; DT.recalculate(F); LI.analyze(DT); Now we only need one statement: LoopInfo LI(DominatorTree(F)); http://reviews.llvm.org/D11274 llvm-svn: 242486
* Arm: Don't define a label twice with two setjmps in a function.Matthias Braun2015-07-162-14/+3
| | | | | | | | | | Constructing a name based on the function name didn't give us a unique symbol if we had more than one setjmp in a function. Using MCContext::createTempSymbol() always gives us a unique name. Differential Revision: http://reviews.llvm.org/D9314 llvm-svn: 242482
* Fix __builtin_setjmp in combination with sjlj exception handling.Matthias Braun2015-07-167-10/+39
| | | | | | | | | | | | | | | | | | | llvm.eh.sjlj.setjmp was used as part of the SjLj exception handling style but is also used in clang to implement __builtin_setjmp. The ARM backend needs to output additional dispatch tables for the SjLj exception handling style, these tables however can't be emitted if llvm.eh.sjlj.setjmp is simply used for __builtin_setjmp and no actual landing pad blocks exist. To solve this issue a new llvm.eh.sjlj.setup_dispatch intrinsic is introduced which is used instead of llvm.eh.sjlj.setjmp in the SjLj exception handling lowering, so we can differentiate between the case where we actually need to setup a dispatch table and the case where we just need the __builtin_setjmp semantic. Differential Revision: http://reviews.llvm.org/D9313 llvm-svn: 242481
* Fix ffiInvoke() use of DataLayout, broken in 242414Mehdi Amini2015-07-161-3/+3
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242456
* Fix spelling. NFCI.Simon Pilgrim2015-07-161-3/+3
| | | | llvm-svn: 242448
* AArch64: make inexact signalling on round Darwin-specificTim Northover2015-07-161-1/+1
| | | | | | | | | C11 leaves the choice on whether round-to-integer operations set the inexact flag implementation-defined. Darwin does expect it to be set, but this seems to be against the intent of the IEEE document and slower to implement anyway. So it should be opt-in. llvm-svn: 242446
* [PowerPC] v4i32 is a VSRCRegClassBill Schmidt2015-07-161-0/+1
| | | | | | | | | | | | | | | | I was looking at some vector code generation and kept seeing unnecessary vector copies into the Altivec half of the VSX registers. I discovered that we overlooked v4i32 when adding the register classes for VSX; we only added v4f32 and v2f64. This means that anything that canonicalizes into v4i32 (which is a LOT of stuff) ends up being forced into VRRC on its way to VSRC. The fix is one line. The rest of the patch is fixing up some test cases whose code generation has changed as a result. This seems like it would be a good candidate for backport to 3.7. llvm-svn: 242442
* Streamline the coding style in NVPTXLowerAggrCopiesEli Bendersky2015-07-161-111/+127
| | | | | | Make the style consistent with LLVM style throughout and clang-format. llvm-svn: 242439
* [NVPTX] enable SpeculativeExecution in NVPTXJingyue Wu2015-07-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SpeculativeExecution enables a series straight line optimizations (such as SLSR and NaryReassociate) on conditional code. For example, if (...) ... b * s ... if (...) ... (b + 1) * s ... speculative execution can hoist b * s and (b + 1) * s from then-blocks, so that we have ... b * s ... if (...) ... ... (b + 1) * s ... if (...) ... Then, SLSR can rewrite (b + 1) * s to (b * s + s) because after speculative execution b * s dominates (b + 1) * s. The performance impact of this change is significant. It speeds up the benchmarks running EigenFloatContractionKernelInternal16x16 (https://bitbucket.org/eigen/eigen/src/ba68f42fa69e4f43417fe1e52669d4dd5d2b3bee/unsupported/Eigen/CXX11/src/Tensor/TensorContractionCuda.h?at=default#cl-526) by roughly 2%. Some internal benchmarks that have the above code pattern are improved by up to 40%. No significant slowdowns are observed on Eigen CUDA microbenchmarks. Reviewers: jholewinski, broune, eliben Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11201 llvm-svn: 242437
* AArch64: Implement conditional compare sequence matching.Matthias Braun2015-07-164-76/+347
| | | | | | | | | | | | | | | This is a new iteration of the reverted r238793 / http://reviews.llvm.org/D8232 which wrongly assumed that any and/or trees can be represented by conditional compare sequences, however there are some restrictions to that. This version fixes this and adds comments that explain exactly what types of and/or trees can actually be implemented as conditional compare sequences. Related to http://llvm.org/PR20927, rdar://18326194 Differential Revision: http://reviews.llvm.org/D10579 llvm-svn: 242436
* AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operandTom Stellard2015-07-161-6/+9
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11226 llvm-svn: 242434
* AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsetsTom Stellard2015-07-164-3/+39
| | | | | | | | | | | | | | Summary: We can safely assume that the high bit of scratch offsets will never be set, because this would require at least 128 GB of GPU memory. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11225 llvm-svn: 242433
* LiveInterval: Document and enforce rules about empty subranges.Matthias Braun2015-07-163-0/+9
| | | | | | | | | Empty subranges are not allowed in a LiveInterval and must be removed instead: Check this in the verifiers, put a reminder for this in the comment of the shrinkToUses variant for a single lane and make it automatic for the shrinkToUses variant for a LiveInterval. llvm-svn: 242431
* Do not duplicate method name in comment, remove duplicate commentMatthias Braun2015-07-161-3/+0
| | | | llvm-svn: 242430
* Revert "Add missing load/store flags to thumb2 instructions."Pete Cooper2015-07-161-4/+1
| | | | | | | | | | This reverts commit r242300. This is causing buildbot failures which we are investigating. I'll reapply once we know whats going on, but for now want to get the bots green. llvm-svn: 242428
* Rename LoopInfo::Analyze() to LoopInfo::analyze() and turn its parameter ↵Cong Hou2015-07-162-3/+3
| | | | | | | | | | type to const&. The benefit of turning the parameter of LoopInfo::analyze() to const& is that it now can accept a rvalue. http://reviews.llvm.org/D11250 llvm-svn: 242426
* Internalize: internalize comdat members as a group, and drop comdat on such ↵Peter Collingbourne2015-07-161-26/+71
| | | | | | | | | | | | | | | | | | | | members. Internalizing an individual comdat group member without also internalizing the other members of the comdat can break comdat semantics. For example, if a module contains a reference to an internalized comdat member, and the linker chooses a comdat group from a different object file, this will break the reference to the internalized member. This change causes the internalizer to only internalize comdat members if all other members of the comdat are not externally visible. Once a comdat group has been fully internalized, there is no need to apply comdat rules to its members; later optimization passes (e.g. globaldce) can legally drop individual members of the comdat. So we drop the comdat attribute from all comdat members. Differential Revision: http://reviews.llvm.org/D10679 llvm-svn: 242423
* [NVPTX] Don't leak dead instructions after unlinking them from the BasicBlockBenjamin Kramer2015-07-161-2/+2
| | | | llvm-svn: 242417
* Make ExecutionEngine owning a DataLayoutMehdi Amini2015-07-168-50/+62
| | | | | | | | | | | | | | | | | | | | Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. The ExecutionEngine will act as an exception and will be unsafe to be reused across context. We don't enforce this rule but undefined behavior can occurs if the user tries to do it. Reviewers: lhames Subscribers: echristo, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11110 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 242414
* Correct lowering of memmove in NVPTXEli Bendersky2015-07-162-61/+168
| | | | | | | | | | This fixes https://llvm.org/bugs/show_bug.cgi?id=24056 Also a bit of refactoring along the way. Differential Revision: http://reviews.llvm.org/D11220 llvm-svn: 242413
* AMDGPU/R600: Remove unused variableTom Stellard2015-07-161-1/+0
| | | | | | This fixes a warning introduced by r242410. llvm-svn: 242412
* AMDPGU/R600: Replace llvm_unreachable() call with LLVMContext::emitError()Tom Stellard2015-07-161-12/+3
| | | | | | | | | | | | | | | | Summary: This fixes an issue on MIPS where the infinite-loop-evergreen.ll test was failing to terminate. Fixes PR24147. Reviewers: arsenm, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11260 llvm-svn: 242410
* [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute ↵James Molloy2015-07-166-0/+50
| | | | | | | | | | | | | difference operation This adds new intrinsics "*absdiff" for absolute difference ops to facilitate efficient code generation for "sum of absolute differences" operation. The patch also contains the introduction of corresponding SDNodes and basic legalization support.Sanity of the generated code is tested on X86. This is 1st of the three patches. Patch by Shahid Asghar-ahmad! llvm-svn: 242409
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