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* Factor out a loopHasNoAbnormalExits; NFCSanjoy Das2016-06-091-9/+8
| | | | llvm-svn: 272236
* Search for llvm-symbolizer binary in the same directory as argv[0], beforeRichard Smith2016-06-093-15/+37
| | | | | | | looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
* [codeview] Skip DIGlobalVariables with no variableReid Kleckner2016-06-091-2/+3
| | | | | | They have probably been discarded during optimization. llvm-svn: 272231
* [pdbdump] Verify part of TPI hash streams.Rui Ueyama2016-06-091-0/+28
| | | | | | | | | | | | | | | | | TPI hash table contains a parallel array for the type records. For each type record R, a hash value is calculated by `H(R) % NumBuckets` where H is a hash function, and the result is stored to a bucket element. H is TPI1::hashPrec function in microsoft-pdb repository. Our hash function does not support all type record types yet. Currently it supports only records for line number. I'll extend it in a follow up patch. The aim of verify the hash table is not only detect corrupted files. It ensures that our understanding of how the hash values are calculated is correct. llvm-svn: 272229
* [cpu-detection] Add missing break statements in outer switchesAlina Sbirlea2016-06-091-6/+9
| | | | | | | | | | | | Summary: Break on all switch cases for outer and inner switches. No functionality changed. Reviewers: llvm-commits, sanjoy Differential Revision: http://reviews.llvm.org/D21158 llvm-svn: 272228
* [MIR] Check that generic virtual registers get a size.Quentin Colombet2016-06-083-4/+11
| | | | | | | | Without that check it was possible to write test cases where the size was not specified and we ended up with weird asserts down the road, because the default value (1) would not make sense. llvm-svn: 272226
* Function names should start with lowercase letters.Rui Ueyama2016-06-082-3/+3
| | | | llvm-svn: 272225
* [LoopSimplify] Preserve LCSSA when merging exit blocks.Michael Zolotukhin2016-06-081-2/+21
| | | | | | | | | | | | | | Summary: This fixes PR26682. Also add LCSSA as a preserved pass to LoopSimplify, that looks correct to me and allows to write a test for the issue. Reviewers: chandlerc, bogner, sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21112 llvm-svn: 272224
* [PDB] Move PDB functions to a separate file.Rui Ueyama2016-06-083-59/+79
| | | | | | | | We are going to use the hash functions from TPI streams. Differential Revision: http://reviews.llvm.org/D21142 llvm-svn: 272223
* [LoopUnroll] Check that DT is available before trying to verify it.Michael Zolotukhin2016-06-081-1/+1
| | | | llvm-svn: 272221
* [RegBankSelect] Print out the actual mapping of the operands.Quentin Colombet2016-06-081-0/+1
| | | | | | This improves the debuggability of the pass. llvm-svn: 272210
* [RegBankSelect] Remove a debug print of a potentially dead instruction.Quentin Colombet2016-06-081-2/+2
| | | | | | | | For complex rewrittings, which do not occur currently, the related machine instruction may have been deleted in the process. Therefore, do not try to print it after the mapping is applied. llvm-svn: 272209
* [RegisterBankInfo] Avoid code duplication in OperandsMapper for the ↵Quentin Colombet2016-06-081-6/+17
| | | | | | | | | | | | | computation of the end of range. Refactor the code so that we do not compute in two different places the end iterator for the range of new virtual registers for a given operand. Although this refactoring was intended as NFC, this is not the case because it actually fixes a bug where we were returning a range off by 1 (too long). Right now, this could not result in an actual bug because we were accessing this range via the BreakDown size of the related operand. llvm-svn: 272208
* [RegisterBankInfo] Add dump/print methods for OperandsMapper.Quentin Colombet2016-06-081-2/+55
| | | | | | Improve debuggability of the OperandsMapper helper class. llvm-svn: 272207
* [SLPVectorizer] Handle GEP with differing constant index typesMichael Zolotukhin2016-06-081-1/+1
| | | | | | | | | | | | | | | | | | | Summary: This fixes PR27617. Bug description: The SLPVectorizer asserts on encountering GEPs with different index types, such as i8 and i64. The patch includes a simple relaxation of the assert to allow constants being of different types, along with a regression test that will provoke the unrelaxed assert. Reviewers: nadav, mzolotukhin Subscribers: JesperAntonsson, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D20685 Patch by Jesper Antonsson! llvm-svn: 272206
* [PM] Add missing caching of GlobalsAA to EarlyCSE.Davide Italiano2016-06-081-0/+1
| | | | llvm-svn: 272204
* Revive http://reviews.llvm.org/D12778 to handle forward-hot-prob and ↵Dehao Chen2016-06-081-3/+10
| | | | | | | | | | | | | | | | | | | | | | | backward-hot-prob consistently. Summary: Consider the following diamond CFG: A / \ B C \/ D Suppose A->B and A->C have probabilities 81% and 19%. In block-placement, A->B is called a hot edge and the final placement should be ABDC. However, the current implementation outputs ABCD. This is because when choosing the next block of B, it checks if Freq(C->D) > Freq(B->D) * 20%, which is true (if Freq(A) = 100, then Freq(B->D) = 81, Freq(C->D) = 19, and 19 > 81*20%=16.2). Actually, we should use 25% instead of 20% as the probability here, so that we have 19 < 81*25%=20.25, and the desired ABDC layout will be generated. Reviewers: djasper, davidxl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20989 llvm-svn: 272203
* [InstCombine] move fold of select of add/sub to helper function; NFCISanjay Patel2016-06-081-61/+75
| | | | llvm-svn: 272199
* [DebugInfo] Add calling convention support for DWARF and CodeViewReid Kleckner2016-06-0812-36/+91
| | | | | | | | | | | | | | | | | | | | | Summary: Now DISubroutineType has a 'cc' field which should be a DW_CC_ enum. If it is present and non-zero, the backend will emit it as a DW_AT_calling_convention attribute. On the CodeView side, we translate it to the appropriate enum for the LF_PROCEDURE record. I added a new LLVM vendor specific enum to the list of DWARF calling conventions. DWARF does not appear to attempt to standardize these, so I assume it's OK to do this until we coordinate with GCC on how to emit vectorcall convention functions. Reviewers: dexonsmith, majnemer, aaboud, amccarth Subscribers: mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D21114 llvm-svn: 272197
* [InstCombine] fix outdated comment, simplify logic; NFCISanjay Patel2016-06-081-16/+13
| | | | llvm-svn: 272196
* The patch set unroll disable pragma when unrollEvgeny Stupachenko2016-06-081-11/+11
| | | | | | | | | | | | | | | | | with user specified count has been applied. Summary: Previously SetLoopAlreadyUnrolled() set the disable pragma only if there was some loop metadata. Now it set the pragma in all cases. This helps to prevent multiple unroll when -unroll-count=N is given. Reviewers: mzolotukhin Differential Revision: http://reviews.llvm.org/D20765 From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 272195
* [PM] Refector LoopAccessInfo analysis code Xinliang David Li2016-06-086-17/+16
| | | | | | | | This is the preparation patch to port the analysis to new PM Differential Revision: http://reviews.llvm.org/D20560 llvm-svn: 272194
* [InstCombine] reduce indent; NFCSanjay Patel2016-06-081-63/+64
| | | | llvm-svn: 272193
* [MemCpyOpt] Do not exchange llvm.lifetime.start and llvm.memcpyTim Shen2016-06-081-0/+5
| | | | | | | | | | Reviewers: iteratee Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D21087 llvm-svn: 272192
* [InstCombine] use copyIRFlags() ; NFCISanjay Patel2016-06-081-12/+2
| | | | llvm-svn: 272191
* Apply most suggestions of clang-tidy's performance-unnecessary-value-paramBenjamin Kramer2016-06-0827-56/+54
| | | | | | | Avoids unnecessary copies. All changes audited & pass tests with asan. No functional change intended. llvm-svn: 272190
* Generate codeview for array type metadata.Adrian McCarthy2016-06-082-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D21107 llvm-svn: 272187
* Attempt #2 to appease the buildbots.George Burgess IV2016-06-081-3/+3
| | | | | | | MSVC calls the copy ctor on StratifiedSets for some reason. So, undelete it. llvm-svn: 272184
* [codeview] Avoid emitting an empty file checksum tableReid Kleckner2016-06-081-0/+5
| | | | | | | | | | Again, the Microsoft linker does not like empty substreams. We still emit an empty string table if CodeView is enabled, but that doesn't cause problems because it always contains at least one null byte. llvm-svn: 272183
* [SCEV] Break out of loop if there is no more work to doSanjoy Das2016-06-081-1/+1
| | | | | | | This is NFC as far as externally visible behavior is concerned, but will keep us from spinning in the worklist traversal algorithm unnecessarily. llvm-svn: 272182
* [SCEV] Track no-abnormal-exits instead of no-throw callsSanjoy Das2016-06-081-10/+10
| | | | | | | | | | | Absence of may-unwind calls is not enough to guarantee that a UB-generating use of an add-rec poison in the loop latch will actually cause UB. We also need to guard against calls that terminate the thread or infinite loop themselves. This partially addresses PR28012. llvm-svn: 272181
* Teach isGuarantdToTransferExecToSuccessor about debug info intrinsicsSanjoy Das2016-06-081-3/+6
| | | | | | Calls to `@llvm.dbg.*` can be assumed to terminate. llvm-svn: 272180
* Fix a bug in SCEV's poison value propagationSanjoy Das2016-06-081-12/+13
| | | | | | | | | | | | | The worklist algorithm introduced in rL271151 didn't check to see if the direct users of the post-inc add recurrence propagates poison. This change fixes the problem and makes the code structure more obvious. Note for release managers: correctness wise, this bug wasn't a regression introduced by rL271151 -- the behavior of SCEV around post-inc add recurrences was strictly improved (in terms of correctness) in rL271151. llvm-svn: 272179
* [RegBankSelect] Silence an unused variable warning in release mode.Quentin Colombet2016-06-081-0/+1
| | | | llvm-svn: 272177
* [RegBankSelect] Comment on how we could improve repairing with copies.Quentin Colombet2016-06-081-0/+11
| | | | | | | | | | | When repairing with a copy, instead of accounting for the cost of that copy and actually inserting it, we may be able to use an alternative source for the register to repair and just use it. Make sure this is documented, so that we consider that opportunity at some point. llvm-svn: 272176
* Try to appease buildbots.George Burgess IV2016-06-081-3/+8
| | | | | | | r272064 apparently made them angry. This undoes some changes made in r272064 (defaulting move ctors) to make them happy again. llvm-svn: 272173
* [pdb] Handle stream index errors better.Zachary Turner2016-06-088-89/+143
| | | | | | | Reviewed By: ruiu Differential Revision: http://reviews.llvm.org/D21128 llvm-svn: 272172
* Remove a patch .rej file.Rui Ueyama2016-06-081-11/+0
| | | | llvm-svn: 272171
* [AArch64][RegisterBankInfo] G_OR are fine on either GPR or FPR.Quentin Colombet2016-06-082-0/+63
| | | | | | | | | | Teach AArch64RegisterBankInfo that G_OR can be mapped on either GPR or FPR for 64-bit or 32-bit values. Add test cases demonstrating how this information is used to coalesce a computation on a single register bank. llvm-svn: 272170
* [RegBankSelect] Use RegisterBankInfo applyMapping method.Quentin Colombet2016-06-081-11/+8
| | | | | | | The RegBankSelect pass can now rely on the target to do the remapping of the instructions. llvm-svn: 272169
* [RegisterBankInfo] Implement the method to apply a mapping.Quentin Colombet2016-06-081-0/+27
| | | | | | | | | Now, the target will be able to provide its how implementation to remap an instruction. This open the way to crazier optimizations, but to beginning with, we will be able to handle something else than the default mapping. llvm-svn: 272165
* [RegBankSelect] Use the OperandMapper class to hold remap information.Quentin Colombet2016-06-081-10/+8
| | | | | | | | | Now that we have an entity that hold the remap information the rewritting should be easier to do. No functional changes. llvm-svn: 272164
* [RegBankSelect] Use const_iterator instead of iterator for repairReg.Quentin Colombet2016-06-081-1/+1
| | | | | | | The repairing code has no reason to change the source or destination of the registers. llvm-svn: 272163
* [RegisterBankInfo] Introduce OperandsMapper class.Quentin Colombet2016-06-081-0/+90
| | | | | | | This helper class is used to encapsulate the necessary information to remap an instruction. llvm-svn: 272161
* [RegBankSelect] Introduce a command line option to override the running mode.Quentin Colombet2016-06-081-0/+14
| | | | | | | | | | When the command line option is set, it overrides any thing that the target may have set. The rationale is that we get what we asked for. Options are respectively regbankselect-fast and regbankselect-greedy for fast and greedy mode. llvm-svn: 272158
* [RegBankSelect] Explain what it would take to support non-copyQuentin Colombet2016-06-081-0/+9
| | | | | | | | | | | repairing. Copies are easy because we repair only when there is a mismatch. For non-copy repairing, i.e., cases that involves breaking down or gathering up the value, one of the operand may not have a register bank yet. Thus, derivate a cost from that, requires more work. llvm-svn: 272157
* [ARM] MSR instructions implicitly set CPSROliver Stannard2016-06-082-0/+4
| | | | | | | | | | | | | | | The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
* Support: correct AArch64 TargetParser implementationSaleem Abdulrasool2016-06-081-20/+21
| | | | | | | | | | | | | | | | | | | | | | | The architecture enumeration is shared across ARM and AArch64. However, the data is not. The code incorrectly would index into the array using the architecture index which was offset by the ARMv7 architecture enumeration. We do not have a marker for indicating the architectural family to which the enumeration belongs so we cannot be clever about offsetting the index (at least it is not immediately apparent to me). Instead, fall back to the tried-and-true method of slowly iterating the array (its not a large array, so the impact of this is not too high). Because of the incorrect indexing, if we were lucky, we would crash, but usually we would return an invalid StringRef. We did not have any tests for the AArch64 target parser previously;. Extend the previous tests I had added for ARM to cover AArch64 for ensuring that we return expected StringRefs. Take the opportunity to change some iterator types to references. This work is needed to support parsing `.arch name` directives in the AArch64 target asm parser. llvm-svn: 272145
* [PM] LoopSimplify. Remove unneeded pass dependencies. NFCI.Davide Italiano2016-06-081-3/+0
| | | | llvm-svn: 272140
* [PM/SimplifyCFG] Preserve GlobalsAA even if the IR is mutated.Davide Italiano2016-06-081-4/+5
| | | | llvm-svn: 272139
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