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* [NFC] Zero initialize local variablesHiroshi Inoue2018-06-011-1/+1
| | | | | | This patch makes local variables zero initialized to avoid broken values in debug output. llvm-svn: 333754
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-016-14/+73
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet2018-06-0111-59/+32
| | | | | | | | | | | | | | | Summary: They've been deprecated in favor of UADDO/ADDCARRY or USUBO/SUBCARRY for a while. Target that uses these opcodes are changed in order to ensure their behavior doesn't change. Reviewers: efriedma, craig.topper, dblaikie, bkramer Subscribers: jholewinski, arsenm, jyknight, sdardis, nemanjai, nhaehnle, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, mgrang, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D47422 llvm-svn: 333748
* [AArch64][GlobalISel] Zero-extend s1 values when returning.Amara Emerson2018-06-012-12/+7
| | | | | | | | | | | Before we were relying on the any extend of the s1 to s32, but for AAPCS we need to zero-extend it to at least s8. Fixes PR36719 Differential Revision: https://reviews.llvm.org/D47425 llvm-svn: 333747
* Revert r333740: IPSCCP] Use PredicateInfo to propagate facts from cmp.Florian Hahn2018-06-012-134/+10
| | | | | | This is breaking the clang-with-thin-lto-ubuntu bot. llvm-svn: 333745
* [AArch64][SVE] Asm: Support for FDUP_ZI (copy fp immediate) instruction.Sander de Smalen2018-06-012-0/+39
| | | | | | | | | | | | | Unpredicated copy of floating-point immediate value into SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D47482 llvm-svn: 333744
* [mips] Guard more aliases correctly.Simon Dardis2018-06-012-48/+56
| | | | | | Also, duplicate an alias for microMIPS. llvm-svn: 333741
* Recommit r333268: [IPSCCP] Use PredicateInfo to propagate facts from cmp ↵Florian Hahn2018-06-012-10/+134
| | | | | | | | | | | | | | | | | | | instructions. This patch updates IPSCCP to use PredicateInfo to propagate facts to true branches predicated by EQ and to false branches predicated by NE. As a follow up, we should be able to extend it to also propagate additional facts about nonnull. Reviewers: davide, mssimpso, dberlin, efriedma Reviewed By: davide, dberlin Differential Revision: https://reviews.llvm.org/D45330 llvm-svn: 333740
* [mips] Guard 'nop' properly and add mips16's nop instructionSimon Dardis2018-06-013-12/+19
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47583 llvm-svn: 333739
* DWARFAcceleratorTable: Add an iterator-based api for accessing names in the ↵Pavel Labath2018-06-012-37/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | index Summary: Back when we were introducing the DWARF v5 name index, there was a short discussion whether we shouldn't have a nicer api for iterating over the index. At that time, I did not find it necessary since the iteration over names was done only from within the index itself (and I figured the internal implementation can deal with a slightly rough interface). However, now I ran into a use for this kind of API in LLDB (for finding all names matching a regular expression), so it looked like a nice opportunity to introduce one. To make the API more useful, I've made the NameTableEntry class a bit smarter: it now stores the string section reference (so it can return its name) and its position in the name index (mainly useful for dumping/logging). I also convert the internal users to use the new API, which also gives test coverage for the added code. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47590 llvm-svn: 333738
* [mips] Select the correct instruction for computing frameindexesSimon Dardis2018-06-014-3/+7
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47582 llvm-svn: 333736
* NFC Avoid a warning in WasmEHPrepare.cppGabor Buella2018-06-011-1/+1
| | | | | | | | | | ``` ../lib/CodeGen/WasmEHPrepare.cpp:166:30: warning: extra ‘;’ [-Wpedantic] false, false); ^ ``` llvm-svn: 333732
* [AArch64][SVE] Asm: Support for DUPM (masked immediate) instruction.Sander de Smalen2018-06-017-1/+137
| | | | | | | | | | | | | Unpredicated copy of repeating immediate pattern to SVE vector, along with MOV-aliases. Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D47328 llvm-svn: 333731
* [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg ↵Craig Topper2018-06-011-7/+18
| | | | | | | | encodes a GPR. This is different than the behavior of EVEX.X extending modrm.rm to 5 bits. llvm-svn: 333728
* [X86][Disassembler] Ignore EVEX.X extension of modrm.rm to 5-bits when ↵Craig Topper2018-06-011-0/+1
| | | | | | modrm.rm encodes a k-register. llvm-svn: 333727
* [X86][Disassembler] Clamp index to 4-bits when decoding GPR registers.Craig Topper2018-06-011-3/+4
| | | | | | A 5-bit value can occur when EVEX.X is 0 due to it being used to extend modrm.rm to encode XMM16-31. But if modrm.rm instead encodes a GPR, the Intel documentation says EVEX.X should be ignored so just mask it to 4 bits once we know its a GPR. llvm-svn: 333725
* [X86][Disassembler] Make sure EVEX.X is not used to extend base registers of ↵Craig Topper2018-06-011-3/+5
| | | | | | | | | | memory operations. This was an accidental side effect of EVEX.X being used to encode XMM16-XMM31 using modrm.rm with modrm.mod==0x3. I think there are still more bugs related to this. llvm-svn: 333722
* [X86][Disassembler] Use a local variable instead of using a field in the ↵Craig Topper2018-06-012-10/+11
| | | | | | instruction object. NFC llvm-svn: 333721
* AMDGPU/R600: Move intrinsics to IntrinsicsAMDGPU.tdTom Stellard2018-06-013-70/+6
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle, jvesely Reviewed By: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D47487 llvm-svn: 333720
* [X86] Make sure the check for VEX.vvvv being all ones on instructions that ↵Craig Topper2018-06-011-1/+3
| | | | | | don't use it doesn't ignore a bit in 32-bit mode. llvm-svn: 333717
* [X86][Disassembler] Suppress reading of EVEX.V' and EVEX.R' in 32-bit mode.Craig Topper2018-06-011-2/+2
| | | | llvm-svn: 333714
* Change ambiguous uses of term 'funclet' to 'EH scopes'. NFC.Heejin Ahn2018-06-014-48/+51
| | | | | | | | | | | | | | | | | | Summary: `getEHScopeMembership()` function is used not only for funclet-based EHs; they apply to all EH schemes that use the scoped IR (catchpad/cleanuppad/...). D47005 (rL333045) changed some of the uses of the term 'funclet' to 'EH scopes' in case they apply to all scoped EH, and this fixes more of them. For `FuncletLayout` pass, I left it as is because the pass is only used for funclet-based EH. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47611 llvm-svn: 333711
* [WebAssembly] Update to the new names for the memory intrinsics.Dan Gohman2018-05-311-0/+9
| | | | | | | | | The WebAssembly committee has decided on the names `memory.size` and `memory.grow` for the memory intrinsics, so update the LLVM intrinsics to follow those names, keeping both sets of old names in place for compatibility. llvm-svn: 333708
* [WebAssembly] Fix the signatures for the __mulo* libcalls.Dan Gohman2018-05-311-3/+31
| | | | | | | | The __mulo* libcalls have an extra i32* to return the overflow value. Fixes PR37401. llvm-svn: 333706
* [WebAssembly] Support instruction selection for catching exceptionsHeejin Ahn2018-05-3112-14/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This lowers exception catching-related instructions: 1. Lowers `wasm.catch` intrinsic to `catch` instruction 2. Removes `catchpad` and `cleanuppad` instructions; they are not necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or `MachineBasicBlock::isEHPad()` can be used instead.) 3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret` and `cleanupret` instructions in isel, which will be replaced with other instructions in `WebAssemblyExceptionPrepare` pass. 4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various transformation for EH. Currently this pass only replaces `catchret` and `cleanupret` instructions into appropriate wasm instructions to make this patch successfully run until the end. Currently this does not handle lowering of intrinsics related to LSDA info generation (`wasm.landingpad.index` and `wasm.lsda`), because they cannot be tested without implementing `EHStreamer`'s wasm-specific handlers. They are marked as TODO, which is needed to make isel pass. Also this does not generate `try` and `end_try` markers yet, which will be handled in later patches. This patch is based on the first wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D44090 llvm-svn: 333705
* [LoopIdiomRecognize] Only convert loops to ctlz if we can prove that the ↵Craig Topper2018-05-311-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | input is non-negative. Summary: Loop idiom recognize tries to convert loops like ``` int foo(int x) { int cnt = 0; while (x) { x >>= 1; ++cnt; } return cnt; } ``` into calls to ctlz, but if x is initially negative this loop should be infinite. It happens that the cases that motivated this change have an absolute value of x before the loop. So this patch restricts the transform to cases where we know x is positive. Note: We are relying on the absolute value of INT_MIN to be undefined so we can assume that the result is always positive. Fixes PR37479 Reviewers: spatel, hfinkel, efriedma, javed.absar Reviewed By: efriedma Subscribers: dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D47348 llvm-svn: 333702
* [WebAssembly] Add Wasm exception handling prepare passHeejin Ahn2018-05-315-6/+358
| | | | | | | | | | | | | | | | Summary: This adds a pass that transforms a program to be prepared for Wasm exception handling. This is using Windows EH instructions and based on the previous Wasm EH proposal. (https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md) Reviewers: dschuff, majnemer Subscribers: jfb, mgorny, sbc100, jgravelle-google, JDevlieghere, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D43746 llvm-svn: 333696
* [AMDGPU] Construct memory clauses before RAStanislav Mekhanoshin2018-05-315-0/+422
| | | | | | | | | | | | | | | | | | Memory clauses are formed into bundles in presence of xnack. Their source operands are marked as early-clobber. This allows to allocate distinct source and destination registers within a clause and prevent breaking the clause with s_nop in the hazard recognizer. Clauses are undone before post-RA scheduler to allow some rescheduling, which will not break the clause since artificial edges are created in the dag to keep memory operations together. Yet this allows a better ILP in some cases. Differential Revision: https://reviews.llvm.org/D47511 llvm-svn: 333691
* [InstCombine] narrow select to match condition operands' sizeSanjay Patel2018-05-311-8/+11
| | | | | | | | | | | | | This is the planned enhancement to D47163 / rL333611. We want to match cmp/select sizes because that will be recognized as min/max more easily and lead to better codegen (especially for vector types). As mentioned in D47163, this improves some of the tests that would also be folded by D46380, so we may want to adjust that patch to match the new patterns where the extend op occurs after the select. llvm-svn: 333689
* [ORC] Add a getRequestedSymbols method to MaterializationResponsibility.Lang Hames2018-05-311-7/+37
| | | | | | | | | | | This method returns the set of symbols in the target VSO that have queries waiting on them. This can be used to make decisions about which symbols to delegate to another MaterializationUnit (typically this will involve delegating all symbols that have *not* been requested to another MaterializationUnit so that materialization of those symbols can be deferred until they are requested). llvm-svn: 333684
* [ORC] Rename IRMaterializationUnit's Discardable member to SymbolToDefinition,Lang Hames2018-05-311-4/+6
| | | | | | | | | | and make it protected rather than private. The new name reflects the actual information in the map, and this information can be useful to derived classes (for example, to quickly look up the IR definition of a requested symbol). llvm-svn: 333683
* IRGen: Write .dwo files when -split-dwarf-file is used together with ↵Peter Collingbourne2018-05-311-1/+6
| | | | | | | | -fthinlto-index. Differential Revision: https://reviews.llvm.org/D47597 llvm-svn: 333677
* Relax GOTPCREL relocations for tail jmp instructions.Sriraman Tallam2018-05-311-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D47563 llvm-svn: 333676
* [JumpThreading] Fix some strange formatting of code inside LLVM_DEBUG. NFCCraig Topper2018-05-311-5/+5
| | | | | | I don't know if clang-format got confused here or what. llvm-svn: 333675
* [ADT] Make escaping fn conform to coding guidelinesJonas Devlieghere2018-05-314-16/+16
| | | | | | | | As noted by Adrian on llvm-commits, PrintHTMLEscaped and PrintEscaped in StringExtras did not conform to the LLVM coding guidelines. This commit rectifies that. llvm-svn: 333669
* [SimplifyLibcalls] [NFC] Cleanup, improvementsDavid Bolvansky2018-05-311-11/+9
| | | | | | | | | | | | | | | | Summary: * Use "find('%')" instead of loop to find '%' char (we already uses find('%') in optimizePrintFString..) * Convert getParent() chains to getModule()/getFunction() Reviewers: lebedev.ri, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47397 llvm-svn: 333668
* [MC] Fallback on DWARF when generating compact unwind on AArch64Francis Visoiu Mistrih2018-05-311-3/+11
| | | | | | | | | | | | | | | Instead of asserting when using the def_cfa directive with a register different from fp, fallback on DWARF. Easily triggered with: .cfi_def_cfa x1, 32; rdar://40249694 Differential Revision: https://reviews.llvm.org/D47593 llvm-svn: 333667
* [GlobalISel][Mips] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-0/+2
| | | | | | | | | | | | call for Mips Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333665
* [GlobalISel][AMDGPU] LegalizerInfo verifier: Adding ↵Roman Tereshin2018-05-311-0/+1
| | | | | | | | | | | | LegalizerInfo::verify(...) call for AMDGPU Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333664
* [GlobalISel][ARM] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-3/+5
| | | | | | | | | | | | call and fixing bugs exposed Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333663
* [GlobalISel][X86] LegalizerInfo verifier: Adding LegalizerInfo::verify(...) ↵Roman Tereshin2018-05-311-2/+3
| | | | | | | | | | | | call and fixing bugs exposed Reviewers: aemerson, qcolombet Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D46339 llvm-svn: 333662
* [X86][SSE] Recognise splat rotations and expand back to shift ops.Simon Pilgrim2018-05-311-0/+12
| | | | | | Noticed while fixing PR37426, for splat rotations (rotation by an uniform value) its better to just expand back to shift ops than performing as a general non-uniform rotation. llvm-svn: 333661
* [X86][AVX] Add peekThroughEXTRACT_SUBVECTORs helper (NFCI)Simon Pilgrim2018-05-311-10/+10
| | | | | | We often need this for AVX1 128-bit integer ops as they may have been split from a 256-bit source. llvm-svn: 333660
* [DA] Fix direction vectors for weakZeroSrcSIVDavid Green2018-05-311-4/+4
| | | | | | | | | | Both weakZeroSrcSIV and weakZeroDstSIV are currently giving the same direction vectors. Fix weakZeroSrcSIVtest by flipping the directions it gives. Differential Revision: https://reviews.llvm.org/D46678 llvm-svn: 333658
* [X86] Introduce WriteFLDC for x87 constant loads.Clement Courbet2018-05-3111-10/+18
| | | | | | | | | | | | | | | | | Summary: {FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded. - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake. - For ZnVer1 and Atom, values were transferred form InstRWs. - For SLM and BtVer2, I've guessed some values :( Reviewers: RKSimon, craig.topper, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47585 llvm-svn: 333656
* [MCSchedule] Add the ability to compute the latency and throughput ↵Andrea Di Biagio2018-05-313-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | information for MCInst. This patch extends the MCSchedModel API with new methods that can be used to obtain the latency and reciprocal througput information for an MCInst. Scheduling models have recently gained the ability to resolve variant scheduling classes associated with MCInst objects. Before, models were only able to resolve a variant scheduling class from a MachineInstr object. This patch is mainly required by D47374 to avoid regressing a pair of x86 specific -print-schedule tests for btver2. Patch D47374 introduces a new variant class to teach the btver scheduling model (x86 target) how to correctly compute the latency profile for some zero-idioms using the new scheduling predicates. The new methods added by this patch would be mainly used by llc when flag -print-schedule is specified. In particular, tests that contain inline assembly require that code is parsed at code emission stage into a sequence of MCInst. That forces the print-schedule functionality to query the latency/rthroughput information for MCInst instructions too. If we don't expose this new API, then we lose "-print-schedule" test coverage as soon as variant scheduling classes are added to the x86 models. The tablegen SubtargetEmitter changes teaches how to query latency profile information using a object that derives from TargetSubtargetInfo. Note that this should really have been part of r333286. To avoid code duplication, the logic that "resolves" variant scheduling classes for MCInst, has been moved to a common place in MC. That logic is used by the "resolveVariantSchedClass" methods redefined in override by the tablegen'd GenSubtargetInfo classes. Differential Revision: https://reviews.llvm.org/D47536 llvm-svn: 333650
* Extend the GlobalObject metadata interfaceBenjamin Kramer2018-05-315-58/+53
| | | | | | | | | | | | - Make eraseMetadata return whether it changed something - Wire getMetadata for a single MDNode efficiently into the attachment map - Add hasMetadata, which is less weird than checking getMetadata == nullptr on a multimap. Use it to simplify code. llvm-svn: 333649
* [mips] Guard all short instructions correctly.Simon Dardis2018-05-312-22/+40
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
* [InstCombine, ARM] Convert vld1 to llvm loadAlexandros Lamprineas2018-05-311-1/+30
| | | | | | | | | | Convert a vector load intrinsic into an llvm load instruction. This is beneficial when the underlying object being addressed comes from a constant, since we get constant-folding for free. Differential Revision: https://reviews.llvm.org/D46273 llvm-svn: 333643
* [X86] Extract latency of fldz/fld1 in separate classes.Clement Courbet2018-05-3111-10/+26
| | | | | | | | | | | | | | | | | Summary: - I've measured the values for Broadwell, Haswell, SandyBridge, Skylake. - For ZnVer1 and Atom, values were transferred form `InstRW`s. - For SLM and BtVer2, values are from Agner. This is split off from https://reviews.llvm.org/D47377 Reviewers: RKSimon, andreadb Subscribers: gbedwell, llvm-commits Differential Revision: https://reviews.llvm.org/D47523 llvm-svn: 333642
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