summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of ↵Daniel Sanders2014-05-073-161/+156
| | | | | | | | | | | | | | | | | FGRPredicates/GPRPredicates Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 llvm-svn: 208213
* [mips] Add INSN_<name> adverbs and start using them instead of ↵Daniel Sanders2014-05-071-6/+8
| | | | | | | | | | | | | | | | | AdditionalPredicates overrides Summary: No functional change Depends on D3641 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3642 llvm-svn: 208212
* [msan] Fix -fsanitize=memory -fno-integrated-as.Evgeniy Stepanov2014-05-071-1/+1
| | | | llvm-svn: 208211
* AArch64/ARM64: optimise vector selects & enable testTim Northover2014-05-071-0/+41
| | | | | | | | | When performing a scalar comparison that feeds into a vector select, it's actually better to do the comparison on the vector side: the scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP" since the vector comparisons are all mask based. llvm-svn: 208210
* [mips] Add ISA_<name> adverbs and start using them instead of ↵Daniel Sanders2014-05-074-42/+46
| | | | | | | | | | | | | | | | | | AdditionalPredicates overrides Summary: One small functional change. The recently added PAUSE instruction now has the HasStdEnc predicate which was accidentally removed by a Requires<>. Depends on D3640 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3641 llvm-svn: 208209
* Remove the UseCFI option from createAsmStreamer.Rafael Espindola2014-05-078-29/+20
| | | | | | We were already always passing true, this just removes the option. llvm-svn: 208205
* [mips] Continue splitting Instruction.Predicates into smaller lists and ↵Daniel Sanders2014-05-073-29/+39
| | | | | | | | | | | | | | | | | | | re-join them with !listconcat Summary: Move IsGP64bit into GPRPredicates, and IsFP64bit/NotFP64bit into FGRPredicates No functional change (confirmed by diffing tablegen-erated files). Depends on D3639 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3640 llvm-svn: 208201
* [ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.James Molloy2014-05-071-0/+5
| | | | llvm-svn: 208200
* [ARM64-BE] Fix variable-argument saving.James Molloy2014-05-071-1/+2
| | | | llvm-svn: 208199
* [ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big ↵James Molloy2014-05-071-0/+17
| | | | | | | | | | | | | | | | endian. The AAPCS states that values passed in registers must have a value as though they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is, loading scalars to vector registers and loading 1-element vectors is equivalent. The logic implemented here is to ensure that at all call boundaries and during formal argument lowering all vectors are treated as their bitwidth-based floating point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64, v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be generated during code generation. llvm-svn: 208198
* [mips] Move IsFP64bit/NotFP64bit to the front of the AdditionalPredicates listDaniel Sanders2014-05-071-6/+6
| | | | | | | | | | | | | | Summary: This makes it easier to prove a more complicated change in the next commit is non-functional. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3639 llvm-svn: 208197
* [ARM64-BE] Implement the crazy bitcast handling for big endian vectors.James Molloy2014-05-071-46/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because we've canonicalised on using LD1/ST1, every time we do a bitcast between vector types we must do an equivalent lane reversal. Consider a simple memory load followed by a bitconvert then a store. v0 = load v2i32 v1 = BITCAST v2i32 v0 to v4i16 store v4i16 v2 In big endian mode every memory access has an implicit byte swap. LDR and STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that is, they treat the vector as a sequence of elements to be byte-swapped. The two pairs of instructions are fundamentally incompatible. We've decided to use LD1/ST1 only to simplify compiler implementation. LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes the original code sequence: v0 = load v2i32 v1 = REV v2i32 (implicit) v2 = BITCAST v2i32 v1 to v4i16 v3 = REV v4i16 v2 (implicit) store v4i16 v3 But this is now broken - the value stored is different to the value loaded due to lane reordering. To fix this, on every BITCAST we must perform two other REVs: v0 = load v2i32 v1 = REV v2i32 (implicit) v2 = REV v2i32 v3 = BITCAST v2i32 v2 to v4i16 v4 = REV v4i16 v5 = REV v4i16 v4 (implicit) store v4i16 v5 This means an extra two instructions, but actually in most cases the two REV instructions can be combined into one. For example: (REV64_2s (REV64_4h X)) === (REV32_4h X) There is also no 128-bit REV instruction. This must be synthesized with an EXT instruction. Most bitconverts require some sort of conversion. The only exceptions are: a) Identity conversions - vNfX <-> vNiX b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX Even though there are hundreds of changed lines, I have a fairly high confidence that they are somewhat correct. The changes to add two REV instructions per bitcast were pretty mechanical, and once I'd done that I threw the resulting .td at a script I wrote which combined the two REVs together (and added an EXT instruction, for f128) based on an instruction description I gave it. This was much less prone to error than doing it all manually, plus my brain would not just have melted but would have vapourised. llvm-svn: 208194
* [ARM64-BE] Predicate VLDR/VSTR for vectors as little-endian only. We must ↵James Molloy2014-05-071-95/+131
| | | | | | use LD1/ST1 on big-endian. llvm-svn: 208193
* [ARM64-BE] Make big endian (scalar) argument passing work correctly.James Molloy2014-05-071-6/+38
| | | | | | | | | | This completes the port of r204814 (cpirker "AArch64_BE function argument passing for ARM ABI") from AArch64 to ARM64, and fixes a bunch of issues found during later development along the way. The biggest of these was that the alignment fixup logic wasn't replicated into all the places it should have been. llvm-svn: 208192
* MergeFunctions Pass, introduced total ordering among values.Stepan Dyatkovskiy2014-05-071-41/+96
| | | | | | | | | | | | | | | | | | | This is a third patch of patch series that improves MergeFunctions performance time from O(N*N) to O(N*log(N)). This patch description: Being comparing functions we need to compare values we meet at left and right sides. Its easy to sort things out for external values. It just should be the same value at left and right. But for local values (those were introduced inside function body) we have to ensure they were introduced at exactly the same place, and plays the same role. In short, patch introduces values serial numbering and comparison routine. The last one compares two values by their serial numbers. llvm-svn: 208189
* [mips] Split Instruction.Predicates into smaller lists and re-join them with ↵Daniel Sanders2014-05-077-77/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | !listconcat Summary: The overall idea is to chop the Predicates list into subsets that are usually overridden independently. This allows subclasses to partially override the predicates of their superclasses without having to re-add all the existing predicates. This patch starts the process by moving HasStdEnc into a new EncodingPredicates list and almost everything else into AdditionalPredicates. It has revealed a couple likely bugs where 'let Predicates' has removed the HasStdEnc predicate. No functional change (confirmed by diffing tablegen-erated files). Depends on D3549, D3506 Reviewers: vmedic Differential Revision: http://reviews.llvm.org/D3550 llvm-svn: 208184
* [tablegen] Add !listconcat operator with the similar semantics as !strconcatDaniel Sanders2014-05-074-2/+36
| | | | | | | | | | | | | | | | | | | | Summary: It concatenates two or more lists. In addition to the !strconcat semantics the lists must have the same element type. My overall aim is to make it easy to append to Instruction.Predicates rather than override it. This can be done by concatenating lists passed as arguments, or by concatenating lists passed in additional fields. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D3506 llvm-svn: 208183
* [mips] Move HasStdEnc to the front of the predicates lists.Daniel Sanders2014-05-075-61/+61
| | | | | | | | | | | | | | | | | | Summary: This will make it easier to prove that a more complicated change in the following commit is non-functional. No functional change. Depends on D3506 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3549 llvm-svn: 208179
* [BUG][REFACTOR]Zinovy Nis2014-05-073-43/+46
| | | | | | | | | 1) Fix for printing debug locations for absolute paths. 2) Location printing is moved into public method DebugLoc::print() to avoid re-inventing the wheel. Differential Revision: http://reviews.llvm.org/D3513 llvm-svn: 208177
* Second patch of patch series that improves MergeFunctions performance time ↵Stepan Dyatkovskiy2014-05-071-4/+278
| | | | | | | | | | | | | | | | | from O(N*N) to O(N*log(N)). The idea is to introduce total ordering among functions set. It allows to build binary tree and perform function look-up procedure in O(log(N)) time. This patch description: Introduced total ordering among constants implemented in cmpConstants method. Method performs lexicographical comparison between constants represented as hypothetical numbers of next format: <bitcastability-trait><raw-bit-contents> Please, read cmpConstants declaration comments for more details. llvm-svn: 208173
* Work-around MSVS build breakage due to r208148Timur Iskhodzhanov2014-05-071-2/+4
| | | | llvm-svn: 208171
* [asan] Add a flag to control asm instrumentation.Evgeniy Stepanov2014-05-071-1/+8
| | | | | | With this change, asm instrumentation is disabled by default. llvm-svn: 208167
* Allow using normal .eh_frame based unwinding on ARM. Use the sameJoerg Sonnenberger2014-05-073-1/+17
| | | | | | encodings as x86. Use this exception model for NetBSD. llvm-svn: 208166
* PR19562: DebugInfo temporary MDNode leak: Don't include a temporary node to ↵David Blaikie2014-05-071-2/+1
| | | | | | | | | | replace with a variable list for methods, since they're always declarations and thus never include variables This field is used for a list of variables to ensure they are not lost during optimization (they're only included when optimizations are enabled). llvm-svn: 208159
* [C++11] Add NArySCEV->Operands iterator rangeTobias Grosser2014-05-071-8/+6
| | | | llvm-svn: 208158
* ARM: mark additional instructions as MachineFrameSetupSaleem Abdulrasool2014-05-071-5/+10
| | | | | | | | Mark up additional instructions which are part of the function prologue as MachineFrameSetup. These instructions are part of the function prologue, emitted by the PEI pass to setup the stack for use in the activating frame. llvm-svn: 208153
* ARM: fix WoA PEI instruction selectionSaleem Abdulrasool2014-05-071-1/+2
| | | | | | | | | | | The ARM::BLX instruction is an ARM mode instruction. The Windows on ARM target is limited to Thumb instructions. Correctly use the thumb mode tBLXr instruction. This would manifest as an errant write into the object file as the instruction is 4-bytes in length rather than 2. The result would be a corrupted object file that would eventually result in an executable that would crash at runtime. llvm-svn: 208152
* llvm-cov: Handle missing source files as GCOV doesJustin Bogner2014-05-071-13/+29
| | | | | | | | | | | If the source files referenced by a gcno file are missing, gcov outputs a coverage file where every line is simply /*EOF*/. This also occurs for lines in the coverage that are past the end of a file that is found. This change mimics gcov. llvm-svn: 208149
* llvm-cov: Implement --no-outputJustin Bogner2014-05-071-15/+43
| | | | | | | | In gcov, there's a -n/--no-output option, which disables the writing of any .gcov files, so that it emits only the summary info on stdout. This implements the same behaviour in llvm-cov. llvm-svn: 208148
* [Support/MemoryBuffer] Remove the assertion that the file size did not shrink.Argyrios Kyrtzidis2014-05-061-3/+0
| | | | | | This can happen in practice with the user changing files and we can recover from it. llvm-svn: 208143
* Fix ASan init function detection after clang r208128.Nico Weber2014-05-061-3/+24
| | | | llvm-svn: 208141
* Special case aliases in GlobalValue::getSection.Rafael Espindola2014-05-062-1/+6
| | | | | | | | This is similar to the getAlignment patch, but is done just for completeness. It looks like we never call getSection on an alias. All the tests still pass if the if is replaced with an assert. llvm-svn: 208139
* Update an embarassing out-of-date comment.Andrew Trick2014-05-061-5/+6
| | | | llvm-svn: 208137
* Use a range based for loop for the SubtargetFeatures print function.Eric Christopher2014-05-061-2/+2
| | | | llvm-svn: 208132
* Revert "Try simplifying LexicalScopes ownership again."David Blaikie2014-05-061-32/+28
| | | | | | | | | Speculatively reverting due to a suspicious failure on a Windows buildbot. This reverts commit 10c37a012ea11596d44cd9059fe09c959caf30c8. llvm-svn: 208131
* Fix odd formatting that snuck into last patch.Eric Christopher2014-05-061-3/+3
| | | | llvm-svn: 208130
* If a function needs a frame pointer, but r11 (aka fp) has not been used,Joerg Sonnenberger2014-05-061-0/+4
| | | | | | | | remove it from the list of unspilled registers. Otherwise the following attempt to keep the stack aligned by picking an extra GPR register to spill will not work as it picks up r11. llvm-svn: 208129
* ArrayRef-ize the Feature and Processor tables for SubtargetFeatures.Eric Christopher2014-05-062-71/+52
| | | | | | | | This removes arguments passed everywhere and allows the use of standard iteration over lists. Should be no functional change. llvm-svn: 208127
* Copy the full TailCallKind in CallInst::clone_implReid Kleckner2014-05-061-1/+1
| | | | | | | Split from the musttail inliner change. This will be covered by an opt test when the inliner change lands. llvm-svn: 208126
* Do not make -pass-remarks additive.Diego Novillo2014-05-061-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: When I initially introduced -pass-remarks, I thought it would be a neat idea to make it additive. So, if one used it as: $ llc -pass-remarks=inliner --pass-remarks=loop.* the compiler would build the regular expression '(inliner)|(loop.*)'. The more I think about it, the more I regret it. This is not how other flags work. The standard semantics are right-to-left overrides. This is how clang interprets -Rpass. And I think the two should be compatible in this respect. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3614 llvm-svn: 208122
* TTI: Estimate @llvm.fmuladd cost as fmul + fadd when FMA's aren't legal on ↵Benjamin Kramer2014-05-061-1/+7
| | | | | | the target. llvm-svn: 208115
* [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 ↵Andrea Di Biagio2014-05-061-1/+41
| | | | | | | | | | | | | | | | | | | | (and vice versa). Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. llvm-svn: 208107
* Implememting named register intrinsicsRenato Golin2014-05-0612-0/+109
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* Special case aliases in GlobalValue::getAlignment.Rafael Espindola2014-05-062-1/+7
| | | | | | | | | An alias has the address of what it points to, so it also has the same alignment. This allows a few optimizations to see past aliases for free. llvm-svn: 208103
* Have the SubtargetFeature help routine just not return a number andEric Christopher2014-05-061-6/+4
| | | | | | | | fall back to the normal path without a cpu. While doing this fix llc to just exit when we don't have a module to process instead of asserting. llvm-svn: 208102
* Be more strict about not allowing setSection on aliases.Rafael Espindola2014-05-061-0/+5
| | | | llvm-svn: 208095
* Be more strict about not calling setAlignment on global aliases.Rafael Espindola2014-05-062-6/+15
| | | | | | | The fact that GlobalAlias::setAlignment exists at all is a side effect of how the classes are organized, it should never be used. llvm-svn: 208094
* AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover2014-05-061-17/+62
| | | | llvm-svn: 208091
* AArch64/ARM64: make NEON vector list parsing a bit more robustTim Northover2014-05-061-2/+5
| | | | | | | It doesn't change the results, but it seems silly not to diagnose obvious problems early on. llvm-svn: 208083
* AArch64/ARM64: add more specific diagnostic for floating imm 0.0.Tim Northover2014-05-061-4/+5
| | | | llvm-svn: 208082
OpenPOWER on IntegriCloud