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* Merge MCELF.h into MCSymbolELF.h.Rafael Espindola2015-06-0217-165/+158
| | | | | | | Now that we have a dedicated type for ELF symbol, these helper functions can become member function of MCSymbolELF. llvm-svn: 238864
* [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.Daniel Sanders2015-06-021-3/+9
| | | | | | | | | | | | | | | | | | | | | Summary: Following on from r209907 which made personality encodings indirect, do the same for TType encodings. This fixes the case where a try/catch block needs to generate references to, for example, std::exception in the .gcc_except_table. Previous attempts at committing this broke the buildbots due to bugs in IAS. These bugs have now been fixed so trying again. Reviewers: petarj Reviewed By: petarj Subscribers: srhines, joerg, tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9669 llvm-svn: 238863
* AArch64: fix typo in SMIN far atomics and add testsTim Northover2015-06-021-1/+1
| | | | llvm-svn: 238858
* DebugInfo: Really support 2^16 arguments in a subprogramDuncan P. N. Exon Smith2015-06-021-1/+1
| | | | | | | | As a follow-up to r235955, actually support up to 65535 arguments in a subprogram. r235955 missed assembly support, having only tested the new limit via C++ unit tests. Code patch by Amjad Aboud. llvm-svn: 238854
* [mips][mcjit] Add support for R_MIPS_PC32.Daniel Sanders2015-06-021-1/+5
| | | | | | | | | | | | | | | | | | Summary: This allows us to resolve relocations for DW_EH_PE_pcrel TType encodings in the exception handling LSDA. Also fixed a nearby typo. Reviewers: petarj, vkalintiris Reviewed By: vkalintiris Subscribers: vkalintiris, llvm-commits Differential Revision: http://reviews.llvm.org/D10127 llvm-svn: 238844
* Push constness through LoopInfo::isLoopHeader and clean it up a bit.Benjamin Kramer2015-06-021-2/+1
| | | | | | NFC. llvm-svn: 238843
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-027-54/+267
| | | | | | | | | | | | | | | | | | | command-line options (2nd try) The first try (r238051) to land this was reverted due to bot failures that were hopefully addressed by r238788. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238842
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+7
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Shorten implementation of lowerV16X32VectorShuffle()Elena Demikhovsky2015-06-021-39/+61
| | | | | | | using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines. Added matching of VALIGN instruction. llvm-svn: 238830
* [mips] Add support for dynamic stack realignment.Vasileios Kalintiris2015-06-028-8/+141
| | | | | | | | | | | | | | | | | | | | Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 llvm-svn: 238829
* Simplify now that we always use an alignment of 2 for ELF files.Rafael Espindola2015-06-022-46/+22
| | | | | | This saves 123144 bytes out of llvm-nm on powerpc64le. llvm-svn: 238824
* Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin2015-06-021-22/+20
| | | | | | | | | This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. llvm-svn: 238821
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-028-5/+432
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-023-0/+48
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-021-14/+51
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-025-107/+25
| | | | llvm-svn: 238810
* AVX-512: Implemented GETEXP instruction for KNL and SKXAsaf Badouh2015-06-025-25/+107
| | | | | | | Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. llvm-svn: 238809
* [TableGen] Use range-based for loops. NFCCraig Topper2015-06-021-12/+10
| | | | llvm-svn: 238808
* [TableGen] Rename ListInit::getSize to just 'size' to be more consistent.Craig Topper2015-06-022-6/+6
| | | | llvm-svn: 238806
* [TableGen] Use range-based for loops. NFC.Craig Topper2015-06-021-11/+10
| | | | llvm-svn: 238805
* [RuntimeDydlELF] Use range-based loop.Davide Italiano2015-06-021-5/+3
| | | | | | | Differential Revision: http://reviews.llvm.org/D10165 Reviewed by: rafael llvm-svn: 238804
* Create a MCSymbolELF.Rafael Espindola2015-06-0212-39/+47
| | | | | | | | | This create a MCSymbolELF class and moves SymbolSize since only ELF needs a size expression. This reduces the size of MCSymbol from 56 to 48 bytes. llvm-svn: 238801
* MC: Tidy up LOH naming a bit. NFC.Jim Grosbach2015-06-012-2/+2
| | | | llvm-svn: 238800
* [Support] Simplify Triple::getOSVersionDavid Majnemer2015-06-011-9/+1
| | | | | | | Those who are interested in the Android version can use getEnvironmentVersion instead of getOSVersion. llvm-svn: 238798
* [ADT] Add Triple::getEnvironmentVersionDavid Majnemer2015-06-011-16/+40
| | | | | | | | This allows us to extract version numbers from the environment. getOSVersion is currently overloaded for that purpose, this allows us to clean it up. llvm-svn: 238796
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-011-20/+22
| | | | | | | | | | | | | The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 llvm-svn: 238795
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-014-72/+255
| | | | | | | | | | | | Previously CCMP/FCCMP instructions were only used by the AArch64ConditionalCompares pass for control flow. This patch uses them for SELECT like instructions as well by matching patterns in ISelLowering. PR20927, rdar://18326194 Differential Revision: http://reviews.llvm.org/D8232 llvm-svn: 238793
* [bpf] fix buildAlexei Starovoitov2015-06-011-2/+2
| | | | | | | | fix breakage due to r238634 Patch by Vijay Subramanian. llvm-svn: 238792
* Move the name pointer out of Value into a map that lives on theOwen Anderson2015-06-013-10/+41
| | | | | | | | | | | | | | | | LLVMContext. Production builds of clang do not set names on most Value's, so this is wasted space on almost all subclasses of Value. This reduces the size of all Value subclasses by 8 bytes on 64 bit hosts. The one tricky part of this change is averting compile time regression by keeping Value::hasName() fast. This required stealing bits out of NumOperands. With this change, peak memory usage on verify-uselistorder-nodbg.lto.bc is decreased by approximately 2.3% (~3MB absolute on my machine). llvm-svn: 238791
* R600/SI: Don't hardcode pointer typeMatt Arsenault2015-06-011-4/+5
| | | | llvm-svn: 238789
* add missing dependency for ExecutionEngine libSanjay Patel2015-06-012-1/+2
| | | | | | | This appears to be masked most of the time, but the problem was exposed on some bots by r238051. llvm-svn: 238788
* LiveRangeEdit: Fix liveranges not shrinking on subrange kill.Matthias Braun2015-06-011-3/+18
| | | | | | | | | | | | | | If a dead instruction we may not only have a last-use in the main live range but also in a subregister range if subregisters are tracked. We need to partially rebuild live ranges in both cases. The testcase only broke when subregister liveness was enabled. I commited it in the current form because there is currently no flag to enable/disable subregister liveness. This fixes PR23720. llvm-svn: 238785
* ARMLoadStoreOptimizer: Fix doxygen comments; NFCMatthias Braun2015-06-011-34/+28
| | | | llvm-svn: 238784
* Make the C++ LTO API easier to use from C++ clients.Peter Collingbourne2015-06-011-14/+7
| | | | | | | | | | | Start using C++ types such as StringRef and MemoryBuffer in the C++ LTO API. In doing so, clarify the ownership of the native object file: the caller now owns it, not the LTOCodeGenerator. The C libLTO library has been modified to use a derived class of LTOCodeGenerator that owns the object file. Differential Revision: http://reviews.llvm.org/D10114 llvm-svn: 238776
* Revert "[Hexagon] Adding basic ELF relocation generation and testing ↵Rafael Espindola2015-06-013-427/+28
| | | | | | | | | | | | advanced relaxation codepath." This reverts commit r238748. It broke the msan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio llvm-svn: 238772
* Disable MachineSink on convergent operations, similar to how IR Sink isOwen Anderson2015-06-011-0/+4
| | | | | | | restricted. No test because no in-tree target currently has convergent MachineInstr's. llvm-svn: 238763
* Teach the IR Sink pass to (conservatively) respect convergent annotations.Owen Anderson2015-06-011-0/+6
| | | | llvm-svn: 238762
* [mips][FastISel] Implement bswap.Vasileios Kalintiris2015-06-011-0/+64
| | | | | | | | | | | | | | | | | | Summary: Implement bswap intrinsic for MIPS FastISel. It's very different for misp32 r1/r2 . Based on a patch by Reed Kotler. Test Plan: bswap1.ll test-suite Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7219 llvm-svn: 238760
* [mips][FastISel] Implement intrinsics memset, memcopy & memmove.Vasileios Kalintiris2015-06-011-7/+89
| | | | | | | | | | | | | | | | | | | | Summary: Implement the intrinsics memset, memcopy and memmove in MIPS FastISel. Make some needed infrastructure fixes so that this can work. Based on a patch by Reed Kotler. Test Plan: memtest1.ll The patch passes test-suite for mips32 r1/r2 and at O0/O2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7158 llvm-svn: 238759
* [mips][FastISel] Implement srem/urem and sdiv/udiv instructions.Vasileios Kalintiris2015-06-011-0/+61
| | | | | | | | | | | | | | | | | | | Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
* [mips][FastISel] Implement the select statement for MIPS FastISel.Vasileios Kalintiris2015-06-011-0/+47
| | | | | | | | | | | | | | | | | | Summary: Implement the LLVM IR select statement for MIPS FastISelsel. Based on a patch by Reed Kotler. Test Plan: "Make check" test included now. Passes test-suite at O2/O0 mips32 r1/r2. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6774 llvm-svn: 238756
* [mips][FastISel] Clobber HI0/LO0 registers in MUL instructions.Vasileios Kalintiris2015-06-011-0/+33
| | | | | | | | | | | | | | | | | | | | | Summary: The contents of the HI/LO registers are unpredictable after the execution of the MUL instruction. In addition to implicitly defining these registers in the MUL instruction definition, we have to mark those registers as dead too. Without this the fast register allocator is running out of registers when the MUL instruction is followed by another one that tries to allocate the AC0 register. Based on a patch by Reed Kotler. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D9825 llvm-svn: 238755
* Fix relocation selection for foo-. on mips.Rafael Espindola2015-06-011-1/+1
| | | | | | This handles only the 32 bit case. llvm-svn: 238751
* Simplify code, NFC.Rafael Espindola2015-06-011-107/+60
| | | | llvm-svn: 238750
* Add isConstant argument to MDBuilder::createTBAAStructTagNodeArtur Pilipenko2015-06-011-4/+11
| | | | | | | | | | According to the TBAA description struct-path tag node can have an optional IsConstant field. Add corresponding argument to MDBuilder::createTBAAStructTagNode. Reviewed By: hfinkel Differential Revision: http://reviews.llvm.org/D10160 llvm-svn: 238749
* [Hexagon] Adding basic ELF relocation generation and testing advanced ↵Colin LeMahieu2015-06-013-28/+427
| | | | | | relaxation codepath. llvm-svn: 238748
* The fragment implies the section, don't store both.Rafael Espindola2015-06-014-3/+15
| | | | | | This reduces MCSymbol from 64 to 56 bytes on x86_64. llvm-svn: 238747
* AVX-512: Optimized vector shuffle for v16f32 and v16i32 types.Elena Demikhovsky2015-06-011-36/+48
| | | | llvm-svn: 238743
* Re-commit of r238201 with fix for building with shared libraries.Luke Cheeseman2015-06-017-18/+629
| | | | llvm-svn: 238739
* AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.Elena Demikhovsky2015-06-014-6/+34
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238738
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