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* [InstCombine] Don't create extra ConstantInt objects in foldSelectICmpAnd. NFCICraig Topper2017-07-061-19/+17
| | | | | | Instead just use APInt objects and only create a ConstantInt at the end if we need it for the Offset. llvm-svn: 307270
* [LSR] Narrow search space by filtering non-optimal formulae with the same ↵Wei Mi2017-07-061-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ScaledReg and Scale. When the formulae search space is huge, LSR uses a series of heuristic to keep pruning the search space until the number of possible solutions are within certain limit. The big hammer of the series of heuristics is NarrowSearchSpaceByPickingWinnerRegs, which picks the register which is used by the most LSRUses and deletes the other formulae which don't use the register. This is a effective way to prune the search space, but quite often not a good way to keep the best solution. We saw cases before that the heuristic pruned the best formula candidate out of search space. To relieve the problem, we introduce a new heuristic called NarrowSearchSpaceByFilterFormulaWithSameScaledReg. The basic idea is in order to reduce the search space while keeping the best formula, we want to keep as many formulae with different Scale and ScaledReg as possible. That is because the central idea of LSR is to choose a group of loop induction variables and use those induction variables to represent LSRUses. An induction variable candidate is often represented by the Scale and ScaledReg in a formula. If we have more formulae with different ScaledReg and Scale to choose, we have better opportunity to find the best solution. That is why we believe pruning search space by only keeping the best formula with the same Scale and ScaledReg should be more effective than PickingWinnerReg. And we use two criteria to choose the best formula with the same Scale and ScaledReg. The first criteria is to select the formula using less non shared registers, and the second criteria is to select the formula with less cost got from RateFormula. The patch implements the heuristic before NarrowSearchSpaceByPickingWinnerRegs, which is the last resort. Testing shows we get 1.8% and 2% on two internal benchmarks on x86. llvm nightly testsuite performance is neutral. We also tried lsr-exp-narrow and it didn't help on the two improved internal cases we saw. Differential Revision: https://reviews.llvm.org/D34583 llvm-svn: 307269
* [X86][SSE4A] Add support for shuffle combining to INSERTQI.Simon Pilgrim2017-07-061-0/+16
| | | | llvm-svn: 307268
* Doxygen formatting. NFCIJoel Jones2017-07-061-2/+12
| | | | llvm-svn: 307263
* [MachineVerifier] Add check that tied physregs aren't different.Mikael Holmen2017-07-061-0/+8
| | | | | | | | | | | | | | | | Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files. Original patch by Jesper Antonsson Reviewers: stoklund, sanjoy, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D34394 llvm-svn: 307259
* [X86][SSE] combineX86ShuffleChain - merge duplicate creations of integer ↵Simon Pilgrim2017-07-061-20/+12
| | | | | | mask types llvm-svn: 307257
* [X86][SSE] combineX86ShuffleChain - merge duplicate 'Zeroable' element masksSimon Pilgrim2017-07-061-20/+12
| | | | llvm-svn: 307255
* [X86][SSE4A] Add support for shuffle combining to EXTRQ.Simon Pilgrim2017-07-061-1/+28
| | | | llvm-svn: 307254
* [X86][SSE4A] Split EXTRQ/INSERTQ shuffle matching from lowering. NFCI.Simon Pilgrim2017-07-061-99/+112
| | | | | | First step toward supporting shuffle combining to EXTRQ/INSERTQ. llvm-svn: 307250
* Revert "Revert "Revert "[IndVars] Canonicalize comparisons between ↵Max Kazantsev2017-07-061-4/+0
| | | | | | | | | non-negative values and indvars""" It appears that the problem is still there. Needs more analysis to understand why SaturatedMultiply test fails. llvm-svn: 307249
* [RegisterCoalescer] Fix for SubRange join unreachableDavid Stuttard2017-07-061-0/+28
| | | | | | | | | | | | | | | | Summary: During remat, some subranges might end up having invalid segments which caused problems for later coalescing. Added in a check to remove segments that are invalidated as part of the remat. See http://llvm.org/PR33524 Subscribers: MatzeB, qcolombet Differential Revision: https://reviews.llvm.org/D34391 llvm-svn: 307247
* [ARM] GlobalISel: Map s32 G_FCMP in reg bank selectDiana Picus2017-07-061-0/+14
| | | | | | Map hard G_FCMP operands to FPR and the result to GPR. llvm-svn: 307245
* Revert "Revert "[IndVars] Canonicalize comparisons between non-negative ↵Max Kazantsev2017-07-061-0/+4
| | | | | | | | | | | | | values and indvars"" It seems that the patch was reverted by mistake. Clang testing showed failure of the MathExtras.SaturatingMultiply test, however I was unable to reproduce the issue on the fresh code base and was able to confirm that the transformation introduced by the change does not happen in the said test. This gives a strong confidence that the actual reason of the failure of the initial patch was somewhere else, and that problem now seems to be fixed. Re-submitting the change to confirm that. llvm-svn: 307244
* [ARM] GlobalISel: Legalize G_FCMP for s32Diana Picus2017-07-063-0/+164
| | | | | | | | | | | | | | | | | | | | | This covers both hard and soft float. Hard float is easy, since it's just Legal. Soft float is more involved, because there are several different ways to handle it based on the predicate: one and ueq need not only one, but two libcalls to get a result. Furthermore, we have large differences between the values returned by the AEABI and GNU functions. AEABI functions return a nice 1 or 0 representing true and respectively false. GNU functions generally return a value that needs to be compared against 0 (e.g. for ogt, the value returned by the libcall is > 0 for true). We could introduce redundant comparisons for AEABI as well, but they don't seem easy to remove afterwards, so we do different processing based on whether or not the result really needs to be compared against something (and just truncate if it doesn't). llvm-svn: 307243
* [ARM] GlobalISel: Widen s1, s8, s16 G_CONSTANTDiana Picus2017-07-061-0/+2
| | | | | | Get the legalizer to widen small constants. llvm-svn: 307239
* Avoid constructing GlobalExtensions only to find out it is empty.Frederich Munch2017-07-061-4/+14
| | | | | | | | | | | | | | | | Summary: GlobalExtensions is dereferenced twice, once for iteration and then a check if it is empty. As a ManagedStatic this dereference forces it's construction which is unnecessary. Reviewers: efriedma, davide, mehdi_amini Reviewed By: mehdi_amini Subscribers: chapuni, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D33381 llvm-svn: 307229
* Revert "Revert "Revert "Switch external cvtres.exe for llvm's own resource ↵Eric Beckmann2017-07-051-1/+0
| | | | | | | | | | | | | | library.""" This reverts commit ae21ee0b6cacbc1efaf4d42502e71da2f0eb45c3. The initial revert was done in order to prevent ongoing errors on chromium bots such as CrWinClangLLD. However, this was done haphazardly and I didn't realize there were test and compilation failures, so this revert was reverted. Now that those have been fixed, we can revert the revert of the revert. llvm-svn: 307227
* Revert "Revert "Revert "Replace trivial use of external rc.exe by writing ↵Eric Beckmann2017-07-052-10/+17
| | | | | | | | | | | | | | our own .res file.""" This reverts commit 5fecbbbe5049665d86834cf69d8f75db4f392308. The initial revert was done in order to prevent ongoing errors on chromium bots such as CrWinClangLLD. However, this was done haphazardly and I didn't realize there were test and compilation failures, so this revert was reverted. Now that those have been fixed, we can revert the revert of the revert. llvm-svn: 307226
* [IR] Use CmpInst::isFPPredicate/isIntPredicate in a few other places. NFCCraig Topper2017-07-052-7/+6
| | | | llvm-svn: 307224
* [GlobalOpt] Remove unreachable blocks before optimizing a function.Davide Italiano2017-07-051-0/+18
| | | | | | | | | | | | | | | | | LLVM's definition of dominance allows instructions that are cyclic in unreachable blocks, e.g.: %pat = select i1 %condition, @global, i16* %pat because any instruction dominates an instruction in a block that's not reachable from entry. So, remove unreachable blocks from the function, because a) there's no point in analyzing them and b) GlobalOpt should otherwise grow some more complicated logic to break these cycles. Differential Revision: https://reviews.llvm.org/D35028 llvm-svn: 307215
* Fix libcall expansion creating DAG nodes with invalid type post type ↵Vadim Chugunov2017-07-052-12/+25
| | | | | | | | | | | | legalization. If we are lowering a libcall after legalization, we'll split the return type into a pair of legal values. Patch by Jatin Bhateja and Eli Friedman. Differential Revision: https://reviews.llvm.org/D34240 llvm-svn: 307207
* [DependenceAnalysis] Make sure base objects are the same when comparing GEPsBrendon Cahoon2017-07-051-1/+2
| | | | | | | | | | | | | | | The dependence analysis was returning incorrect information when using the GEPs to compute dependences. The analysis uses the GEP indices under certain conditions, but was doing it incorrectly when the base objects of the GEP are aliases, but pointing to different locations in the same array. This patch adds another check for the base objects. If the base pointer SCEVs are not equal, then the dependence analysis should fall back on the path that uses the whole SCEV for the dependence check. This fixes PR33567. Differential Revision: https://reviews.llvm.org/D34702 llvm-svn: 307203
* [InstCombine] Use CmpInst::Predicate with m_Cmp instead of ↵Craig Topper2017-07-051-1/+1
| | | | | | | | ICmpInst::Predicate. NFC There isn't really an ICmpInst version so we're just accessing the CmpInst version through inheritance. llvm-svn: 307199
* [WebAssembly] Fix types for address taken functionsSam Clegg2017-07-055-18/+29
| | | | | | Differential Revision: https://reviews.llvm.org/D34966 llvm-svn: 307198
* [WebAssembly] MC: Don't generate extra types for weak aliasSam Clegg2017-07-051-0/+4
| | | | | | | | | | Previously we were generating a void(void) function type for a weak alias. Update the weak-alias test case to catch this. Differential Revision: https://reviews.llvm.org/D34734 llvm-svn: 307194
* Revert "Revert "Replace trivial use of external rc.exe by writing our own ↵Eric Beckmann2017-07-052-17/+10
| | | | | | | | .res file."" This reverts commit 8c8dce3b8f15d6ebaefc35ce88f15a85c8cdbd6e. llvm-svn: 307191
* Revert "Revert "Switch external cvtres.exe for llvm's own resource library.""Eric Beckmann2017-07-051-1/+2
| | | | | | | | This reverts commit 165e578e47f1cd38191120aad23a9020fb5476dd. Forgot to run tests on this. llvm-svn: 307190
* Revert "Switch external cvtres.exe for llvm's own resource library."Eric Beckmann2017-07-051-2/+1
| | | | | | | | | This reverts commit 600d52c278e123dd08bee24c1f00932b55add8de. This patch still seems to break CrWinClangLLD, reverting until I can find root problem. llvm-svn: 307189
* Revert "Replace trivial use of external rc.exe by writing our own .res file."Eric Beckmann2017-07-052-10/+17
| | | | | | | | | This patch still seems to break CrWinClangLLD, reverting this once more until I can discover root problem. This reverts commit 3dbbc8ce43be50ffde2b1c655c6d3a25796fe78b. llvm-svn: 307188
* [AMDGPU] Move GISel accessor initialization from TargetMachine to Subtarget.Quentin Colombet2017-07-052-48/+50
| | | | | | NFC llvm-svn: 307186
* [Power9] Disable removing extra swaps on P9.Sean Fertile2017-07-051-1/+3
| | | | | | | | | | | | On power 8 we sometimes insert swaps to deal with the difference between Little-Endian and Big-Endian. The swap removal pass is supposed to clean up these swaps. On power 9 we don't need this pass since we do not need to insert the swaps in the first place. Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34627 llvm-svn: 307185
* {DAGCombiner] Fold (rot x, 0) -> xSimon Pilgrim2017-07-051-0/+4
| | | | llvm-svn: 307184
* [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.Sean Fertile2017-07-051-1/+4
| | | | | | | Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34829 llvm-svn: 307180
* [DAGCombiner] visitRotate patch to optimize pair of ROTR/ROTL instructions ↵Andrew Zhogin2017-07-051-0/+19
| | | | | | | | | | into one with combined shift operand. For two ROTR operations with shifts C1, C2; combined shift operand will be (C1 + C2) % bitsize. Differential revision: https://reviews.llvm.org/D12833 llvm-svn: 307179
* [Power9] Exploit vector extract with variable index.Tony Jiang2017-07-051-0/+92
| | | | | | | | | | | | | | | | This patch adds the exploitation for new power 9 instructions which extract variable elements from vectors: VEXTUBLX VEXTUBRX VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX Differential Revision: https://reviews.llvm.org/D34032 Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) llvm-svn: 307174
* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-054-26/+216
| | | | | | | | | | | | | | | This patch adds on to the exploitation added by https://reviews.llvm.org/D33510. This now catches build vector nodes where the inputs are coming from sign extended vector extract elements where the indices used by the vector extract are not correct. We can still use the new hardware instructions by adding a shuffle to move the elements to the correct indices. I introduced a new PPCISD node here because adding a vector_shuffle and changing the elements of the vector_extracts was getting undone by another DAG combine. Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) Differential Revision: https://reviews.llvm.org/D34009 llvm-svn: 307169
* DebugInfo: Generalize LoadedObjectInfoHelper from RuntimeDyldDavid Blaikie2017-07-053-4/+9
| | | | | | | | Make it usable by any class derived (even indirectly) from LoadedObjectInfo by allowing a custom base class to be specified and perfect forwarding to the ctor. llvm-svn: 307166
* [globalisel][tablegen] Finish fixing compile-time regressions by merging the ↵Daniel Sanders2017-07-051-149/+0
| | | | | | | | | | | | | | | | | | | | | | | matcher and emitter state machines. Summary: Also, made a few minor tweaks to shave off a little more cumulative memory consumption: * All rules share a single NewMIs instead of constructing their own. Only one will end up using it. * Use MIs.resize(1) instead of MIs.clear();MIs.push_back(I) and prevent GIM_RecordInsn from changing MIs[0]. Depends on D33764 Reviewers: rovka, vitalybuka, ab, t.p.northover, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33766 llvm-svn: 307159
* [SLPVectorizer] Add an extra parameter to cancelScheduling function, NFCI.Dinar Temirbulatov2017-07-051-22/+23
| | | | llvm-svn: 307158
* [IndVarSimplify] Add AShr exact flags using induction variables ranges.David Green2017-07-051-2/+34
| | | | | | | | | | This adds exact flags to AShr/LShr flags where we can statically prove it is valid using the range of induction variables. This allows further optimisations to remove extra loads. Differential Revision: https://reviews.llvm.org/D34207 llvm-svn: 307157
* [SystemZ] Simplify handling of 128-bit multiply/divide instructionUlrich Weigand2017-07-057-106/+106
| | | | | | | | | | | Several integer multiply/divide instructions require use of a register pair as input and output. This patch moves setting up the input register pair from C++ code to TableGen, simplifying the whole process and making it more easily extensible. No functional change. llvm-svn: 307155
* [SystemZ] Small cleanups to SystemZScheduleZ13.tdUlrich Weigand2017-07-051-25/+36
| | | | | | | | | | Fixes a couple of whitespace errors, re-sorts the vector floating-point instructions to make them more easily extensible, and adds a missing pseudo instruction. No functional change. llvm-svn: 307154
* [GlobalISel] Refactor Legalizer helpers for libcallsDiana Picus2017-07-052-20/+29
| | | | | | | | | | We used to have a helper that replaced an instruction with a libcall. That turns out to be too aggressive, since sometimes we need to replace the instruction with at least two libcalls. Therefore, change our existing helper to only create the libcall and leave the instruction removal as a separate step. Also rename the helper accordingly. llvm-svn: 307149
* [AsmParser] Mnemonic Spell CorrectorSjoerd Meijer2017-07-051-2/+8
| | | | | | | | | | | | | | | | | | This implements suggesting other mnemonics when an invalid one is specified, for example: $ echo "adXd r1,r2,#3" | llvm-mc -triple arm <stdin>:1:1: error: invalid instruction, did you mean: add, qadd? adXd r1,r2,#3 ^ The implementation is target agnostic, but as a first step I have added it only to the ARM backend; so the ARM backend is a good example if someone wants to enable this too for another target. Differential Revision: https://reviews.llvm.org/D33128 llvm-svn: 307148
* [ARM] GlobalISel: Extract tiny helper. NFCDiana Picus2017-07-051-2/+5
| | | | | | Extract functionality for determining if the target uses AEABI. llvm-svn: 307145
* [MachineIRBuilder] Fix formatting. NFC.Diana Picus2017-07-051-1/+1
| | | | llvm-svn: 307144
* [GlobalISel][X86] For now don't handle not trivial function arguments lowering.Igor Breger2017-07-051-1/+11
| | | | llvm-svn: 307142
* [MachineIRBuilder] Add buildOr helper. NFC.Diana Picus2017-07-051-0/+4
| | | | | | This isn't used anywhere yet, but I need it for a future commit. llvm-svn: 307141
* [GlobalIsel] allow x86_fp80 values to be dumped.Igor Breger2017-07-051-0/+8
| | | | | | | | | | | | | | | | Summary: Otherwise the fallback path fails with an assertion on x86_64 targets, when "x86_fp80" is encountered. Reviewers: t.p.northover, zvi, guyblank Reviewed By: zvi Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34975 llvm-svn: 307140
* [MachineIRBuilder] Add buildBinaryOp helper. NFCDiana Picus2017-07-051-29/+11
| | | | | | | Add a helper for building simple binary ops like add, mul, sub, and. This can be used in the future for quickly adding support for or, xor. llvm-svn: 307139
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