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* Split byval argument initialization so the memcpy(s) are injected at theJulien Lerouge2014-04-151-29/+42
| | | | | | beginning of the first new block after inlining. llvm-svn: 206307
* LTO: Add more loop simplification passes to LTODuncan P. N. Exon Smith2014-04-151-1/+3
| | | | | | | | | Similar to r202051, add missing loop simplification passes to the LTO optimization pipeline. Patch by Rafael Espindola. llvm-svn: 206306
* verify-di: Add back braces for MSVC compatabilityDuncan P. N. Exon Smith2014-04-151-5/+12
| | | | | | | | Fixup after r206300. <rdar://problem/15500563> llvm-svn: 206305
* verify-di: Implement DebugInfoVerifierDuncan P. N. Exon Smith2014-04-154-50/+105
| | | | | | | | | | | | | | | | | | | | | Implement DebugInfoVerifier, which steals verification relying on DebugInfoFinder from Verifier. - Adds LegacyDebugInfoVerifierPassPass, a ModulePass which wraps DebugInfoVerifier. Uses -verify-di command-line flag. - Change verifyModule() to invoke DebugInfoVerifier as well as Verifier. - Add a call to createDebugInfoVerifierPass() wherever there was a call to createVerifierPass(). This implementation as a module pass should sidestep efficiency issues, allowing us to turn debug info verification back on. <rdar://problem/15500563> llvm-svn: 206300
* verify-di: split out VerifierSupportDuncan P. N. Exon Smith2014-04-151-57/+62
| | | | | | | | | Split out assertion and output helpers from Verifier in preparation for writing the DebugInfoVerifier. <rdar://problem/15500563> llvm-svn: 206299
* Use unique_ptr to manage PassInfo instances in the PassRegistryDavid Blaikie2014-04-151-8/+4
| | | | llvm-svn: 206297
* MipsAsmParser.cpp: Fix vg_leak in MipsOperand::CreateMem(). Mem.Base is ↵NAKAMURA Takumi2014-04-151-0/+16
| | | | | | managed by k_Memory itself. llvm-svn: 206293
* MipsAsmParser::ParseRegister(): Be responsible to delete an Operand on a ↵NAKAMURA Takumi2014-04-151-0/+2
| | | | | | temporary Operands. llvm-svn: 206292
* AArch64/ARM64: add missing pattern for extending load.Tim Northover2014-04-151-0/+2
| | | | llvm-svn: 206290
* AArch64/ARM64: only mangle MOVZ/MOVN during encoding when neededTim Northover2014-04-151-0/+16
| | | | | | | | Sometimes we need emit the bits that would actually be a MOVN when producing a relocated MOVZ instruction (don't ask). But not always, a check which ARM64 got wrong until now. llvm-svn: 206289
* AArch64/ARM64: add support for large code-model jump tables.Tim Northover2014-04-152-0/+18
| | | | | | | I've left the MachO CodeGen as it is, there's a reasonable chance it should use the GOT like ConstPools, but I'm not certain. llvm-svn: 206288
* AArch64/ARM64: add patterns for various commutations of FNMADD.Tim Northover2014-04-151-0/+14
| | | | llvm-svn: 206287
* AArch64/ARM64: add half as a storage type on ARM64.Tim Northover2014-04-154-15/+19
| | | | | | | This brings it into line with the AArch64 behaviour and should open the way for certain OpenCL features. llvm-svn: 206286
* AArch64/ARM64: copy patterns for fixed-point conversionsTim Northover2014-04-152-15/+98
| | | | | | | | Code is mostly copied directly across, with a slight extension of the ISelDAGToDAG function so that it can cope with the floating-point constants being behind a litpool. llvm-svn: 206285
* ARM64: add constraints to various FastISel operationsTim Northover2014-04-151-6/+13
| | | | llvm-svn: 206284
* FastISel: constrain the RegClass of operands when emitting instructions.Tim Northover2014-04-152-27/+47
| | | | | | | | | | | ARM64 suffered multiple -verify-machineinstr failures (principally over the xsp/xzr issue) because FastISel was completely ignoring which subset of the general-purpose registers each instruction required. More fixes are coming in ARM64 specific FastISel, but this should cover the generic problems. llvm-svn: 206283
* AArch64/ARM64: add dp tests from AArch64Tim Northover2014-04-151-0/+5
| | | | llvm-svn: 206281
* ARM64AsmParser.cpp: Fix vg_leak in MC/ARM64/fp-encoding.s.NAKAMURA Takumi2014-04-151-0/+2
| | | | llvm-svn: 206279
* Optional hash symbol feature support for ARM64Stepan Dyatkovskiy2014-04-151-16/+37
| | | | | | http://reviews.llvm.org/D3328 llvm-svn: 206276
* Current definition of subtract with immediate instruction aliases uses ↵Vladimir Medic2014-04-153-49/+14
| | | | | | CodeGenOnly defined instructions and post matcher expansion methods to emit real instructions add with immediate. However, they can directly alias add with immediate instruction and remove unnecessary definitions and code in MipsAsmParser.cpp. This patch makes no change in functionality, just removes unnecessary definitions and code. llvm-svn: 206272
* [Allocator] Finally, finish nuking the redundant code that led me hereChandler Carruth2014-04-151-7/+7
| | | | | | | | | | | | | | | | by removing the MallocSlabAllocator entirely and just using MallocAllocator directly. This makes all off these allocators expose and utilize the same core interface. The only ugly part of this is that it exposes the fact that the JIT allocator has no real handling of alignment, any more than the malloc allocator does. =/ It would be nice to fix both of these to support alignments, and then to leverage that in the BumpPtrAllocator to do less over allocation in order to manually align pointers. But, that's another patch for another day. This patch has no functional impact, it just removes the somewhat meaningless wrapper around MallocAllocator. llvm-svn: 206267
* D3348 - [BUG] "Rotate Loop" pass kills "llvm.vectorizer.enable" metadataAlexey Bataev2014-04-152-6/+23
| | | | llvm-svn: 206266
* X86JITInfo: [x86] Rework r206240, X86CompilationCallback_SSE() should be ↵NAKAMURA Takumi2014-04-151-1/+7
| | | | | | called for SSE-enabled code generator, even if LLVM is not built with -msse. llvm-svn: 206261
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-1523-306/+241
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-1549-364/+368
| | | | | | instead of comparing to nullptr. llvm-svn: 206252
* Use unique_ptr to manage TypePromotionActions owned by TypePromotionTransaction.David Blaikie2014-04-151-28/+19
| | | | llvm-svn: 206250
* Use unique_ptr to manage ownership of GCFunctionInfos in GCStrategyDavid Blaikie2014-04-151-10/+2
| | | | llvm-svn: 206249
* Use unique_ptr for the result of Registry entries.David Blaikie2014-04-152-8/+6
| | | | llvm-svn: 206248
* Use unique_ptr to manage ownership of GCStrategy objects in GCMetadataDavid Blaikie2014-04-152-19/+12
| | | | llvm-svn: 206246
* Use unique_ptr for section/segment ownership in WinCOFFObjectWriterDavid Blaikie2014-04-151-41/+32
| | | | llvm-svn: 206245
* Use unique_ptr to own MCFunctions within MCModule.David Blaikie2014-04-153-12/+12
| | | | | | | | MCModule's ctor had to be moved out of line so the definition of MCFunction was available. (ctor requires the dtor of members (in case the ctor throws) which required access to the dtor of MCFunction) llvm-svn: 206244
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-1539-505/+512
| | | | | | instead of comparing to nullptr. llvm-svn: 206243
* Use std::unique_ptr to manage MCBasicBlocks in MCFunction.David Blaikie2014-04-152-15/+10
| | | | llvm-svn: 206242
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-1512-65/+75
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* X86JITInfo: [x86] Use X86CompilationCallback_SSE() along;NAKAMURA Takumi2014-04-151-3/+2
| | | | | | | | | | *not* Subtarget->hasSSE1() *but* __SSE__, the flag that LLVM libraries are compiled The callback calls internal LLVM JIT libraries. It may be built with -msse (or above). FIXME: JIT may use "host" instead of "generic" by default. llvm-svn: 206240
* [ARM64,C++11]: Range'ify the dead-register-definition pass.Jim Grosbach2014-04-151-27/+23
| | | | | | Range-based for loops. No functional change intended. llvm-svn: 206239
* [MC] Emit an error if cfi_startproc is used before a symbol is defined.Quentin Colombet2014-04-151-0/+4
| | | | | | | | | Currently, we bind those directives with the last symbol, so if none has been defined, this would lead to a crash of the compiler. <rdar://problem/15939159> llvm-svn: 206236
* [ARM64][MC] Set the default CPU string to generic.Quentin Colombet2014-04-151-3/+1
| | | | llvm-svn: 206228
* Use std::unique_ptr for DIE childrenDavid Blaikie2014-04-145-43/+31
| | | | | | | | | Got bored, removed some manual memory management. Pushed references (rather than pointers) through a few APIs rather than replacing *x with x.get(). llvm-svn: 206222
* X86: Nuke one more CPU autodetect blurb.Jim Grosbach2014-04-141-7/+1
| | | | | | Missed one in r206094. This brings MC and TargetMachine back into sync. llvm-svn: 206220
* Change argument order and add explanatory comment to r206130David Blaikie2014-04-142-9/+9
| | | | | | Changes requested in code review by Eric Christopher of r206130. llvm-svn: 206219
* Use FrameSetup on frame instructions for the Mips port.Eric Christopher2014-04-142-2/+3
| | | | | | | I can't seem to get a testcase to show a difference here, but it's part of the unconditional-br.ll line table weirdness. llvm-svn: 206218
* Revert "Revert r206045, "Fix shift by constants for vector.""Matt Arsenault2014-04-142-16/+34
| | | | | | Fix cases where the Value itself is used, and not the constant value. llvm-svn: 206214
* [ARM64][MC] Set the default CPU to cyclone when initilizating the MC layer.Quentin Colombet2014-04-141-0/+6
| | | | | | | | This matches that ARM64Subtarget does for now. This is related to <rdar://problem/16573920> llvm-svn: 206211
* Re-apply r206096 after investigating the gdb buildbot failure.Adrian Prantl2014-04-141-9/+14
| | | | | | | | | | | | | | | Thanks to dblaikie for updating the testcase! Debug info: (bugfix) C++ C/Dtors can be compiled to multiple functions, therefore, their declaration cannot have one DW_AT_linkage_name. The specific instances however can and should have that attribute. This patch reorders the code in DwarfUnit::getOrCreateSubprogramDIE() to emit linkage names for C/Dtors. rdar://problem/16362674. llvm-svn: 206210
* Fix for codegen bug that could cause illegal cmn instruction generationLouis Gerbarg2014-04-141-1/+16
| | | | | | | | | | | In rare cases the dead definition elimination pass code can cause illegal cmn instructions when it replaces dead registers on instructions that use unmaterialized frame indexes. This patch disables the dead definition optimization for instructions which include frame index operands. rdar://16438284 llvm-svn: 206208
* Add a flag to disable the ARM64DeadRegisterDefinitionsPassLouis Gerbarg2014-04-141-1/+10
| | | | | | | This patch adds a -arm64-dead-def-elimination flag so that it is possible to disable dead definition elimination. Includes test case. llvm-svn: 206207
* [ARM64] Port over missing subtarget features, and CPU definitions from AArch64.James Molloy2014-04-143-5/+52
| | | | llvm-svn: 206198
* [ARM64] Add big endian target arm64_be.James Molloy2014-04-141-1/+9
| | | | llvm-svn: 206197
* Replace two calls to object::symbol_iterator::increment(), which hadKaelyn Takata2014-04-141-10/+4
| | | | | | been removed in r200442. llvm-svn: 206196
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