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* [mips] Enable spilling and reloading of the dsp register set.Simon Dardis2017-10-033-0/+17
| | | | | | | | | | | The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 llvm-svn: 314798
* [CGP] Make optimizeMemoryInst capable of handling multiple AddrModesJohn Brawn2017-10-031-20/+154
| | | | | | | | | | | | | Currently optimizeMemoryInst requires that all of the AddrModes it sees are identical. This patch makes it capable of tracking multiple AddrModes, so long as they differ in at most one field. This patch does nothing by itself, but later patches will make use of it to insert or reuse phi or select instructions for the differing fields. Differential Revision: https://reviews.llvm.org/D38278 llvm-svn: 314795
* [CGP] In optimizeMemoryInst handle select similarly to phiJohn Brawn2017-10-031-7/+16
| | | | | | | | | | This lets us optimize away selects that perform the same address computation in two different ways and is also the first step towards being able to handle selects between two different, but compatible, address computations. Differential Revision: https://reviews.llvm.org/D38242 llvm-svn: 314794
* [ARM, Asm] Fix ubsan failure caused by out-of-range enum valueOliver Stannard2017-10-031-2/+2
| | | | | | | | In this code, we use ~0U as a sentinel value for any operand class that doesn't have a user-friendly error message, but this value isn't in range of the MatchClassKind enum, so we need to ensure it does not get passed to isSubclass. llvm-svn: 314793
* [X86][SSE] Add support for decoding PACKSS/PACKUS shuffles masks with UNDEFSimon Pilgrim2017-10-031-4/+12
| | | | llvm-svn: 314792
* [ARM, Asm] Remove dead code causing MSan failure.Oliver Stannard2017-10-031-7/+0
| | | | | | | r314779 caused ErrorInfo to be red uninitialised, but also made this code dead, so it can just be removed. llvm-svn: 314791
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-031-0/+53
| | | | | | | | | | If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles. Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773 Differential Revision: https://reviews.llvm.org/D38472 llvm-svn: 314788
* [InlineCost, NFC] Extract code dealing with inbounds GEPs from ↵Evgeny Astigeevich2017-10-031-29/+24
| | | | | | | | | | | | | visitGetElementPtr into a function The code responsible for analysis of inbounds GEPs is extracted into a separate function: CallAnalyzer::canFoldInboundsGEP. With the patch SROA enabling/disabling code is localized at one place instead of spreading across the code of CallAnalyzer::visitGetElementPtr. Differential Revision: https://reviews.llvm.org/D38233 llvm-svn: 314787
* [WebAssembly] MC: Support for init_array and fini_arraySam Clegg2017-10-031-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D37757 llvm-svn: 314783
* [DebugInfo] Handle endianness when moving debug info for split integer ↵Bjorn Pettersson2017-10-031-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values (reapplied) Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Original patch was reverted due to using -stop-after=isel in the test case (but that is only working when AMDGPU target is included in the llc build). The test case has now been updated to use -stop-before=expand-isel-pseudos instead. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314781
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-032-133/+289
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* Remove unused variable. NFCI.Simon Pilgrim2017-10-031-1/+0
| | | | llvm-svn: 314778
* [X86][SSE] Add support for shuffle combining from PACKSS/PACKUSSimon Pilgrim2017-10-031-0/+4
| | | | | | Mentioned in D38472 llvm-svn: 314777
* [X86][SSE] Add support for PACKSS/PACKUS constant foldingSimon Pilgrim2017-10-031-0/+85
| | | | | | Pulled out of D38472 llvm-svn: 314776
* [MiSched] - Simplify ProcResEntry accessJaved Absar2017-10-031-6/+8
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38447 llvm-svn: 314775
* ISel type legalization: add debug messages. NFCI.Sjoerd Meijer2017-10-032-168/+197
| | | | | | | | | | This adds some more debug messages to the type legalizer and functions like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make the debug messages a little bit more informative and useful. Differential Revision: https://reviews.llvm.org/D38450 llvm-svn: 314773
* [RISCV] Parse RISC-V eflags in ObjectYAMLAlex Bradbury2017-10-031-0/+8
| | | | | | | Differential Revision: https://reviews.llvm.org/D38311 Patch by Chih-Mao Chen. llvm-svn: 314770
* [trivial] fix format, NFCHiroshi Inoue2017-10-031-1/+1
| | | | llvm-svn: 314769
* [ObjectYAML] Handle SHF_COMPRESSEDShoaib Meenai2017-10-031-0/+1
| | | | | | | | | This was previously being silently dropped by obj2yaml and caused parsing errors with yaml2obj. Differential Revision: https://reviews.llvm.org/D38490 llvm-svn: 314768
* [X86] Provide the LSDA pointer with RIP relative addressing if necessaryMartin Storsjo2017-10-032-5/+7
| | | | | | | | | | | | | This makes sure the LSDA pointer isn't truncated to 32 bit. Make LowerINTRINSIC_WO_CHAIN a member function instead of a static function, so that it can use the getGlobalWrapperKind method. This solves the second half of the issues mentioned in PR34720. Differential Revision: https://reviews.llvm.org/D38343 llvm-svn: 314767
* [Lint] Avoid failed assertion by fetching the proper pointer typeMikael Holmen2017-10-032-11/+19
| | | | | | | | | | | | | | | | | | | | | Summary: When checking if a constant expression is a noop cast we fetched the IntPtrType by doing DL->getIntPtrType(V->getType())). However, there can be cases where V doesn't return a pointer, and then getIntPtrType() triggers an assertion. Now we pass DataLayout to isNoopCast so the method itself can determine what the IntPtrType is. Reviewers: arsenm Reviewed By: arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D37894 llvm-svn: 314763
* [InstCombine] Change a bunch of methods to take APInts by reference instead ↵Craig Topper2017-10-032-134/+134
| | | | | | | | of pointer. This allows us to remove a bunch of dereferences and only have a few dereferences at the call sites. llvm-svn: 314762
* [InstCombine] Replace an equality compare of two APInt pointers with a ↵Craig Topper2017-10-031-1/+1
| | | | | | | | compare of the APInts themselves. Apparently this works by virtue of the fact that the pointers are pointers to the APInts stored inside of the ConstantInt objects. But I really don't think we should be relying on that. llvm-svn: 314761
* [Legalizer] Add support for G_OR NarrowScalar.Quentin Colombet2017-10-032-0/+45
| | | | | | | | | | | | | | Legalize bitwise OR: A = BinOp<Ty> B, C into: B1, ..., BN = G_UNMERGE_VALUES B C1, ..., CN = G_UNMERGE_VALUES C A1 = BinOp<Ty/N> B1, C2 ... AN = BinOp<Ty/N> BN, CN A = G_MERGE_VALUES A1, ..., AN llvm-svn: 314760
* Rewrite a function so that it doesn't use pointers to pointers. NFC.Rui Ueyama2017-10-031-12/+13
| | | | | | | | Previous code was a bit puzzling because of its use of pointers. In this patch, we pass a vector and its offsets, instead of pointers to vector elements. llvm-svn: 314756
* LTO: Improve error reporting when adding a cache entry.Peter Collingbourne2017-10-031-4/+6
| | | | | | | | Move error handling code next to the code that returns the error, and change the error message in order to distinguish it from a similar error message elsewhere in this file. llvm-svn: 314745
* SparseSolver: Rename getOrInitValueState to getValueState, matching what ↵Daniel Berlin2017-10-031-6/+6
| | | | | | SCCP calls it llvm-svn: 314744
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-0319-442/+466
| | | | | | | | | | | | | | These are problematic because they apply to everything, and can easily clobber whatever more specific predicate you are trying to add to a function. Currently instructions use SubtargetPredicate/PredicateControl to apply this to patterns applied to an instruction definition, but not to free standing Pats. Add a wrapper around Pat so the special PredicateControls requirements can be appended to the final predicate list like how Mips does it. llvm-svn: 314742
* [InstSimplify] teach SimplifySelectInst() to fold more vector selectsHaicheng Wu2017-10-021-0/+3
| | | | | | | | | | | | Call ConstantFoldSelectInstruction() to fold cases like below select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3> All operands are constants and the condition has mixed true and false conditions. Differential Revision: https://reviews.llvm.org/D38369 llvm-svn: 314741
* [PassManager] Retire cl::opt that have been set for a while. NFCI.Davide Italiano2017-10-021-33/+21
| | | | llvm-svn: 314740
* [PowerPC] Revert r314666.Tim Shen2017-10-021-7/+2
| | | | | | | | | See https://reviews.llvm.org/D38172. I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply revert it. llvm-svn: 314739
* Template the sparse propagation solver instead of using void pointersDaniel Berlin2017-10-021-18/+31
| | | | | | | | | | | | | | Summary: This avoids using void * as the type of the lattice value and ugly casts needed to make that happen. (If folks want to use references, etc, they can use a reference_wrapper). Reviewers: davide, mssimpso Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38476 llvm-svn: 314734
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-10-023-23/+636
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues addressed since original review: - Avoid bug in regalloc greedy/machine verifier when forwarding to use in an instruction that re-defines the same virtual register. - Fixed bug when forwarding to use in EarlyClobber instruction slot. - Fixed incorrect forwarding to register definitions that showed up in explicit_uses() iterator (e.g. in INLINEASM). - Moved removal of dead instructions found by LiveIntervals::shrinkToUses() outside of loop iterating over instructions to avoid instructions being deleted while pointed to by iterator. - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 314729
* Remove trailing whitespace to trigger re-cmakingMichael Liao2017-10-021-1/+1
| | | | llvm-svn: 314728
* [X86][NFC] Add X86CmovConverterPass to the pass registry.Amjad Aboud2017-10-022-5/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D38355 llvm-svn: 314726
* Remove dead file.Michael Liao2017-10-021-1479/+0
| | | | llvm-svn: 314720
* AMDGPU: Fix typosMatt Arsenault2017-10-021-2/+2
| | | | llvm-svn: 314715
* Add support for Myriad ma2x8x series of CPUsWalter Lee2017-10-021-0/+9
| | | | | | | | | | | | Summary: Also add support for some older Myriad CPUs that were missing. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37552 llvm-svn: 314705
* Move the stripping of invalid debug info from the Verifier to AutoUpgrade.Adrian Prantl2017-10-0210-66/+54
| | | | | | | | | | | | | | | | | | | | | | | | This came out of a recent discussion on llvm-dev (https://reviews.llvm.org/D38042). Currently the Verifier will strip the debug info metadata from a module if it finds the dbeug info to be malformed. This feature is very valuable since it allows us to improve the Verifier by making it stricter without breaking bcompatibility, but arguable the Verifier pass should not be modifying the IR. This patch moves the stripping of broken debug info into AutoUpgrade (UpgradeDebugInfo to be precise), which is a much better location for this since the stripping of malformed (i.e., produced by older, buggy versions of Clang) is a (harsh) form of AutoUpgrade. This change is mostly NFC in nature, the one big difference is the behavior when LLVM module passes are introducing malformed debug info. Prior to this patch, a NoAsserts build would have printed a warning and stripped the debug info, after this patch the Verifier will report a fatal error. I believe this behavior is actually more desirable anyway. Differential Revision: https://reviews.llvm.org/D38184 llvm-svn: 314699
* [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> ↵Sanjay Patel2017-10-021-6/+6
| | | | | | icmp X, (C2<<C1) llvm-svn: 314698
* Update getMergedLocation to check the instruction type and merge properly.Dehao Chen2017-10-026-30/+54
| | | | | | | | | | | | | | Summary: If the merged instruction is call instruction, we need to set the scope to the closes common scope between 2 locations, otherwise it will cause trouble when the call is getting inlined. Reviewers: dblaikie, aprantl Reviewed By: dblaikie, aprantl Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D37877 llvm-svn: 314694
* CodeView symbol dumper: use symbolic names for registersHans Wennborg2017-10-021-4/+7
| | | | | | https://reviews.llvm.org/D38469 llvm-svn: 314690
* Eliminate ftrunc if source is know to be roundedStanislav Mekhanoshin2017-10-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D38421 llvm-svn: 314688
* [dwarfdump] Add -show-formJonas Devlieghere2017-10-021-1/+1
| | | | | | | | | This enables printing of DWARF form types after the DWARF attribute types. Differential revision: https://reviews.llvm.org/D38459 llvm-svn: 314685
* use range-for-loops; NFCISanjay Patel2017-10-021-9/+8
| | | | llvm-svn: 314676
* [AsmParser] Support GAS's .print directiveCoby Tayree2017-10-021-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D38448 llvm-svn: 314674
* remove duplicate comments, reposition related functions; NFCSanjay Patel2017-10-021-56/+49
| | | | llvm-svn: 314669
* [X86][SSE] Fix -Wsign-compare problems introduced in r314658Bjorn Pettersson2017-10-021-4/+4
| | | | | | | | | | | The refactoring in "[X86][SSE] Add createPackShuffleMask helper function. NFCI." resulted in warning when compiling the code (seen in build bots). This patch restores some types from int to unsigned to avoid those warnings. llvm-svn: 314667
* [Debug info] Handle endianness when moving debug info for split integer valuesBjorn Pettersson2017-10-021-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314666
* [X86][SSE] Add createPackShuffleMask helper function. NFCI.Simon Pilgrim2017-10-021-10/+19
| | | | llvm-svn: 314658
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