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* MIR Parser: Extract the method 'parseGlobalValue'. NFC.Alex Lorenz2015-07-281-9/+16
| | | | | | | | | This commit extracts the code that parses a global value from the method 'parseGlobalAddressOperand' into a new method 'parseGlobalValue', so that this code can be reused by the method which will parse the block address machine operands. llvm-svn: 243450
* MIR Parser: Move the function 'lexName'. NFC.Alex Lorenz2015-07-281-20/+20
| | | | | | | This commit moves the function 'lexName' to the start of the file so it can be reused by the function which will lex the named LLVM IR block references. llvm-svn: 243449
* MIR Printer: Remove an outdated TODO comment and assertion. NFC.Alex Lorenz2015-07-281-8/+0
| | | | | | | | | | | | | | | This commit removes an outdated TODO comment and a corresponding assertion which asserts that the mir printer can't the print machine basic blocks that aren't sequentially numbered. This comment and assertion were correct when I was working on the patch which serialized the machine basic blocks, but then I decided to add an 'ID' attribute to the machine basic block's YAML mapping based on the patch review. This comment and assertion then became invalid as with the 'ID' attribute we can serialize the non sequential machine basic blocks and their references without any problems. llvm-svn: 243447
* MIR Parser: Remove redundant parameters. NFC.Alex Lorenz2015-07-281-6/+6
| | | | | | | | | This commit removes the redundant parameters from the two methods 'initializeRegisterInfo' and 'initializeFrameInfo'. The removed parameters are redundant as we are already passing in the 'MachineFunction' to those methods, and those parameters can be derived from the machine function parameter. llvm-svn: 243445
* Implement target independent TLS compatible with glibc's emutls.c.Chih-Hung Hsieh2015-07-2810-29/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'common' section TLS is not implemented. Current C/C++ TLS variables are not placed in common section. DWARF debug info to get the address of TLS variables is not generated yet. clang and driver changes in http://reviews.llvm.org/D10524 Added -femulated-tls flag to select the emulated TLS model, which will be used for old targets like Android that do not support ELF TLS models. Added TargetLowering::LowerToTLSEmulatedModel as a target-independent function to convert a SDNode of TLS variable address to a function call to __emutls_get_address. Added into lib/Target/*/*ISelLowering.cpp to call LowerToTLSEmulatedModel for TLSModel::Emulated. Although all targets supporting ELF TLS models are enhanced, emulated TLS model has been tested only for Android ELF targets. Modified AsmPrinter.cpp to print the emutls_v.* and emutls_t.* variables for emulated TLS variables. Modified DwarfCompileUnit.cpp to skip some DIE for emulated TLS variabls. TODO: Add proper DIE for emulated TLS variables. Added new unit tests with emulated TLS. Differential Revision: http://reviews.llvm.org/D10522 llvm-svn: 243438
* Summary:Martell Malone2015-07-282-0/+5
| | | | | | | | | | | | | | | | Object: add IMAGE_FILE_MACHINE_ARM64 The official specifications state that the value of IMAGE_FILE_MACHINE_ARM64 is 0xAA64 (as per the Microsoft Portable Executable and Common Object Format Specification v8.3). Reviewers: rnk Subscribers: llvm-commits, compnerd, ruiu Differential Revision: http://reviews.llvm.org/D11511 llvm-svn: 243434
* [LVI] Cleanup whitespaces. NFCBruno Cardoso Lopes2015-07-281-61/+61
| | | | llvm-svn: 243430
* fix formatting; NFCSanjay Patel2015-07-281-2/+1
| | | | llvm-svn: 243424
* [AArch64] Match float round and convert to int instructions.Geoff Berry2015-07-281-12/+116
| | | | | | | | | | | | | | Summary: Add patterns for doing floating point round with various rounding modes followed by conversion to int as a single FCVT* instruction. Reviewers: t.p.northover, jmolloy Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D11424 llvm-svn: 243422
* [LAA] Add clarifying comments for the checking pointer grouping algorithm. NFCSilviu Baranga2015-07-281-1/+24
| | | | llvm-svn: 243416
* Implement __builtin_thread_pointerAdhemerval Zanella2015-07-282-0/+19
| | | | | | | This path add the aarch64 lowering of __builtin_thread_pointer. It uses the already implemented AArch64ISD::THREAD_POINTER used in TLS generation. llvm-svn: 243412
* [GMR] Teach GlobalsModRef to distinguish an important and safe case ofChandler Carruth2015-07-281-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | no-alias with non-addr-taken globals: they cannot alias a captured pointer. If the non-global underlying object would have been a capture were it to alias the global, we can firmly conclude no-alias. It isn't reasonable for a transformation to introduce a capture in a way observable by an alias analysis. Consider, even if it were to temporarily capture one globals address into another global and then restore the other global afterward, there would be no way for the load in the alias query to observe that capture event correctly. If it observes it then the temporary capturing would have changed the meaning of the program, making it an invalid transformation. Even instrumentation passes or a pass which is synthesizing stores to global variables to expose race conditions in programs could not trigger this unless it queried the alias analysis infrastructure mid-transform, in which case it seems reasonable to return results from before the transform started. See the comments in the change for a more detailed outlining of the theory here. This should address the primary performance regression found when the non-conservatively-correct path of the alias query was disabled. Differential Revision: http://reviews.llvm.org/D11410 llvm-svn: 243405
* [X86] Remove mergeSPUpdatesUp()Michael Kuperstein2015-07-281-25/+1
| | | | | | | | | | | X86FrameLowering has both a mergeSPUpdates() that accepts a direction, and an mergeSPUpdatesUp(), which seem to do the same thing, except for a slightly different interface. Removed the less general function. NFC. Differential Revision: http://reviews.llvm.org/D11510 llvm-svn: 243396
* [X86][SSE] Use bitmasks instead of shuffles where possible.Simon Pilgrim2015-07-281-0/+8
| | | | | | | | | | VPAND is a lot faster than VPSHUFB and VPBLENDVB - this patch ensures we attempt to lower to a basic bitmask before lowering to the slower byte shuffle/blend instructions. Split off from D11518. Differential Revision: http://reviews.llvm.org/D11541 llvm-svn: 243395
* AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructionsIgor Breger2015-07-283-1/+8
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11528 llvm-svn: 243390
* Changes for MachineBasicBlock to use SortedVector for LiveIns.Puyan Lotfi2015-07-281-5/+0
| | | | llvm-svn: 243389
* Move the Target way of overriding DAG Scheduler to a target hookMehdi Amini2015-07-281-8/+6
| | | | | | | | | | | | | | | Summary: The previous way of overriding it was relying on calling "setDefault" on the global registry, which implies global mutable state. Reviewers: echristo, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11538 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243388
* [GMR] Fix a long-standing bug in GlobalsModRef where it failed to clearChandler Carruth2015-07-281-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | out the per-function modref data structures when functions were deleted or when globals were deleted. I don't actually know how the global deletion side of this bug hasn't been hit before, but for the other it just-so-happens that functions aren't likely to be deleted in the particular part of the LTO pipeline where we currently enable GMR, so we got lucky. With this patch, I can self-host with GMR enabled in the normal pass pipeline! I was a bit concerned about the compile-time impact of this chang, which is part of what motivated my prior string of patches to make the per-function datastructure very dense and fast to walk. With those changes in place, I can't measure a significant compile time difference (the difference is around 0.1% which is *way* below the noise) before and after this patch when building a linked bitcode for all of Clang. Differential Revision: http://reviews.llvm.org/D11453 llvm-svn: 243385
* [LDist][LVer] Explicitly pass the set of memchecks to LoopVersioning, NFCAdam Nemet2015-07-282-8/+11
| | | | | | | | | | | | | | | | | | Before the patch, the checks were generated internally in addRuntimeCheck. Now, we use the new overloaded version of addRuntimeCheck that takes the ready-made set of checks as a parameter. The checks are now generated by the client (LoopDistribution) with the new RuntimePointerChecking::generateChecks API. Also the new printChecks API is used to print out the checks for debugging. This is to continue the transition over to the new model whereby clients will get the full set of checks from LAA, filter it and then pass it to LoopVersioning and in turn to addRuntimeCheck. llvm-svn: 243382
* Remove unnecessary const_casts. NFCCraig Topper2015-07-281-6/+4
| | | | llvm-svn: 243380
* Reserve some constant values for the Swift calling convention.Bob Wilson2015-07-282-0/+4
| | | | | | | | | | | Swift has a custom calling convention that also requires some new flags on arguments and one new attribute on alloca instructions. This patch does not include the implementation of that calling convention - that will be provided as part of the open-source release of Swift; this only reserves the bitcode constant values so that they are not used for other purposes. llvm-svn: 243379
* [libFuzzer] ensure that the dfsan tracing hooks actually run (using ↵Kostya Serebryany2015-07-282-1/+5
| | | | | | -verbosity=3 in tests) llvm-svn: 243365
* [libFuzzer] when using cmp traces, first check that the CMP is evaluated to ↵Kostya Serebryany2015-07-281-4/+44
| | | | | | one value much more frequently than to the other value (heuristic) llvm-svn: 243363
* fix invalid load folding with SSE/AVX FP logical instructions (PR22371)Sanjay Patel2015-07-283-46/+59
| | | | | | | | | | | | | | | | | | This is a follow-up to the FIXME that was added with D7474 ( http://reviews.llvm.org/rL229531 ). I thought this load folding bug had been made hard-to-hit, but it turns out to be very easy when targeting 32-bit x86 and causes a miscompile/crash in Wine: https://bugs.winehq.org/show_bug.cgi?id=38826 https://llvm.org/bugs/show_bug.cgi?id=22371#c25 The quick fix is to simply remove the scalar FP logical instructions from the load folding table in X86InstrInfo, but that causes us to miss load folds that should be possible when lowering fabs, fneg, fcopysign. So the majority of this patch is altering those lowerings to use *vector* FP logical instructions (because that's all x86 gives us anyway). That lets us do the load folding legally. Differential Revision: http://reviews.llvm.org/D11477 llvm-svn: 243361
* [opaque pointer type] Avoid using pointee types to retrieve InlineAsm's ↵David Blaikie2015-07-282-19/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | function type As a stop-gap, retrieving the InlineAsm's function type was done via the pointee type of its (pointer) Value type. Instead, pass down and store the FunctionType in the InlineAsm object. The only wrinkle with this is the ConstantUniqueMap, which then needs to ferry the FunctionType down through the InlineAsmKeyType. This could be done a bit differently if the ConstantInfo trait were broadened a bit to provide an extension point for access to the TypeClass object from the ValType objects, so that the ConstantUniqueMap<InlineAsm> would then be keyed on FunctionTypes instead of PointerTypes that point to FunctionTypes. This drops the number of IR tests that don't roundtrip through bitcode* without calling PointerType::getElementType from 416 to 8 (out of 10733). 3 of those crash when roundtripping at ToT anyway. * modulo various unavoidable uses of pointer types when validating IR (for now) and in the way globals are parsed, unfortunately. These cases will either go away (because such validation will no longer be necessary or possible when pointee types are opaque), or have to be made simultaneously with the removal of pointee types. llvm-svn: 243356
* [LAA] Split out a helper to print a collection of memchecksAdam Nemet2015-07-271-34/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is effectively an NFC but we can no longer print the index of the pointer group so instead I print its address. This still lets us cross-check the section that list the checks against the section that list the groups (see how I modified the test). E.g. before we printed this: Run-time memory checks: Check 0: Comparing group 0: %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %store_ind %arrayidxC1 = getelementptr inbounds i16, i16* %c, i64 %store_ind_inc Against group 1: %arrayidxA = getelementptr i16, i16* %a, i64 %ind %arrayidxA1 = getelementptr i16, i16* %a, i64 %add ... Grouped accesses: Group 0: (Low: %c High: (78 + %c)) Member: {%c,+,4}<%for.body> Member: {(2 + %c),+,4}<%for.body> Now we print this (changes are underlined): Run-time memory checks: Check 0: Comparing group (0x7f9c6040c320): ~~~~~~~~~~~~~~ %arrayidxC1 = getelementptr inbounds i16, i16* %c, i64 %store_ind_inc %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %store_ind Against group (0x7f9c6040c358): ~~~~~~~~~~~~~~ %arrayidxA1 = getelementptr i16, i16* %a, i64 %add %arrayidxA = getelementptr i16, i16* %a, i64 %ind ... Grouped accesses: Group 0x7f9c6040c320: ~~~~~~~~~~~~~~ (Low: %c High: (78 + %c)) Member: {(2 + %c),+,4}<%for.body> Member: {%c,+,4}<%for.body> llvm-svn: 243354
* [opaque pointers] Avoid the use of pointee types when parsing inline asm in IRDavid Blaikie2015-07-272-7/+11
| | | | | | | | | | | | | | When parsing calls to inline asm the pointee type (of the pointer type representing the value type of the InlineAsm value) was used. To avoid using it, use the ValID structure to ferry the FunctionType directly through to the InlineAsm construction. This is a bit of a workaround - alternatively the inline asm could explicitly describe the type but that'd be verbose/redundant in the IR and so long as the inline asm calls directly in the context of a call or invoke, this should suffice. llvm-svn: 243349
* [LSR] Generate and use zero extendsSanjoy Das2015-07-271-21/+139
| | | | | | | | | | | | | | | | | Summary: If a scale or a base register can be rewritten as "Zext({A,+,1})" then LSR will now consider a formula of that form in its normal cost computation. Depends on D9180 Reviewers: qcolombet, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9181 llvm-svn: 243348
* [TargetTransformInfo][NFCI] Add TargetTransformInfo::isZExtFree.Sanjoy Das2015-07-271-0/+4
| | | | | | | | | | | | | | Summary: This function is not used in this change but will be used in a subsequent change. Reviewers: mcrosier, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9180 llvm-svn: 243347
* WebAssembly: add a generic CPUJF Bastien2015-07-271-0/+3
| | | | | | | | | | Summary: WebAssemblySubtarget.cpp expects a default 'generic' CPU to exist, and this seems to be prevalent with other targets. It makes sense to have something between MVP and bleeding-edge, even though for now it's the same as MVP. This removes a warning that's currently generated. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11546 llvm-svn: 243345
* MIR Serialization: Serialize the unnamed basic block references.Alex Lorenz2015-07-276-7/+93
| | | | | | | | | | | | This commit serializes the references from the machine basic blocks to the unnamed basic blocks. This commit adds a new attribute to the machine basic block's YAML mapping called 'ir-block'. This attribute contains the actual reference to the basic block. Reviewers: Duncan P. N. Exon Smith llvm-svn: 243340
* WebAssembly: more MCAsmInfo nits.JF Bastien2015-07-271-5/+1
| | | | | | | | | | Summary: As suggested by sunfish. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11544 llvm-svn: 243339
* [llvm-mc] Add --no-warn flag with -W alias to disable outputting warnings ↵Colin LeMahieu2015-07-272-1/+3
| | | | | | while assembling. llvm-svn: 243338
* IR: Expose the method 'getLocalSlot' in the module slot tracker.Alex Lorenz2015-07-271-0/+5
| | | | | | | | | | | This commit publicly exposes the method 'getLocalSlot' in the 'ModuleSlotTracker' class. This change is useful for MIR serialization, to serialize the unnamed basic block and unnamed alloca references. Reviewers: Duncan P. N. Exon Smith llvm-svn: 243336
* - Added support for parsing HWDiv features using Target Parser.Alexandros Lamprineas2015-07-273-21/+79
| | | | | | | - Architecture extensions are represented as a bitmap. Phabricator: http://reviews.llvm.org/D11457 llvm-svn: 243335
* [llvm-mc] Pushing plumbing through for --fatal-warnings flag.Colin LeMahieu2015-07-279-10/+10
| | | | llvm-svn: 243334
* [IndVars] Make loop varying predicates loop invariant.Sanjoy Das2015-07-272-5/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Was D9784: "Remove loop variant range check when induction variable is strictly increasing" This change re-implements D9784 with the two differences: 1. It does not use SCEVExpander and does not generate new instructions. Instead, it does a quick local search for existing `llvm::Value`s that it needs when modifying the `icmp` instruction. 2. It is more general -- it deals with both increasing and decreasing induction variables. I've added all of the tests included with D9784, and two more. As an example on what this change does (copied from D9784): Given C code: ``` for (int i = M; i < N; i++) // i is known not to overflow if (i < 0) break; a[i] = 0; } ``` This transformation produces: ``` for (int i = M; i < N; i++) if (M < 0) break; a[i] = 0; } ``` Which can be unswitched into: ``` if (!(M < 0)) for (int i = M; i < N; i++) a[i] = 0; } ``` I went back and forth on whether the top level logic should live in `SimplifyIndvar::eliminateIVComparison` or be put into its own routine. Right now I've put it under `eliminateIVComparison` because even though the `icmp` is not *eliminated*, it no longer is an IV comparison. I'm open to putting it in its own helper routine if you think that is better. Reviewers: reames, nicholas, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11278 llvm-svn: 243331
* remove unnecessary forward declaration; NFCSanjay Patel2015-07-271-16/+12
| | | | llvm-svn: 243328
* don't repeat function names in comments; NFCSanjay Patel2015-07-271-61/+49
| | | | llvm-svn: 243327
* WebAssembly: minor MCAsmInfo fixesJF Bastien2015-07-271-1/+8
| | | | | | | | | | | | Summary: Fix pointer / callee-save stack sto size. Update comment character to be LISP-ish. Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11537 llvm-svn: 243326
* MIR Serialization: Serialize the '.cfi_def_cfa_register' CFI instruction.Alex Lorenz2015-07-274-0/+15
| | | | llvm-svn: 243322
* MIR Parser: Rename the standalone parsing methods. NFC.Alex Lorenz2015-07-271-6/+7
| | | | | | | | This commit renames the methods 'parseMBB' and 'parseNamedRegister' to 'parseStandaloneMBB' and 'parseStandaloneNamedRegister' in order for their names to be consistent with the method 'parseStandaloneVirtualRegister'. llvm-svn: 243319
* Revert "[PeepholeOptimizer] Look through PHIs to find additional register ↵Bruno Cardoso Lopes2015-07-272-277/+83
| | | | | | | | sources" Still breaks some ARM buildbots. This reverts r243271. llvm-svn: 243318
* [LAA] Upper-case variable names, NFCAdam Nemet2015-07-271-4/+4
| | | | llvm-svn: 243313
* [LAA] Split out a helper from addRuntimeCheck to generate the check, NFCAdam Nemet2015-07-271-14/+18
| | | | llvm-svn: 243312
* [AArch64] Remove check for Darwin that was needed to decide if x18 shouldAkira Hatanaka2015-07-271-9/+7
| | | | | | | | | be reserved. The decision to reserve x18 is going to be made solely by the front-end, so it isn't necessary to check if the OS is Darwin in the backend. llvm-svn: 243308
* Fixed signed/unsigned comparison warning.Simon Pilgrim2015-07-271-1/+1
| | | | llvm-svn: 243306
* [InstCombine][X86][SSE] Replace sign/zero extension intrinsics with native IRSimon Pilgrim2015-07-271-14/+45
| | | | | | | | Now that we are generating sane codegen for vector sext/zext nodes on SSE targets, this patch uses instcombine to replace the SSE41/AVX2 pmovsx and pmovzx intrinsics with the equivalent native IR code. Differential Revision: http://reviews.llvm.org/D11503 llvm-svn: 243303
* Revert "Remove unnecessary null check. NFC."Pete Cooper2015-07-271-0/+3
| | | | | | | | | | | This reverts commit r243167. Duncan pointed out that dyn_cast can return null in these cases, so this was an unsafe commit to make. Sorry for the noise. Worryingly there were no tests which fail... llvm-svn: 243302
* Fix assert when inlining a constantexpr addrspacecastMatt Arsenault2015-07-271-2/+1
| | | | | | | | | | | | The pointer size of the addrspacecasted pointer might not have matched, so this would have hit an assert in accumulateConstantOffset. I think this was here to allow constant folding of a load of an addrspacecasted constant. Accumulating the offset through the addrspacecast doesn't make much sense, so something else is necessary to allow folding the load through this cast. llvm-svn: 243300
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