| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | - Added MCSubtargetInfo to capture subtarget features and scheduling | Evan Cheng | 2011-07-01 | 28 | -28/+201 |
| | | | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257 | ||||
| * | Fix off-by-one error. | Jim Grosbach | 2011-07-01 | 1 | -1/+1 |
| | | | | | | | (low two bits always zero, so off by one bit of encoded value). llvm-svn: 134247 | ||||
| * | Hide the call to InitMCInstrInfo into tblgen generated ctor. | Evan Cheng | 2011-07-01 | 27 | -51/+85 |
| | | | | | llvm-svn: 134244 | ||||
| * | Pseudo-ize t2MOVCC[ri]. | Jim Grosbach | 2011-07-01 | 4 | -55/+18 |
| | | | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. llvm-svn: 134242 | ||||
| * | Eliminate one extra conversion. | Evan Cheng | 2011-07-01 | 1 | -1/+1 |
| | | | | | llvm-svn: 134240 | ||||
| * | Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵ | Duncan Sands | 2011-07-01 | 1 | -0/+1 |
| | | | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. llvm-svn: 134237 | ||||
| * | Another misuse of StringRef. MSVC is very sensitive to that kind of error. | Francois Pichet | 2011-07-01 | 1 | -2/+2 |
| | | | | | llvm-svn: 134236 | ||||
| * | Fix likely typo, reduce number of instruction name collisions. | Nick Lewycky | 2011-07-01 | 1 | -1/+1 |
| | | | | | llvm-svn: 134235 | ||||
| * | Fix use after free. | Rafael Espindola | 2011-07-01 | 1 | -1/+1 |
| | | | | | llvm-svn: 134234 | ||||
| * | Avoid DenseMap lookup. | Rafael Espindola | 2011-07-01 | 1 | -6/+8 |
| | | | | | llvm-svn: 134231 | ||||
| * | Fix off by one error. I misunderstood the comment about killedAt. | Rafael Espindola | 2011-07-01 | 1 | -1/+1 |
| | | | | | llvm-svn: 134229 | ||||
| * | Check the liveinterval, not the kill flag. | Rafael Espindola | 2011-07-01 | 1 | -7/+10 |
| | | | | | llvm-svn: 134228 | ||||
| * | Don't inflate register classes used by inline asm. | Jakob Stoklund Olesen | 2011-07-01 | 1 | -0/+3 |
| | | | | | | | | | | | | | The constraints are represented by the register class of the original virtual register created for the inline asm. If the register class were included in the operand descriptor, we might be able to do this. For now, just give up on regclass inflation when inline asm is involved. No test case, this bug hasn't happened yet. llvm-svn: 134226 | ||||
| * | Improve Mips back-end's handling of DBG_VALUE. | Akira Hatanaka | 2011-07-01 | 5 | -23/+70 |
| | | | | | llvm-svn: 134224 | ||||
| * | Improve constant folding of undef for cmp and select operators. | Dan Gohman | 2011-07-01 | 2 | -6/+11 |
| | | | | | llvm-svn: 134223 | ||||
| * | Add support for the 'j' immediate constraint. This is conditionalized on | Eric Christopher | 2011-07-01 | 1 | -0/+9 |
| | | | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 llvm-svn: 134222 | ||||
| * | Improve constant folding of undef for binary operators. | Dan Gohman | 2011-07-01 | 1 | -4/+24 |
| | | | | | llvm-svn: 134221 | ||||
| * | Add support for the ARM 't' register constraint. And another testcase | Eric Christopher | 2011-07-01 | 1 | -0/+5 |
| | | | | | | | | | for the 'x' register constraint. Part of rdar://9119939 llvm-svn: 134220 | ||||
| * | Switch SubtargetFeatures from std::string to StringRef. | Evan Cheng | 2011-07-01 | 1 | -22/+19 |
| | | | | | llvm-svn: 134219 | ||||
| * | We'll return a null RC by default if we can't match. | Eric Christopher | 2011-07-01 | 1 | -2/+1 |
| | | | | | | | Part of rdar://9119939 llvm-svn: 134217 | ||||
| * | Add 134199 back, but disable the optimization when the second copy is a kill. | Rafael Espindola | 2011-07-01 | 1 | -10/+100 |
| | | | | | llvm-svn: 134216 | ||||
| * | Add support for the 'x' constraint. | Eric Christopher | 2011-07-01 | 1 | -0/+9 |
| | | | | | | | Part of rdar://9307836 and rdar://9119939 llvm-svn: 134215 | ||||
| * | Remove tabs. | Bill Wendling | 2011-06-30 | 1 | -6/+6 |
| | | | | | llvm-svn: 134212 | ||||
| * | Capitalize the unsigned part of the initializer. | Eric Christopher | 2011-06-30 | 1 | -1/+1 |
| | | | | | llvm-svn: 134211 | ||||
| * | Rename Pair to RCPair lacking any better naming ideas. | Eric Christopher | 2011-06-30 | 1 | -10/+10 |
| | | | | | llvm-svn: 134210 | ||||
| * | Improve comment: Show the register the DWARF label is added to. | Bill Wendling | 2011-06-30 | 1 | -1/+2 |
| | | | | | llvm-svn: 134209 | ||||
| * | Use the correct registers on X86_64. | Bill Wendling | 2011-06-30 | 1 | -4/+4 |
| | | | | | llvm-svn: 134208 | ||||
| * | Fix a problem with fast-isel return values introduced in r134018. | Jakob Stoklund Olesen | 2011-06-30 | 1 | -2/+3 |
| | | | | | | | | | | We would put the return value from long double functions in the wrong register. This fixes gcc.c-torture/execute/conversion.c llvm-svn: 134205 | ||||
| * | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach | 2011-06-30 | 9 | -86/+26 |
| | | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204 | ||||
| * | Add support for the 'h' constraint. | Eric Christopher | 2011-06-30 | 2 | -1/+10 |
| | | | | | | | Part of rdar://9119939 llvm-svn: 134203 | ||||
| * | Add target a target hook to get the register number used by the compact unwind | Bill Wendling | 2011-06-30 | 2 | -0/+19 |
| | | | | | | | | encoding for the registers it knows about. Return -1 if it can't handle that register. llvm-svn: 134202 | ||||
| * | Revert my previous patch while I debug llvm-gcc bootstrap. | Rafael Espindola | 2011-06-30 | 1 | -95/+10 |
| | | | | | llvm-svn: 134201 | ||||
| * | Add one more comment to the FDE verbose asm output. | Bill Wendling | 2011-06-30 | 1 | -0/+1 |
| | | | | | llvm-svn: 134200 | ||||
| * | Don't give up on coalescing A and B when we find | Rafael Espindola | 2011-06-30 | 1 | -10/+95 |
| | | | | | | | | | | | | | A = X B = X Instead, proceed as if we had found A = X B = A llvm-svn: 134199 | ||||
| * | Add a convenience typedef for std::pair<unsigned, const TargetRegisterClass*>. | Eric Christopher | 2011-06-30 | 1 | -7/+8 |
| | | | | | | | | | No functional change. Part of rdar://9119939 llvm-svn: 134198 | ||||
| * | Thumb1 register to register MOV instruction is predicable. | Jim Grosbach | 2011-06-30 | 8 | -51/+60 |
| | | | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197 | ||||
| * | Add comments to the FDE. | Bill Wendling | 2011-06-30 | 1 | -5/+13 |
| | | | | | llvm-svn: 134196 | ||||
| * | Add more comments to the ASM output for the CIE's "moves". | Bill Wendling | 2011-06-30 | 1 | -1/+20 |
| | | | | | llvm-svn: 134194 | ||||
| * | Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c | Jakob Stoklund Olesen | 2011-06-30 | 1 | -3/+3 |
| | | | | | llvm-svn: 134193 | ||||
| * | Add comments to the ASM output to help understand the compact unwind and CIE ↵ | Bill Wendling | 2011-06-30 | 1 | -6/+61 |
| | | | | | | | tables. llvm-svn: 134191 | ||||
| * | Create a isFullCopy predicate. | Rafael Espindola | 2011-06-30 | 1 | -5/+1 |
| | | | | | llvm-svn: 134189 | ||||
| * | Add r134057 back, but splice the predecessor after the successors phi | Rafael Espindola | 2011-06-30 | 3 | -11/+33 |
| | | | | | | | | | | nodes. Original message: Let simplify cfg simplify bb with only debug and lifetime intrinsics. llvm-svn: 134182 | ||||
| * | Pseudo-ize the Thumb tTPsoft instruction. | Jim Grosbach | 2011-06-30 | 3 | -24/+7 |
| | | | | | | | | It's just a call to a special helper function. Get rid of the T2 variant entirely, as it's identical to the Thumb1 version. llvm-svn: 134178 | ||||
| * | indvars -disable-iv-rewrite: handle cloning binary operators that cannot ↵ | Andrew Trick | 2011-06-30 | 1 | -3/+7 |
| | | | | | | | overflow. llvm-svn: 134177 | ||||
| * | Pseudo-ize the t2LDMIA_RET instruction. | Jim Grosbach | 2011-06-30 | 2 | -19/+12 |
| | | | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173 | ||||
| * | Pseudo-ize the Thumb tPOP_RET instruction. | Jim Grosbach | 2011-06-30 | 2 | -9/+10 |
| | | | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172 | ||||
| * | Remove dead code. | Rafael Espindola | 2011-06-30 | 1 | -88/+0 |
| | | | | | llvm-svn: 134148 | ||||
| * | Kill dead code. | Jim Grosbach | 2011-06-30 | 1 | -1/+0 |
| | | | | | llvm-svn: 134131 | ||||
| * | Size reducing SP adjusting t2ADDri needs to check predication. | Jim Grosbach | 2011-06-30 | 1 | -1/+4 |
| | | | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." llvm-svn: 134130 | ||||
| * | Fix ARMSubtarget feature parsing. | Evan Cheng | 2011-06-30 | 1 | -10/+7 |
| | | | | | llvm-svn: 134129 | ||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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