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* [MC][PredicateExpander] Extend the grammar to support simple switch and ↵Andrea Di Biagio2018-08-091-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | return statements. This patch introduces tablegen class MCStatement. Currently, an MCStatement can be either a return statement, or a switch statement. ``` MCStatement: MCReturnStatement MCOpcodeSwitchStatement ``` A MCReturnStatement expands to a return statement, and the boolean expression associated with the return statement is described by a MCInstPredicate. An MCOpcodeSwitchStatement is a switch statement where the condition is a check on the machine opcode. It allows the definition of multiple checks, as well as a default case. More details on the grammar implemented by these two new constructs can be found in the diff for TargetInstrPredicates.td. This patch makes it easier to read the body of auto-generated TargetInstrInfo predicates. In future, I plan to reuse/extend the MCStatement grammar to describe more complex target hooks. For now, this is just a first step (mostly a minor cosmetic change to polish the new predicates framework). Differential Revision: https://reviews.llvm.org/D50457 llvm-svn: 339352
* [MC] Remove PhysRegSize from MCRegisterClassBjorn Pettersson2018-08-091-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The interface to get size and spill size of a register was moved from MCRegisterInfo to TargetRegisterInfo over a year ago. Afaik the old interface has bee around to give out-of-tree targets a chance to adapt to the new interface. One problem with the old MCRegisterClass::PhysRegSize was that it represented the size of a register as "size in bits" / 8. So a register had to be a multiple of eight bits wide for the size to be correct (and the byte size for the target needed to be eight bits). Reviewers: kparzysz, qcolombet Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47199 llvm-svn: 339350
* [InstCombine] reduce code duplication; NFCSanjay Patel2018-08-091-9/+7
| | | | llvm-svn: 339349
* [TargetLowering] Add BuildSDIVPattern helper to BuildExactSDIV (NFCI).Simon Pilgrim2018-08-091-14/+23
| | | | | | As requested in D50392, pull the magic constant calculations out into a helper function. llvm-svn: 339346
* [ARM] FP16: codegen support for VTRNSjoerd Meijer2018-08-091-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D50454 llvm-svn: 339340
* [X86][SSE] Remove PMULDQ/PMULUDQ by zeroSimon Pilgrim2018-08-091-0/+9
| | | | | | | | Exposed by D50328 Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339337
* [X86][SSE] Combine (some) target shuffles with multiple usesSimon Pilgrim2018-08-091-20/+29
| | | | | | | | | | | | | | As discussed on D41794, we have many cases where we fail to combine shuffles as the input operands have other uses. This patch permits these shuffles to be combined as long as they don't introduce additional variable shuffle masks, which should reduce instruction dependencies and allow the total number of shuffles to still drop without increasing the constant pool. However, this may mean that some memory folds may no longer occur, and on pre-AVX require the occasional extra register move. This also exposes some poor PMULDQ/PMULUDQ codegen which was doing unnecessary upper/lower calculations which will in fact fold to zero/undef - the fix will be added in a followup commit. Differential Revision: https://reviews.llvm.org/D50328 llvm-svn: 339335
* [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.Andrew V. Tischenko2018-08-0911-57/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D49861 llvm-svn: 339321
* [NVPTX] Select atomic loads and storesJonas Hahnfeld2018-08-091-34/+82
| | | | | | | | | | | | | | | | | | | According to PTX ISA .volatile has the same memory synchronization semantics as .relaxed.sys, so it can be used to implement monotonic atomic loads and stores. This is important for OpenMP's atomic construct where - 'read's and 'write's are lowered to atomic loads and stores, and - an update of float or double types are lowered into a cmpxchg loop. (Note that PTX could do better because it has atom.add.f{32,64} but LLVM's atomicrmw instruction only allows integer types.) Higher levels of atomicity (like acquire and release) need additional synchronization properties which were added with PTX ISA 6.0 / sm_70. So using these instructions still results in an error. Differential Revision: https://reviews.llvm.org/D50391 llvm-svn: 339316
* [RISCV] Add "lla" pseudo-instruction to assemblerRoger Ferrer Ibanez2018-08-092-3/+69
| | | | | | | | | | | | | | | | | | | | | | | | This pseudo-instruction is similar to la but uses PC-relative addressing unconditionally. This is, la is only different to lla when using -fPIC. This pseudo-instruction seems often forgotten in several specs but it is definitely mentioned in binutils opcodes/riscv-opc.c. The semantics are defined both in page 37 of the "RISC-V Reader" book but also in function macro found in gas/config/tc-riscv.c. This is a very first step towards adding PIC support for Linux in the RISC-V backend. The lla pseudo-instruction expands to a sequence of auipc + addi with a couple of pc-rel relocations where the second points to the first one. This is described in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#pc-relative-symbol-addresses For now, this patch only introduces support of that pseudo instruction at the assembler parser. Differential Revision: https://reviews.llvm.org/D49661 llvm-svn: 339314
* [NFC] ConstantMerge: don't insert when find should be usedJF Bastien2018-08-091-2/+5
| | | | | | | | | | Summary: DenseMap's operator[] performs an insertion if the entry isn't found. The second phase of ConstantMerge isn't trying to insert anything: it's just looking to see if the first phased performed an insertion. Use find instead, avoiding insertion of every single global initializer in the map of constants. This has the side-effect of making all entries in CMap non-null (because only global declarations would have null initializers, and that would be a bug). Subscribers: dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D50476 llvm-svn: 339309
* [LICM] Add an assert to ensure all instruction types needing aliasing are ↵Philip Reames2018-08-091-0/+2
| | | | | | handled [NFC] llvm-svn: 339308
* [DWARF] Verifier now handles .debug_types sections.Paul Robinson2018-08-081-23/+35
| | | | | | Differential Revision: https://reviews.llvm.org/D50466 llvm-svn: 339302
* [DAGCombiner] loosen constraints for fsub+fadd foldSanjay Patel2018-08-081-14/+7
| | | | | | | | | isNegatibleForFree() should not matter here (as the test diffs show) because it's always a win to replace an fsub+fadd with fneg. The problem in D50195 persists because either (1) we are doing these folds in the wrong order or (2) we're missing another fold for fadd. llvm-svn: 339299
* [DAGCombiner] move fadd simplification ahead of other foldsSanjay Patel2018-08-081-9/+6
| | | | | | | | | I don't know if it's possible to expose this diff in a test, but we should always try simplifications (no new nodes created) before more complicated transforms for efficiency (similar to what we do in IR). llvm-svn: 339298
* [ADT] Normalize empty triple componentsPetr Hosek2018-08-081-0/+6
| | | | | | | | | | | | | | | | | LLVM triple normalization is handling "unknown" and empty components differently; for example given "x86_64-unknown-linux-gnu" and "x86_64-linux-gnu" which should be equivalent, triple normalization returns "x86_64-unknown-linux-gnu" and "x86_64--linux-gnu". autoconf's config.sub returns "x86_64-unknown-linux-gnu" for both "x86_64-linux-gnu" and "x86_64-unknown-linux-gnu". This changes the triple normalization to behave the same way, replacing empty triple components with "unknown". This addresses PR37129. Differential Revision: https://reviews.llvm.org/D50219 llvm-svn: 339294
* [DWARF] Unclamp line table version on Darwin for v5 and later.Jonas Devlieghere2018-08-081-3/+6
| | | | | | | | | On Darwin we pin the DWARF line tables to version 2. Stop doing so for DWARF v5 and later. Differential revision: https://reviews.llvm.org/D49381 llvm-svn: 339288
* [ARM] Avoid spilling lr with Thumb1 tail calls.Eli Friedman2018-08-081-2/+7
| | | | | | | | | | | | | | | Normally, if any registers are spilled, we prefer to spill lr on Thumb1 so we can fold the "bx lr" into the "pop". However, if there are tail calls involved, restoring lr is expensive, so skip the optimization in that case. The spill of r7 in the new test also isn't necessary, but that's mostly orthogonal to this patch. (It's the same code in ARMFrameLowering, but it's not related to tail calls.) Differential Revision: https://reviews.llvm.org/D49459 llvm-svn: 339283
* [MS Demangler] Create a new backref context for template instantiations.Zachary Turner2018-08-081-29/+39
| | | | | | | | Template manglings use a fresh back-referencing context, so we need to do the same. This fixes several existing tests which are marked as FIXME, so those are now actually run. llvm-svn: 339275
* revert '[CodeGen] emit inline asm clobber list warnings for reserved'Ties Stuij2018-08-081-78/+32
| | | | llvm-svn: 339274
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-083-92/+210
| | | | | | Differential Revision: https://reviews.llvm.org/D50405 llvm-svn: 339272
* AMDGPU: Error more gracefully on libcallsMatt Arsenault2018-08-081-0/+3
| | | | | | | I think this is the only situation where the callsite will have a null instruction. llvm-svn: 339271
* AMDGPU: Fix shifts for i128Matt Arsenault2018-08-081-0/+4
| | | | llvm-svn: 339270
* [WASM] Fix overflow when reading custom sectionJonas Devlieghere2018-08-081-3/+10
| | | | | | | | | | | | | When reading a custom WASM section, it was possible that its name extended beyond the size of the section. This resulted in a bogus value for the section size due to the size overflowing. Fixes heap buffer overflow detected by OSS-fuzz: https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=8190 Differential revision: https://reviews.llvm.org/D50387 llvm-svn: 339269
* [DebugInfo] Fine tune emitting flags as part of the producerJonas Devlieghere2018-08-081-1/+1
| | | | | | | | | When using APPLE extensions, don't duplicate the compiler invocation's flags both in AT_producer and AT_APPLE_flags. Differential revision: https://reviews.llvm.org/D50453 llvm-svn: 339268
* [InstCombine] fold fadd+fsub with common operandSanjay Patel2018-08-081-0/+5
| | | | | | | This is a sibling to the simplify from: https://reviews.llvm.org/rL339174 llvm-svn: 339267
* [InstCombine] fold fsub+fsub with common operandSanjay Patel2018-08-081-0/+8
| | | | | | | This is a sibling to the simplify from: rL339171 llvm-svn: 339266
* [DAG] DAGCombiner::visitSDIVLike - remove unnecessary isConstOrConstSplat ↵Simon Pilgrim2018-08-081-4/+1
| | | | | | | | call. NFCI. The isConstOrConstSplat result is only used in a ISD::matchUnaryPredicate call which can perform the equivalent iteration just as quickly. llvm-svn: 339262
* [PowerPC] Improve codegen for vector loads using scalar_to_vectorZaara Syeda2018-08-083-20/+83
| | | | | | | | | | | | | | | | This patch aims to improve the codegen for vector loads involving the scalar_to_vector (load X) sequence. Initially, ld->mv instructions were used for scalar_to_vector (load X), so this patch allows scalar_to_vector (load X) to utilize: LXSD and LXSDX for i64 and f64 LXSIWAX for i32 (sign extension to i64) LXSIWZX for i32 and f64 Committing on behalf of Amy Kwan. Differential Revision: https://reviews.llvm.org/D48950 llvm-svn: 339260
* [CodeGen] emit inline asm clobber list warnings for reservedTies Stuij2018-08-081-32/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, in line with GCC, when specifying reserved registers like sp or pc on an inline asm() clobber list, we don't always preserve the original value across the statement. And in general, overwriting reserved registers can have surprising results. For example: ``` extern int bar(int[]); int foo(int i) { int a[i]; // VLA asm volatile( "mov r7, #1" : : : "r7" ); return 1 + bar(a); } ``` Compiled for thumb, this gives: ``` $ clang --target=arm-arm-none-eabi -march=armv7a -c test.c -o - -S -O1 -mthumb ... foo: .fnstart @ %bb.0: @ %entry .save {r4, r5, r6, r7, lr} push {r4, r5, r6, r7, lr} .setfp r7, sp, #12 add r7, sp, #12 .pad #4 sub sp, #4 movs r1, #7 add.w r0, r1, r0, lsl #2 bic r0, r0, #7 sub.w r0, sp, r0 mov sp, r0 @APP mov.w r7, #1 @NO_APP bl bar adds r0, #1 sub.w r4, r7, #12 mov sp, r4 pop {r4, r5, r6, r7, pc} ... ``` r7 is used as the frame pointer for thumb targets, and this function needs to restore the SP from the FP because of the variable-length stack allocation a. r7 is clobbered by the inline assembly (and r7 is included in the clobber list), but LLVM does not preserve the value of the frame pointer across the assembly block. This type of behavior is similar to GCC's and has been discussed on the bugtracker: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11807 . No consensus seemed to have been reached on the way forward. Clang behavior has briefly been discussed on the CFE mailing (starting here: http://lists.llvm.org/pipermail/cfe-dev/2018-July/058392.html). I've opted for following Eli Friedman's advice to print warnings when there are reserved registers on the clobber list so as not to diverge from GCC behavior for now. The patch uses MachineRegisterInfo's target-specific knowledge of reserved registers, just before we convert the inline asm string in the AsmPrinter. If we find a reserved register, we print a warning: ``` repro.c:6:7: warning: inline asm clobber list contains reserved registers: R7 [-Winline-asm] "mov r7, #1" ^ ``` Reviewers: eli.friedman, olista01, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, eraman, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D49727 llvm-svn: 339257
* [RISCV] Add mnemonic alias: move, sbreak and scall.Alex Bradbury2018-08-081-0/+8
| | | | | | | | | Further improve compatibility with the GNU assembler. Differential Revision: https://reviews.llvm.org/D50217 Patch by Kito Cheng. llvm-svn: 339255
* [TargetLowering] BuildUDIV - Add support for divide by one (PR38477)Simon Pilgrim2018-08-081-7/+8
| | | | | | | | Provide a pass-through of the numerator for divide by one cases - this is the same approach we take in DAGCombiner::visitSDIVLike. I investigated whether we could achieve this by magic MULHU/SRL values but nothing appeared to work as we don't have a way for MULHU(x,c) -> x llvm-svn: 339254
* [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], ↵Alex Bradbury2018-08-081-0/+31
| | | | | | | | | | | | sra[w], slt and sltu with immediate Match the GNU assembler in supporting immediate operands for these instructions even when the reg-reg mnemonic is used. Differential Revision: https://reviews.llvm.org/D50046 Patch by Kito Cheng. llvm-svn: 339252
* [InstCombine] fold fneg into constant operand of fmul/fdivSanjay Patel2018-08-081-2/+15
| | | | | | | | | | | | This accounts for the missing IR fold noted in D50195. We don't need any fast-math to enable the negation transform. FP negation can always be folded into an fmul/fdiv constant to eliminate the fneg. I've limited this to one-use to ensure that we are eliminating an instruction rather than replacing fneg by a potentially expensive fdiv or fmul. Differential Revision: https://reviews.llvm.org/D50417 llvm-svn: 339248
* [TargetLowering] Remove APInt divisor argument from BuildExactSDIV (NFCI).Simon Pilgrim2018-08-081-14/+22
| | | | | | | | As requested in D50392, this is a minor refactor to BuildExactSDIV to stop taking the uniform constant APInt divisor and instead extract it locally. I also cleanup the operands and valuetypes to better match BuildUDiv (and BuildSDIV in the near future). llvm-svn: 339246
* test commit accessTies Stuij2018-08-081-4/+4
| | | | | | | | | | Summary: changing a few typos Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D50445 llvm-svn: 339245
* [InstCombine] De Morgan: sink 'not' into 'xor' (PR38446)Roman Lebedev2018-08-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | Summary: https://rise4fun.com/Alive/IT3 Comes up in the [most ugliest] `signed int` -> `signed char` case of `-fsanitize=implicit-conversion` (https://reviews.llvm.org/D50250) Previously, we were stuck with `not`: {F6867736} But now we are able to completely get rid of it: {F6867737} (FIXME: why are we loosing the metadata? that seems wrong/strange.) Here, we only want to do that it we will be able to completely get rid of that 'not'. Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: vsk, erichkeane, llvm-commits Differential Revision: https://reviews.llvm.org/D50301 llvm-svn: 339243
* [ARM] FP16: codegen support for VEXTSjoerd Meijer2018-08-081-6/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D50427 llvm-svn: 339241
* [ARM] FP16: vector vmov and vdup supportSjoerd Meijer2018-08-081-0/+13
| | | | | | | | This adds codegen support for the vmov_n_f16 and vdup_n_f16 variants. Differential Revision: https://reviews.llvm.org/D50329 llvm-svn: 339238
* [ARM] FP16: vector VMUL variantsSjoerd Meijer2018-08-081-2/+14
| | | | | | | | This adds codegen support for the vmul_lane_f16 and vmul_n_f16 variants. Differential Revision: https://reviews.llvm.org/D50326 llvm-svn: 339232
* [Wasm] Don't iterate over MachineBasicBlock::successors while erasing from itBenjamin Kramer2018-08-081-8/+10
| | | | | | This will read out of bounds. Found by asan. llvm-svn: 339230
* [TargetLowering] BuildUDIV - Early out for divide by one (PR38477)Simon Pilgrim2018-08-081-0/+4
| | | | | | We're not handling the UDIV by one special case properly - for now just early out. llvm-svn: 339229
* [ARM] FP16: support vector INT_TO_FP and FP_TO_INTSjoerd Meijer2018-08-081-7/+35
| | | | | | | | This adds codegen support for the different vcvt_f16 variants. Differential Revision: https://reviews.llvm.org/D50393 llvm-svn: 339227
* Support inline asm with multiple 64bit output in 32bit GPRThomas Preud'homme2018-08-081-16/+37
| | | | | | | | | | | | | | Summary: Extend fix for PR34170 to support inline assembly with multiple output operands that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR as in the PR). Reviewers: bogner, t.p.northover, lattner, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, tra, eraman, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45437 llvm-svn: 339225
* [ARM] FP16: support the vector vmin and vmax variantsSjoerd Meijer2018-08-081-0/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D50238 llvm-svn: 339221
* [MS Demangler] Properly handle backreferencing of special names.Zachary Turner2018-08-081-20/+36
| | | | | | | | | | | | | | | | | | | | | Function template names are not stored in the backref table, but non-template function names are. The general pattern seems to be that when you are demangling a symbol name, if the name starts with '?' it does not go into the backreference table, otherwise it does. Note that this even handles the general case of operator names (template or otherwise) not going into the back-reference table, anonymous namespaces not going into the backreference table, etc. It's important that we apply this check *only* for the unqualified portion of a name, and only for symbol names. For example, this does not apply to type names (such as class templates) and we need to make sure that these still do go into the backref table. Differential Revision: https://reviews.llvm.org/D50394 llvm-svn: 339211
* [Coverage] Ignore 'unused' functions with non-zero execution countsVedant Kumar2018-08-071-6/+15
| | | | | | | | | | | | | | | | | Frontends emit 'unused' coverage mapping records for functions which are provably unused in a TU. These unused records contain a single counter with CounterKind::Zero. However, a function may be unused in one TU and used in another. When this happens, prefer the records with a full set of counters instead of arbitrarily picking the first loaded record. There is no impact on the single-TU case. In the multiple-TU case, this resolves issues causing a function to appear unused when it's not. Testing: check-{llvm,clang,compiler-rt} rdar://42981322 llvm-svn: 339194
* [Coverage] Delete getCounterMismatches, it's dead code (NFC)Vedant Kumar2018-08-071-5/+0
| | | | | | | Exactly one counted region is inserted into a function record for every region in a coverage mapping. llvm-svn: 339193
* Refactor FileCheck to make it usable as an APIAditya Nandakumar2018-08-072-0/+1341
| | | | | | | | | | https://reviews.llvm.org/D50283 reviewed by bogner This patch refactors FileCheck's implementation into support so it can be used from C++ in other places (Unit tests). llvm-svn: 339192
* AMDGPU: Remove broken i16 ternary patternsJan Vesely2018-08-071-11/+0
| | | | | | | | | | | | | | | Fixup test to check for GCN prefix These patterns always zero extend the result even though it might need sign extension. This has been broken since the addition of i16 support. It has popped up in mad_sat(char) test since min(max()) combination is turned into v_med3, resulting in the following (incorrect) sequence: v_mad_i16 v2, v10, v9, v11 v_med3_i32 v2, v2, v8, v7 Fixes mad_sat(char) piglit on VI. Differential Revision: https://reviews.llvm.org/D49836 llvm-svn: 339190
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