summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* MIPS DSP: Add immediate leaves.Akira Hatanaka2012-09-221-0/+20
| | | | llvm-svn: 164435
* MIPS DSP: Add predicates and instruction template.Akira Hatanaka2012-09-221-0/+25
| | | | llvm-svn: 164434
* Add MIPS DSP register classes. Set actions of DSP vector operations and overrideAkira Hatanaka2012-09-212-0/+49
| | | | | | TargetLowering's callback functions. llvm-svn: 164431
* SelectionDAG node enums for MIPS DSP nodes.Akira Hatanaka2012-09-212-0/+55
| | | | llvm-svn: 164430
* Add MIPS accumulator and DSP control registers.Akira Hatanaka2012-09-212-1/+45
| | | | llvm-svn: 164429
* Add flags and feature bits for mips dsp.Akira Hatanaka2012-09-212-0/+9
| | | | llvm-svn: 164428
* Fix a case where the new SROA pass failed to zap dead operands toChandler Carruth2012-09-211-0/+4
| | | | | | | | | | | selects with a constant condition. This resulted in the operands remaining live through the SROA rewriter. Most of the time, this just caused some dead allocas to persist and get zapped by later passes, but in one case found by Joerg, it caused a crash when we tried to *promote* the alloca despite it having this dead use. We already have the mechanisms in place to handle this, just wire select up to them. llvm-svn: 164427
* Add an --enable-backtraces option to configure to determineEric Christopher2012-09-211-1/+1
| | | | | | | | | whether or not we want to print out backtrace information. Useful for libraries that don't need backtrace information on a crash. rdar://11844710 llvm-svn: 164426
* [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.Chad Rosier2012-09-214-0/+16
| | | | llvm-svn: 164420
* Have the DbgVariable "isArtificial" and "isObjectPointer" notEric Christopher2012-09-212-5/+5
| | | | | | | | | | | | care about it being an argument variable so that we can decide that captured block and lambda vars that don't happen to be arguments could be an argument pointer. Add the object pointer for one case onto the subprogram die. rdar://12001329 llvm-svn: 164419
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164415
* Add comment.Chad Rosier2012-09-211-1/+2
| | | | llvm-svn: 164414
* Fix a significant recent(?) regression. StackSlotColoring no longer did anythingEvan Cheng2012-09-214-3/+10
| | | | | | | | | because LiveStackAnalysis was not preserved by VirtRegWriter. This caused big stack usage regression in some cases. rdar://12340383 llvm-svn: 164408
* LoopIdiom: Give up when the loop is not in canonical form.Benjamin Kramer2012-09-211-0/+5
| | | | | | | | | We rely on it when doing the transforms. This can happen when there is an indirectbr in the loop. Fixes PR13892. llvm-svn: 164383
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-aligned i32 loads/stores. rdar://12304911 llvm-svn: 164381
* InstCombine: Make sure we use the pre-zext type when creating a constant of ↵Benjamin Kramer2012-09-211-1/+2
| | | | | | | | a value that is zext'd. Fixes PR13250. llvm-svn: 164377
* Encapsulate the "construct*AlignmentFromInt" functions.Bill Wendling2012-09-212-4/+4
| | | | llvm-svn: 164373
* Fix a typo in r164357Michael Liao2012-09-211-8/+8
| | | | llvm-svn: 164372
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-214-11/+12
| | | | | | Attributes class. Now with fix. llvm-svn: 164370
* BitcodeReader: Correctly insert blockaddress constant referring to a already ↵Benjamin Kramer2012-09-211-6/+22
| | | | | | | | | | | | parsed function. We inserted a placeholder that was never replaced because the function was already visited. Assert that all placeholders have been resolved when tearing down the bitcode reader. Fixes PR13895. llvm-svn: 164369
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. llvm-svn: 164361
* Add missing i8 max/min/umax/umin supportMichael Liao2012-09-211-9/+44
| | | | | | - Fix PR5145 and turn on test 8-bit atomic ops llvm-svn: 164358
* Revise td of X86 atomic instructionsMichael Liao2012-09-213-218/+209
| | | | | | | - Rewirte most atomic instructions in templates for both better maintenance and future extensions, such as HLE in TSX. llvm-svn: 164357
* Mips16FrameLowering.cpp: Remove unused TII introduced in r164349. ↵NAKAMURA Takumi2012-09-211-1/+0
| | | | | | [-Wunused-variable] llvm-svn: 164354
* Properly save and restore RA and Mips16 callee save registers S0,S1Akira Hatanaka2012-09-213-6/+52
| | | | | | Patch by Reed Kotler. llvm-svn: 164349
* [fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier2012-09-211-0/+6
| | | | | | | non-halfword-aligned i16 loads/stores. rdar://12304911 llvm-svn: 164345
* Tidy up. Whitespace.Jim Grosbach2012-09-211-2/+2
| | | | llvm-svn: 164344
* Tidy up. Formatting.Jim Grosbach2012-09-211-1/+1
| | | | llvm-svn: 164343
* ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach2012-09-211-2/+29
| | | | | | | | | | | The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 llvm-svn: 164340
* Ignore PHI-defs for -new-coalescer interference checks.Jakob Stoklund Olesen2012-09-201-4/+8
| | | | | | | | A PHI can't create interference on its own. If two live ranges interfere at a PHI, they must also interfere when leaving one of the PHI predecessors. llvm-svn: 164330
* Extend -new-coalescer SSA update to handle mapped values as well.Jakob Stoklund Olesen2012-09-202-9/+62
| | | | | | | | | | | | | The old-fashioned many-to-one value mapping doesn't always work when merging vector lanes. A value can map to multiple different values, and it can even be necessary to insert new PHIs. When a value number is defined by a copy from a value number that required SSa update, include the live range of the copied value number in the SSA update as well. It is not necessarily a copy of the original value number any longer. llvm-svn: 164329
* Only emit DW_AT_object_pointer if this is a definition.Eric Christopher2012-09-201-3/+0
| | | | llvm-svn: 164326
* SimplifyCFG: sink common codes from IF, ELSE blocks down to END block.Manman Ren2012-09-201-0/+173
| | | | | | | | | | | | We already have HoistThenElseCodeToIf, this patch implements SinkThenElseCodeToEnd. When END block has only two predecessors and each predecessor terminates with unconditional branches, we compare instructions in IF and ELSE blocks backwards and check whether we can sink the common instructions down. rdar://12191395 llvm-svn: 164325
* Revert r164308 to fix buildbots.Bill Wendling2012-09-204-12/+11
| | | | llvm-svn: 164309
* Make the 'get*AlignmentFromAttr' functions into member functions within the ↵Bill Wendling2012-09-204-11/+12
| | | | | | Attributes class. llvm-svn: 164308
* Remove more bare uses of the different Attribute enums.Bill Wendling2012-09-201-6/+6
| | | | llvm-svn: 164307
* Make the 'getAsString' function a method of the Attributes class.Bill Wendling2012-09-203-48/+48
| | | | llvm-svn: 164305
* Fix 80-col violations.Nadav Rotem2012-09-201-13/+19
| | | | llvm-svn: 164297
* Change enum type in a static table to uint8_t instead. Saves about 700 ↵Craig Topper2012-09-201-6/+6
| | | | | | hundred bytes of static data. Change unsigned char in same table to uint8_t for explicitness. llvm-svn: 164285
* Re-work X86 code generation of atomic ops with spin-loopMichael Liao2012-09-205-540/+508
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Rewrite/merge pseudo-atomic instruction emitters to address the following issue: * Reduce one unnecessary load in spin-loop previously the spin-loop looks like thisMBB: newMBB: ld t1 = [bitinstr.addr] op t2 = t1, [bitinstr.val] not t3 = t2 (if Invert) mov EAX = t1 lcs dest = [bitinstr.addr], t3 [EAX is implicit] bz newMBB fallthrough -->nextMBB the 'ld' at the beginning of newMBB should be lift out of the loop as lcs (or CMPXCHG on x86) will load the current memory value into EAX. This loop is refined as: thisMBB: EAX = LOAD [MI.addr] mainMBB: t1 = OP [MI.val], EAX LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined] JNE mainMBB sinkMBB: * Remove immopc as, so far, all pseudo-atomic instructions has all-register form only, there is no immedidate operand. * Remove unnecessary attributes/modifiers in pseudo-atomic instruction td * Fix issues in PR13458 - Add comprehensive tests on atomic ops on various data types. NOTE: Some of them are turned off due to missing functionality. - Revise tests due to the new spin-loop generated. llvm-svn: 164281
* Convert some attribute existence queries over to use the predicate methods.Bill Wendling2012-09-194-38/+38
| | | | llvm-svn: 164268
* Add predicates for queries on whether an attribute exists.Bill Wendling2012-09-191-7/+6
| | | | llvm-svn: 164264
* Add in new data types that are used by AMDIL/ANL among others.Micah Villmow2012-09-191-0/+20
| | | | llvm-svn: 164261
* Resolve conflicts involving dead vector lanes for -new-coalescer.Jakob Stoklund Olesen2012-09-191-9/+155
| | | | | | | | | | | | | | | | | | | | | A common coalescing conflict in vector code is lane insertion: %dst = FOO %src = BAR %dst:ssub0 = COPY %src The live range of %src interferes with the ssub0 lane of %dst, but that lane is never read after %src would have clobbered it. That makes it safe to merge the live ranges and eliminate the COPY: %dst = FOO %dst:ssub0 = BAR This patch teaches the new coalescer to resolve conflicts where dead vector lanes would be clobbered, at least as long as the clobbered vector lanes don't escape the basic block. llvm-svn: 164250
* This patch adds memory support functions which will later be used to ↵Andrew Kaylor2012-09-193-90/+325
| | | | | | implement section-specific protection handling in MCJIT. llvm-svn: 164249
* Add support for macro parameters/arguments delimited by spaces,Preston Gurd2012-09-193-25/+133
| | | | | | | | | | to improve compatibility with GNU as. Based on a patch by PaX Team. Fixed assertion failures on non-Darwin and added additional test cases. llvm-svn: 164248
* Add support for accessing an MDNode's operands via the C binding. Patch byDuncan Sands2012-09-191-0/+13
| | | | | | Anthony Bryant. llvm-svn: 164247
* Support default parameters/arguments for assembler macros.Preston Gurd2012-09-191-7/+31
| | | | | | | | This patch is based on the one by PaX Team. Patch by Andy Zhang! llvm-svn: 164246
* Enhance unmatched '.endr' directive error message in assembler.Preston Gurd2012-09-191-1/+1
| | | | | | | | The directive can be matched with directives other than '.rept' Patch by Andy Zhang! llvm-svn: 164245
* Unify the logic in SelectAtomicLoadAdd and SelectAtomicLoadArithMichael Liao2012-09-191-176/+140
| | | | | | | | | | | - Merge the processing of LOAD_ADD with other atomic load-arith operations - Separate the logic getting target constant for atomic-load-op and add an optimization for atomic-load-add on i16 with negative value - Optimize a minor case for atomic-fetch-add i16 with negative operand. Test case is revised. llvm-svn: 164243
OpenPOWER on IntegriCloud