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* [PATCH] [PGO] Fixed cast operation in ↵Ana Pazos2017-06-191-1/+1
| | | | | | | | | | | | | | emIntrinsicVisitor::instrumentOneMemIntrinsic. Reviewers: xur, efriedma, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34293 llvm-svn: 305737
* Revert r305382, it caused PR33513.Nico Weber2017-06-191-6/+6
| | | | llvm-svn: 305735
* [CGP, PowerPC] try to constant fold before creating loads for memcmp expansionSanjay Patel2017-06-191-3/+13
| | | | | | | | | | | | | | | This is the last step needed to avoid regressions for x86 before we flip the switch to allow expansion of the smallest set of memcpy() via CGP. The DAG version checks for constant strings, so we need to do that here too. FWIW, the 2 constant test is not handled by LibCallSimplifier::optimizeMemCmp() because that code is limited to 8-bit constant arrays. LibCallSimplifier will also fail to optimize some 1 constant tests because its alignment requirements are too strict (shouldn't require alignment for a constant operand). Differential Revision: https://reviews.llvm.org/D34071 llvm-svn: 305734
* Remove convenient but probably not worthwhile macro for lambda workaroundDavid Blaikie2017-06-191-15/+18
| | | | | | Cleanup from r305405 llvm-svn: 305731
* Have writeCOFFWriter return Expected<unique_ptr>.Eric Beckmann2017-06-191-16/+14
| | | | | | | | | | | | Summary: Have writeCOFFWriter return Expected<unique_ptr> instead of requiring being passed an uninitialized unique_ptr. Reviewers: zturner, ruiu Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34307 llvm-svn: 305730
* Improve profile-guided heuristics to use estimated trip count.Taewook Oh2017-06-191-27/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Existing heuristic uses the ratio between the function entry frequency and the loop invocation frequency to find cold loops. However, even if the loop executes frequently, if it has a small trip count per each invocation, vectorization is not beneficial. On the other hand, even if the loop invocation frequency is much smaller than the function invocation frequency, if the trip count is high it is still beneficial to vectorize the loop. This patch uses estimated trip count computed from the profile metadata as a primary metric to determine coldness of the loop. If the estimated trip count cannot be computed, it falls back to the original heuristics. Reviewers: Ayal, mssimpso, mkuper, danielcdh, wmi, tejohnson Reviewed By: tejohnson Subscribers: tejohnson, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32451 llvm-svn: 305729
* [InstCombine] Make sure AddReachableCodeToWorklist sets MadeIRChangeBjorn Pettersson2017-06-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some optimizations in AddReachableCodeToWorklist did not update the MadeIRChange state. This could happen both when removing trivially dead instructions (DCE) and at constant folds. It is essential that changes to the IR is reported correctly, since for example InstCombinePass::run() will indicate that all analyses are preserved otherwise. And the CGPassManager determines if the CallGraph is up-to-date based on status from InstructionCombiningPass::runOnFunction(). The new test case early_dce_clobbers_callgraph.ll is a reproducer for some asserts that started to trigger after changes in the inliner in r305245. With this patch the test case passes again. Reviewers: sanjoy, craig.topper, dblaikie Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34346 llvm-svn: 305725
* Revert r304824 "Fix PR23384 (part 3 of 3)"Hans Wennborg2017-06-193-14/+1
| | | | | | | | | | | | | | | | | This seems to be interacting badly with ASan somehow, causing false reports of heap-buffer overflows: PR33514. > Summary: > The patch makes instruction count the highest priority for > LSR solution for X86 (previously registers had highest priority). > > Reviewers: qcolombet > > Differential Revision: http://reviews.llvm.org/D30562 > > From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 305720
* [PDB] Start emitting source file and line informationReid Kleckner2017-06-193-12/+32
| | | | | | | | | | | | | | | | | | | | | | | Summary: This is a first step towards getting line info to show up in VS and windbg. So far, only llvm-pdbutil can parse the PDBs that we produce. cvdump doesn't like something about our file checksum tables. I'll have to dig into that next. This patch adds a new DebugSubsectionRecordBuilder which takes bytes directly from some other producer, such as a linker, and sticks it into the PDB. Line tables only need to be relocated. No data needs to be rewritten. File checksums and string tables, on the other hand, need to be re-done. Reviewers: zturner, ruiu Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D34257 llvm-svn: 305713
* [CodeView] Fix dumping of public symbol record flagsReid Kleckner2017-06-194-3/+22
| | | | | | | I noticed nonsensical type information while dumping PDBs produced by MSVC. llvm-svn: 305708
* [NewGVN] Simplify findConditionEquivalence(). NFCI.Davide Italiano2017-06-191-3/+1
| | | | llvm-svn: 305707
* Remove brackets, NFC.Dinar Temirbulatov2017-06-191-4/+2
| | | | llvm-svn: 305706
* [InstCombine] Cleanup some duplicated one use checksCraig Topper2017-06-191-10/+4
| | | | | | | | | | | | | | | | | | | Summary: These 4 patterns have the same one use check repeated twice for each. Once without a cast and one with. But the cast has no effect on what method is called. For the OR case I believe it is always profitable regardless of the number of uses since we'll never increase the instruction count. For the AND case I believe it is profitable if the pair of xors has one use such that we'll get rid of it completely. Or if the C value is something freely invertible, in which case the not doesn't cost anything. Reviewers: spatel, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34308 llvm-svn: 305705
* [Reassociate] Support some reassociation of vector xorsCraig Topper2017-06-191-6/+7
| | | | | | | | | | | | | | | | | Summary: Currently we don't try to do anything with vector xors. This patch adds support for removing duplicate pairs from a chain of vector xors as its pretty easy to support. We still dont' try to combine the xors with and/ors, but I might try that in a future patch. Reviewers: mcrosier, davide, resistor Reviewed By: mcrosier Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34338 llvm-svn: 305704
* [Reassociate] Make one of the helper methods static because it doesn't use ↵Craig Topper2017-06-191-2/+2
| | | | | | any class variables. NFC llvm-svn: 305703
* Allow truncated and extend memory operations in Store Merge. NFCI.Nirav Dave2017-06-191-24/+46
| | | | | | | | | | As all store merges checks are based on the memory operation performed, allow use of truncated stores and extended loads as valid input candidates for merging. Relanding after fixing selection between truncated and normal store. llvm-svn: 305701
* [JumpThreading][LVI] Invalidate LVI information after blocks are mergedAnna Thomas2017-06-191-0/+31
| | | | | | | | | | | | | | | | | | | Summary: After a single predecessor is merged into a basic block, we need to invalidate the LVI information for the new merged block, when LVI is not provably true for all of instructions in the new block. The test cases added show the correct LVI information using the LVI printer pass. Reviewers: reames, dberlin, davide, sanjoy Reviewed by: dberlin, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34108 llvm-svn: 305699
* [TRE] Improve code motion in TRE, use AA to tell whether a load can be moved ↵Xin Tong2017-06-191-19/+27
| | | | | | | | | | | | | | | | before a call that writes to memory. Summary: use AA to tell whether a load can be moved before a call that writes to memory. Reviewers: dberlin, davide, sanjoy, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D34115 llvm-svn: 305698
* [AArch64] Fix order of checks in shouldScheduleAdjacent.Florian Hahn2017-06-191-2/+2
| | | | | | | We need to check the opcode of FirstMI before accessing the operands. This caused a buildbot failure during bootstrapping on AArch64. llvm-svn: 305694
* AMDGPU/GlobalISel: Mark G_BITCAST s32 <--> <2 x s16> legalTom Stellard2017-06-191-0/+7
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D34129 llvm-svn: 305692
* [GlobalISel][X86] Fold FI/G_GEP into LDR/STR instruction addressing mode.Igor Breger2017-06-191-4/+42
| | | | | | | | | | | | | | Summary: Implement some of the simplest addressing modes.It should help to test ABI. Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33888 llvm-svn: 305691
* Recommit rL305677: [CodeGen] Add generic MacroFusion passFlorian Hahn2017-06-196-253/+204
| | | | | | | | | | | | | Use llvm::make_unique to avoid ambiguity with MSVC. This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305690
* [ARM] GlobalISel: Support G_ICMP for s8 and s16Diana Picus2017-06-191-0/+2
| | | | | | Widen to s32 (like all other binary ops). llvm-svn: 305683
* Revert r305677 [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-196-204/+253
| | | | | | This causes Windows buildbot failures do an ambiguous call. llvm-svn: 305681
* [CodeGen] Add generic MacroFusion pass.Florian Hahn2017-06-196-253/+204
| | | | | | | | | | | | | | | | | | Summary: This patch adds a generic MacroFusion pass, that is used on X86 and AArch64, which both define target-specific shouldScheduleAdjacent functions. This generic pass should make it easier for other targets to implement macro fusion and I intend to add macro fusion for ARM shortly. Reviewers: craig.topper, evandro, t.p.northover, atrick, MatzeB Reviewed By: MatzeB Subscribers: atrick, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34144 llvm-svn: 305677
* [ARM] GlobalISel: Support G_ICMP for i32 and pointersDiana Picus2017-06-193-0/+119
| | | | | | | | | | | | | | Add support throughout the pipeline: - mark as legal for s32 and pointers - map to GPRs - lower to a sequence of instructions, which moves 0 or 1 into the result register based on the flags set by a CMPrr We have copied from FastISel a helper function which maps CmpInst predicates into ARMCC codes. Ideally, we should be able to move it somewhere that both FastISel and GlobalISel can use. llvm-svn: 305672
* [SCEV] Teach SCEVExpander to expand BinPowMax Kazantsev2017-06-191-5/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of SCEVExpander demonstrates a very naive behavior when it deals with power calculation. For example, a SCEV for x^8 looks like (x * x * x * x * x * x * x * x) If we try to expand it, it generates a very straightforward sequence of muls, like: x2 = mul x, x x3 = mul x2, x x4 = mul x3, x ... x8 = mul x7, x This is a non-efficient way of doing that. A better way is to generate a sequence of binary power calculation. In this case the expanded calculation will look like: x2 = mul x, x x4 = mul x2, x2 x8 = mul x4, x4 In some cases the code size reduction for such SCEVs is dramatic. If we had a loop: x = a; for (int i = 0; i < 3; i++) x = x * x; And this loop have been fully unrolled, we have something like: x = a; x2 = x * x; x4 = x2 * x2; x8 = x4 * x4; The SCEV for x8 is the same as in example above, and if we for some reason want to expand it, we will generate naively 7 multiplications instead of 3. The BinPow expansion algorithm here allows to keep code size reasonable. This patch teaches SCEV Expander to generate a sequence of BinPow multiplications if we have repeating arguments in SCEVMulExpressions. Differential Revision: https://reviews.llvm.org/D34025 llvm-svn: 305663
* NewGVN: Fix PR 33461, caused by slightly overzealous verification.Daniel Berlin2017-06-191-18/+30
| | | | llvm-svn: 305657
* Delete TypeDatabase.Zachary Turner2017-06-185-585/+86
| | | | | | | | Merge the functionality into the random access type collection. This class was only being used in 2 places, so getting rid of it simplifies the code. llvm-svn: 305653
* [APFloat] Move the integerPartWidth constant into APFloatBase. Remove ↵Craig Topper2017-06-181-37/+30
| | | | | | integerPart typedef at file scope and just use the one in APFloatBase everywhere. NFC llvm-svn: 305652
* [Reassociate] Use APInt::isNullValue() instead of comparing with 0. NFCCraig Topper2017-06-181-8/+9
| | | | | | This should compile to slightly better code. llvm-svn: 305651
* Implement AllocateRWX and ReleaseRWX for NetBSDKamil Rytarowski2017-06-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: NetBSD ships with PaX MPROTECT disallowing RWX mappings. There is a solution to bypass this restriction with double mapping RX (code) and RW (data) using mremap(2) MAP_REMAPDUP. The initial mapping must be mmap(2)ed with protection: PROT_MPROTECT(PROT_EXEC). This functionality to bypass PaX MPROTECT appeared in NetBSD-7.99.72. This patch fixes 20 failing tests: - LLVM :: DebugInfo/debuglineinfo-macho.test - LLVM :: DebugInfo/debuglineinfo.test - LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_Mips64r2N64_PIC_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_N32_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_N64R6_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_O32R6_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/Mips/ELF_O32_PIC_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/COFF_i386.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/COFF_x86_64.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF-relaxed.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_STT_FILE.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_x64-64_PC8_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_x64-64_PIC_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_x86-64_PIC-small-relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_x86-64_debug_frame.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/ELF_x86_64_StubBuf.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/MachO_empty_ehframe.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/MachO_i386_DynNoPIC_relocations.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/MachO_i386_eh_frame.s - LLVM :: ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s Sponsored by <The NetBSD Foundation> Reviewers: joerg, lhames Reviewed By: joerg Subscribers: sdardis, llvm-commits, arichardson Differential Revision: https://reviews.llvm.org/D33874 llvm-svn: 305650
* Add argmononly attribute to strlen and wcslen, i.e. they only read memory ↵Xin Tong2017-06-181-0/+1
| | | | | | | | | | | | | | | | (string) passed to them. Summary: This allows strlen to be moved out of the loop in case its argument is not modified in the loop in LICM. Reviewers: hfinkel, davide, sanjoy, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34323 llvm-svn: 305641
* Fixed the warning introduced by r305625 to make ubuntu-gcc7.1-werror bot green.Galina Kistanova2017-06-171-1/+1
| | | | llvm-svn: 305640
* [SROA] Add support for non-integral pointersSanjoy Das2017-06-171-2/+11
| | | | | | | | | | | | | | Summary: C.f. http://llvm.org/docs/LangRef.html#non-integral-pointer-type Reviewers: chandlerc, loladiro Reviewed By: loladiro Subscribers: reames, loladiro, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D32203 llvm-svn: 305639
* [TRE] Add assertion for folding trivial return blockXin Tong2017-06-171-0/+4
| | | | llvm-svn: 305637
* [TRE] Update comments. NFCXin Tong2017-06-171-1/+1
| | | | llvm-svn: 305636
* [CMake] Introduce LLVM_TARGET_TRIPLE_ENV as an option to override ↵NAKAMURA Takumi2017-06-172-1/+15
| | | | | | | | | | | | | | | | | | | LLVM_DEFAULT_TARGET_TRIPLE at runtime. No behavior is changed if LLVM_TARGET_TRIPLE_ENV is blank or undefined. If LLVM_TARGET_TRIPLE_ENV is "TEST_TARGET_TRIPLE" and $TEST_TARGET_TRIPLE is not blank, llvm::sys::getDefaultTargetTriple() returns $TEST_TARGET_TRIPLE. Lit resets config.target_triple and config.environment[LLVM_TARGET_TRIPLE_ENV] to change the default target. Without changing LLVM_DEFAULT_TARGET_TRIPLE nor rebuilding, lit can be run; TEST_TARGET_TRIPLE=i686-pc-win32 bin/llvm-lit -sv path/to/test/ TEST_TARGET_TRIPLE=i686-pc-win32 ninja check-clang-tools Differential Revision: https://reviews.llvm.org/D33662 llvm-svn: 305632
* Rework logic and comment out the default relocation models for PPC.Eric Christopher2017-06-171-10/+13
| | | | llvm-svn: 305630
* Turn a large if block into a smaller early return for clarity.Eric Christopher2017-06-171-11/+10
| | | | llvm-svn: 305629
* Remove the old and unused PPC32 and PPC64TargetMachine classes.Eric Christopher2017-06-172-47/+4
| | | | llvm-svn: 305628
* Remove unused forward declaration.Eric Christopher2017-06-171-1/+0
| | | | llvm-svn: 305627
* Tidy up some calls to getRegister for readability.Eric Christopher2017-06-171-5/+6
| | | | llvm-svn: 305626
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2017-06-171-116/+317
| | | | | | | | | | | | | | | | | | | Re-apply r276044/r279124/r305516. Fixed a problem where we would refuse to place spills as the very first instruciton of a basic block and thus artifically increase pressure (test in test/CodeGen/PowerPC/scavenging.mir:spill_at_begin) This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 305625
* [PPC] Remove isBarrier from CFENCE8's definition.Tim Shen2017-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is my misunderstanding on isBarrier. It's not for memory barriers, but for other control flow purposes. lwsync doesn't have it either. This fixes a simple crash with -verify-machineinstrs like below: define void @Foo() { entry: %tmp = load atomic i64, i64* undef acquire, align 8 unreachable } I deliberately don't want to check in the test, since there is little chance to regress on such a mistake. Such a test adds noise to the code base. I plan to check in first, since it fixes a crash, and the fix is obvious. Reviewers: kbarton, echristo Subscribers: sanjoy, nemanjai, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34314 llvm-svn: 305624
* [SelectionDAG] Update Loop info after splitting critical edges.Davide Italiano2017-06-171-6/+9
| | | | | | The analysis is expected to be preserved by SelectionDAG. llvm-svn: 305621
* Don't crash if a type record can't be found.Zachary Turner2017-06-171-0/+9
| | | | | | | This was a regression introduced in a previous patch. Adding back the code that handles this case. llvm-svn: 305617
* [WebAssembly] Use __stack_pointer global when writing wasm binarySam Clegg2017-06-1610-69/+37
| | | | | | | | | | | | | | | | | | This ensures that symbolic relocations are generated for stack pointer manipulations. These relocations are of type R_WEBASSEMBLY_GLOBAL_INDEX_LEB. This change also adds support for reading relocations of this type in WasmObjectFile.cpp. Since its a globally imported symbol this does mean that the get_global/set_global instruction won't be valid until the objects are linked that global used in no longer an imported global. Differential Revision: https://reviews.llvm.org/D34172 llvm-svn: 305616
* [CodeView] Fix random access of type names.Zachary Turner2017-06-163-10/+258
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Suppose we had a type index offsets array with a boundary at type index N. Then you request the name of the type with index N+1, and that name requires the name of index N-1 (think a parameter list, for example). We didn't handle this, and we would print something like (<unknown UDT>, <unknown UDT>). The fix for this is not entirely trivial, and speaks to a larger problem. I think we need to kill TypeDatabase, or at the very least kill TypeDatabaseVisitor. We need a thing that doesn't do any caching whatsoever, just given a type index it can compute the type name "the slow way". The reason for the bug is that we don't have anything like that. Everything goes through the type database, and if we've visited a record, then we're "done". It doesn't know how to do the expensive thing of re-visiting dependent records if they've not yet been visited. What I've done here is more or less copied the code (albeit greatly simplified) from TypeDatabaseVisitor, but wrapped it in an interface that just returns a std::string. The logic of caching the name is now in LazyRandomTypeCollection. Eventually I'd like to move the record database here as well and the visited record bitfield here as well, at which point we can actually just delete TypeDatabase. I don't see any reason for it if a "sequential" collection is just a special case of a random access collection with an empty partial offsets array. Differential Revision: https://reviews.llvm.org/D34297 llvm-svn: 305612
* Remove some dead code / includes.Zachary Turner2017-06-162-4/+0
| | | | | | | I'm trying to get rid of the TypeDatabase class, so the first step is to minimize its footprint. llvm-svn: 305611
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