summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Missed reverting this bit.Bill Wendling2010-11-011-1/+1
| | | | llvm-svn: 117971
* Minor cleanup.Bill Wendling2010-11-011-11/+7
| | | | llvm-svn: 117969
* rearrange a bit.Chris Lattner2010-11-011-50/+55
| | | | llvm-svn: 117967
* Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-015-4/+93
| | | | llvm-svn: 117964
* Add kill flag verification.Jakob Stoklund Olesen2010-11-011-2/+13
| | | | | | | | At least X86FloatingPoint requires correct kill flags after register allocation, and targets using register scavenging benefit. Conservative kill flags are not enough. llvm-svn: 117960
* Update kill flags while rewriting instructions after splitting.Jakob Stoklund Olesen2010-11-011-0/+3
| | | | llvm-svn: 117959
* Move the machine operand MC encoding patterns to the parent classes.Bill Wendling2010-11-012-41/+36
| | | | llvm-svn: 117956
* When folding away a (shl (shr)) pair, we need to check that the bits that ↵Owen Anderson2010-11-011-1/+1
| | | | | | | | will BECOME the low bits are zero, not that the current low bits are zero. Fixes <rdar://problem/8606771>. llvm-svn: 117953
* use our fancy new MnemonicAlias mechanism to remove a bunch of hacksChris Lattner2010-11-012-51/+16
| | | | | | from X86AsmParser.cpp llvm-svn: 117952
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-012-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. llvm-svn: 117950
* Don't assign new registers created during a split to the same stack slot, butJakob Stoklund Olesen2010-11-013-16/+3
| | | | | | give them individual stack slots once the are actually spilled. llvm-svn: 117945
* Add basic LiveStacks verification.Jakob Stoklund Olesen2010-11-011-0/+20
| | | | | | | When an instruction refers to a spill slot with a LiveStacks entry, check that the spill slot is live at the instruction. llvm-svn: 117944
* NEON does not support truncating vector stores. Radar 8598391.Bob Wilson2010-11-011-0/+4
| | | | llvm-svn: 117940
* Add FIXME.Jim Grosbach2010-11-011-0/+1
| | | | llvm-svn: 117936
* Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gatesJim Grosbach2010-11-012-20/+22
| | | | | | | codegen using the patterns; the latter gates the assembler recognizing the instruction. llvm-svn: 117931
* Write the line info to .debug_line.Rafael Espindola2010-11-011-0/+9
| | | | llvm-svn: 117930
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-012-15/+21
| | | | llvm-svn: 117929
* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | llvm-svn: 117927
* Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it.Rafael Espindola2010-11-014-69/+46
| | | | llvm-svn: 117925
* The T2 extract/pack instructions are only valid in Thumb2 mode. Mark theJim Grosbach2010-11-011-12/+14
| | | | | | patterns as such llvm-svn: 117923
* Add support for .value.Rafael Espindola2010-11-011-0/+2
| | | | llvm-svn: 117922
* Implement .weakref.Rafael Espindola2010-11-018-2/+121
| | | | llvm-svn: 117911
* Move instruction encoding bits into the parent class and remove the temporaryBill Wendling2010-11-012-273/+224
| | | | | | | *_Encode classes. These instructions are the only ones which use those classes, so a subclass isn't necessary. llvm-svn: 117906
* The testcase is now XFAILed. Sorry about the breakage.Bill Wendling2010-11-011-0/+2
| | | | llvm-svn: 117904
* "mov[zs]x (mem), GR16" are not ambiguous: the memChris Lattner2010-11-011-0/+6
| | | | | | must be 8 bits. Support this memory form. llvm-svn: 117902
* Implement enough of the missing instalias support to getChris Lattner2010-11-012-3/+33
| | | | | | | | | | | | | | | | | | aliases installed and working. They now work when the matched pattern and the result instruction have exactly the same operand list. This is now enough for us to define proper aliases for movzx and movsx, implementing rdar://8017633 and PR7459. Note that we do not accept instructions like: movzx 0(%rsp), %rsi GAS accepts this instruction, but it doesn't make any sense because we don't know the size of the memory operand. It could be 8/16/32 bits. llvm-svn: 117901
* make the asm matcher emitter reject instructions that have commentsChris Lattner2010-11-011-2/+2
| | | | | | | in their asmstring. Fix the two x86 "NOREX" instructions that have them. If these comments are important, the instlowering stuff can print them. llvm-svn: 117897
* reject instructions that contain a \n in their asmstring. MarkChris Lattner2010-11-012-8/+13
| | | | | | | various X86 and ARM instructions that are bitten by this as isCodeGenOnly, as they are. llvm-svn: 117884
* Revert r117876 for now, it's causing more testsuite failures.Eric Christopher2010-10-311-2/+0
| | | | llvm-svn: 117879
* Disable the peephole optimizer until 186.crafty on armv6 is fixed. This is whatBill Wendling2010-10-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | looks like is happening: Without the peephole optimizer: (1) sub r6, r6, #32 orr r12, r12, lr, lsl r9 orr r2, r2, r3, lsl r10 (x) cmp r6, #0 ldr r9, LCPI2_10 ldr r10, LCPI2_11 (2) sub r8, r8, #32 (a) movge r12, lr, lsr r6 (y) cmp r8, #0 LPC2_10: ldr lr, [pc, r10] (b) movge r2, r3, lsr r8 With the peephole optimizer: ldr r9, LCPI2_10 ldr r10, LCPI2_11 (1*) subs r6, r6, #32 (2*) subs r8, r8, #32 (a*) movge r12, lr, lsr r6 (b*) movge r2, r3, lsr r8 (1) is used by (x) for the conditional move at (a). (2) is used by (y) for the conditional move at (b). After the peephole optimizer, these the flags resulting from (1*) are ignored and only the flags from (2*) are considered for both conditional moves. llvm-svn: 117876
* Attach a GCModuleInfo to a MachineFunction.Nicolas Geoffray2010-10-312-3/+6
| | | | llvm-svn: 117867
* fix the !eq operator in tblgen to return a bit instead of an int.Chris Lattner2010-10-312-0/+6
| | | | | | | | Use this to make the X86 and ARM targets set isCodeGenOnly=1 automatically for their instructions that have Format=Pseudo, resolving a hack in tblgen. llvm-svn: 117862
* two changes: make the asmmatcher generator ignore ARM pseudos properly,Chris Lattner2010-10-314-9/+19
| | | | | | | and make it a hard error for instructions to not have an asm string. These instructions should be marked isCodeGenOnly. llvm-svn: 117861
* reapply r117858 with apparent editor malfunction fixed (somehow I Chris Lattner2010-10-315-11/+21
| | | | | | got a dulicated line). llvm-svn: 117860
* revert r117858 while I check out a failure I missed.Chris Lattner2010-10-315-21/+11
| | | | llvm-svn: 117859
* the asm matcher can't handle operands with modifiers (like ${foo:bar}).Chris Lattner2010-10-315-11/+21
| | | | | | | | | | | Instead of silently ignoring these instructions, emit a hard error and force the target author to either refactor the target or mark the instruction 'isCodeGenOnly'. Mark a few instructions in ARM and MBlaze as isCodeGenOnly the are doing this. llvm-svn: 117858
* sketch out the planned instruction alias mechanism, add some comments aboutChris Lattner2010-10-311-0/+14
| | | | | | how the push/pop mnemonic aliases are wrong. llvm-svn: 117857
* Factorize the duplicated logic for choosing the right argumentDuncan Sands2010-10-314-56/+36
| | | | | | | calling convention out of the fast and normal ISel files, and into the calling convention TD file. llvm-svn: 117856
* Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,Duncan Sands2010-10-311-16/+1
| | | | | | | which has the same logic specified in the CallingConv TD file. This brings FastISel in line with the standard X86 ISel. llvm-svn: 117855
* Add support for files with more than 65280 sections. No testcase sinceRafael Espindola2010-10-311-42/+109
| | | | | | it would be a bit too big :-) llvm-svn: 117849
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | llvm-svn: 117848
* Resolve a terrible hack in tblgen: instead of hardcodingChris Lattner2010-10-301-2/+2
| | | | | | | "In32BitMode" and "In64BitMode" into tblgen, allow any predicate that inherits from AssemblerPredicate. llvm-svn: 117831
* Implement (and document!) support for MnemonicAlias's to have Requires Chris Lattner2010-10-302-14/+20
| | | | | | | | | | | directives, allowing things like this: def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; Move the rest of the X86 MnemonicAliases over to the .td file. llvm-svn: 117830
* really zap alias.Chris Lattner2010-10-301-1/+0
| | | | llvm-svn: 117824
* move fcompi alias to .td file and zap some useless code.Chris Lattner2010-10-302-11/+1
| | | | llvm-svn: 117823
* move rep aliases to td fileChris Lattner2010-10-302-5/+7
| | | | llvm-svn: 117822
* move sal aliases to .td file.Chris Lattner2010-10-302-5/+5
| | | | llvm-svn: 117821
* fix an encoding mismatch where "sal %eax, 1" was not using the short encodingChris Lattner2010-10-301-1/+1
| | | | | | for shl. Caught by inspection. llvm-svn: 117820
* move a bunch more aliases from .cpp -> .td file.Chris Lattner2010-10-302-22/+27
| | | | llvm-svn: 117819
* move cmov aliases to .td file.Chris Lattner2010-10-302-49/+25
| | | | llvm-svn: 117818
OpenPOWER on IntegriCloud