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* [X86][Btver2] Improved latency/throughput model for scalar int-to-float ↵Andrea Di Biagio2019-01-293-14/+16
| | | | | | | | | | | | | | conversions. Account for bypass delays when computing the latency of scalar int-to-float conversions. On Jaguar we need to account for an extra 6cy latency (see AMD fam16h SOG). This patch also fixes the number of micropcodes for the register-memory variants of scalar int-to-float conversions. Differential Revision: https://reviews.llvm.org/D57148 llvm-svn: 352518
* Adjust documentation for git migration.James Y Knight2019-01-292-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes most references to the paths: llvm.org/svn/ llvm.org/git/ llvm.org/viewvc/ github.com/llvm-mirror/ github.com/llvm-project/ reviews.llvm.org/diffusion/ to instead point to https://github.com/llvm/llvm-project. This is *not* a trivial substitution, because additionally, all the checkout instructions had to be migrated to instruct users on how to use the monorepo layout, setting LLVM_ENABLE_PROJECTS instead of checking out various projects into various subdirectories. I've attempted to not change any scripts here, only documentation. The scripts will have to be addressed separately. Additionally, I've deleted one document which appeared to be outdated and unneeded: lldb/docs/building-with-debug-llvm.txt Differential Revision: https://reviews.llvm.org/D57330 llvm-svn: 352514
* [SelectionDAGBuilder] Remove redundant variable. NFCI.Nirav Dave2019-01-291-7/+3
| | | | llvm-svn: 352506
* Reversing the checkin for version 352484 as tests are failing.Ayonam Ray2019-01-292-28/+52
| | | | llvm-svn: 352504
* [AMDGPU] Fix a weird WWM intrinsic issue.Neil Henning2019-01-292-17/+17
| | | | | | | | | | | I found a really strange WWM issue through a very convoluted shader that essentially boils down to a bug in SIInstrInfo where canReadVGPR did not correctly identify that WWM is like a copy and can have a VGPR as its source. Differential Revision: https://reviews.llvm.org/D56002 llvm-svn: 352500
* [CodeGen] Omit range checks from jump tables when lowering switches with ↵Ayonam Ray2019-01-292-52/+28
| | | | | | | | | | | | | | | | | unreachable default During the lowering of a switch that would result in the generation of a jump table, a range check is performed before indexing into the jump table, for the switch value being outside the jump table range and a conditional branch is inserted to jump to the default block. In case the default block is unreachable, this conditional jump can be omitted. This patch implements omitting this conditional branch for unreachable defaults. Review ID: D52002 Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev llvm-svn: 352484
* [WebAssembly] Re-enable main-function signature rewritingDan Gohman2019-01-291-12/+24
| | | | | | | | | | | | | | | | Re-enable the code to rewrite main-function signatures into "int main(int argc, char *argv[])", but limited to only handling the case of "int main(void)", so that it doesn't silently strip an argument in the "int main(int argc, char *argv[], char *envp[])" case. This allows main to be called by C startup code, since WebAssembly requires caller and callee signatures to match, so it can't rely on passing main a different number of arguments than it expects. Differential Revision: https://reviews.llvm.org/D57323 llvm-svn: 352479
* [ARM] Use sub for negative offset load/store in thumb1David Green2019-01-292-6/+47
| | | | | | | | | | | This attempts to optimise negative values used in load/store operands a little. We currently try to selct them as rr, materialising the negative constant using a MOV/MVN pair. This instead selects ri with an immediate of 0, forcing the add node to become a simpler sub. Differential Revision: https://reviews.llvm.org/D57121 llvm-svn: 352475
* [IPCP] Don't crash due to arg count/type mismatch between caller/calleeBjorn Pettersson2019-01-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch avoids an assert in IPConstantPropagation when there is a argument count/type mismatch between the caller and the callee. While this is actually UB on C-level (clang emits a warning), the IR verifier seems to accept it. I'm not sure what other frontends/languages might think about this, so simply bailing out to avoid hitting an assert (in CallSiteBase<>::getArgOperand or Value::doRAUW) seems like a simple solution. The problem is exposed by the fact that AbstractCallSites will look through a bitcast at the callee position of a call/invoke. Reviewers: jdoerfert, reames, efriedma Reviewed By: jdoerfert, efriedma Subscribers: eli.friedman, efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D57052 llvm-svn: 352469
* [DebugInfo][DAG] Process FrameIndex dbg.values unconditionallyJeremy Morse2019-01-291-0/+15
| | | | | | | | | | | | | | | A FrameIndex should be valid throughout a block regardless of what instructions get selected in that block -- therefore we shouldn't harness dbg.values that refer to FrameIndexes to an SDNode. There are numerous codegen reasons why an SDNode never appears or doesn't become a location that a DBG_VALUE can refer to. None of them actually affect the variable location. Therefore, before any other tests to encode dbg_values in a SelectionDAG, identify FrameIndex operands and encode them unattached to any SDNode. Differential Revision: https://reviews.llvm.org/D57328 llvm-svn: 352467
* [NFC] Use ArrayRef instead of SmallVectorImpl where possibleMax Kazantsev2019-01-291-6/+6
| | | | llvm-svn: 352466
* [COFF, ARM64] Don't put jump table into a separate COFF section for ↵Martin Storsjo2019-01-292-4/+13
| | | | | | | | | | | | | | | | | | | | | | EK_LabelDifference32 Windows ARM64 has PIC relocation model and uses jump table kind EK_LabelDifference32. This produces jump table entry as ".word LBB123 - LJTI1_2" which represents the distance between the block and jump table. A new relocation type (IMAGE_REL_ARM64_REL32) is needed to do the fixup correctly if they are in different COFF section. This change saves the jump table to the same COFF section as the associated code. An ideal fix could be utilizing IMAGE_REL_ARM64_REL32 relocation type. Patch by Tom Tan! Differential Revision: https://reviews.llvm.org/D57277 llvm-svn: 352465
* [CodeGenPrepare] Handle all debug calls in dupRetToEnableTailCallOpts()Jonas Paulsson2019-01-291-4/+2
| | | | | | | | | | | | This patch makes sure that a debug value that is after the bitcast in dupRetToEnableTailCallOpts() is also skipped. The reduced test case is from SPEC-2006 on SystemZ. Review: Vedant Kumar, Wolfgang Pieb https://reviews.llvm.org/D57050 llvm-svn: 352462
* Fix compiler warning when using clang 3.6.0Mikael Holmen2019-01-291-1/+1
| | | | | | | | | | | | Without the fix we get the following (with -Werror): ../lib/Target/X86/X86ISelLowering.cpp:14181:58: error: suggest braces around initialization of subobject [-Werror,-Wmissing-braces] SmallVector<std::array<int, 2>, 2> LaneSrcs(NumLanes, {-1, -1}); ^~~~~~ { } 1 error generated. llvm-svn: 352455
* [SCEV] Take correct loop in AddRec simplification. PR40420Max Kazantsev2019-01-291-1/+1
| | | | | | | | | | | | The code of AddRec simplification is using wrong loop when it creates a new AddRecExpr. It should be using AddRecLoop which we have saved and against which all gate checks are made, and not calling AddRec->getLoop() over and over again because AddRec may change and become an AddRecurrency from outer loop during the transform iterations. Considering this change trivial, commiting for postcommit review. llvm-svn: 352451
* [WebAssembly] Handle more types of uses in WebAssemblyAddMissingPrototypesSam Clegg2019-01-291-37/+10
| | | | | | | | | | | | | | Previously we were only handling bitcast operations, however prototypeless functions can also appear in other places such as comparisons and as function params. Switch to using replaceAllUsesWith() to replace the prototype-less function uses. This new approach results in some redundant bitcasting but is much simpler and handles all cases. Differential Revision: https://reviews.llvm.org/D56938 llvm-svn: 352445
* [PPC] Include tablegenerated PPCGenCallingConv.inc onceReid Kleckner2019-01-297-147/+137
| | | | | | | | | Move the CC analysis implementation to its own .cpp file instead of duplicating it and artificually using functions in PPCISelLowering.cpp and PPCFastISel.cpp. Follow-up to the same change done for X86, ARM, and AArch64. llvm-svn: 352444
* [WebAssembly] Expand BUILD_PAIR nodesThomas Lively2019-01-281-0/+3
| | | | | | | | | | Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish Differential Revision: https://reviews.llvm.org/D57276 llvm-svn: 352442
* [ThinLTO] Add option to dump per-module summary dot graphTeresa Johnson2019-01-281-0/+14
| | | | | | | | | | | | | | | | | | | | Summary: I found that there currently isn't a way to invoke exportToDot from the command line for a per-module summary index, and therefore no testing of that case. Add an internal option and use it to test dumping of per module summary indexes. In particular, I am looking at fixing the limitation that causes the aliasee GUID in the per-module summary to be 0, and want to be able to test that change. Reviewers: evgeny777 Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D57206 llvm-svn: 352441
* Demanded elements support for vector GEPsPhilip Reames2019-01-281-0/+12
| | | | | | | | GEPs can produce either scalar or vector results. If we're extracting only a subset of the vector lanes, simplifying the operands is helpful in eliminating redundant computation, and (eventually) allowing further optimizations Differential Revision: https://reviews.llvm.org/D57177 llvm-svn: 352440
* [ThinLTO] Refine reachability check to fix compile time increaseTeresa Johnson2019-01-281-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: A recent fix to the ThinLTO whole program dead code elimination (D56117) increased the thin link time on a large MSAN'ed binary by 2x. It's likely that the time increased elsewhere, but was more noticeable here since it was already large and ended up timing out. That change made it so we would repeatedly scan all copies of linkonce symbols for liveness every time they were encountered during the graph traversal. This was needed since we only mark one copy of an aliasee as live when we encounter a live alias. This patch fixes the issue in a more efficient manner by simply proactively visiting the aliasee (thus marking all copies live) when we encounter a live alias. Two notes: One, this requires a hash table lookup (finding the aliasee summary in the index based on aliasee GUID). However, the impact of this seems to be small compared to the original pre-D56117 thin link time. It could be addressed if we keep the aliasee ValueInfo in the alias summary instead of the aliasee GUID, which I am exploring in a separate patch. Second, we only populate the aliasee GUID field when reading summaries from bitcode (whether we are reading individual summaries and merging on the fly to form the compiled index, or reading in a serialized combined index). Thankfully, that's currently the only way we can get to this code as we don't yet support reading summaries from LLVM assembly directly into a tool that performs the thin link (they must be converted to bitcode first). I added a FIXME, however I have the fix under test already. The easiest fix is to simply populate this field always, which isn't hard, but more likely the change I am exploring to store the ValueInfo instead as described above will subsume this. I don't want to hold up the regression fix for this though. Reviewers: trentxintong Subscribers: mehdi_amini, inglorion, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D57203 llvm-svn: 352438
* Recommit r352255 "[SelectionDAG][X86] Don't use SEXTLOAD for promoting ↵Craig Topper2019-01-282-4/+16
| | | | | | | | | | | | | | | | masked loads in the type legalizer" This did not cause the buildbot failure it was previously reverted for. Original commit message: I'm not sure why we were using SEXTLOAD. EXTLOAD seems more appropriate since we don't care about the upper bits. This patch changes this and then modifies the X86 post legalization combine to emit a extending shuffle instead of a sign_extend_vector_inreg. Could maybe use an any_extend_vector_inre On AVX512 targets I think we might be able to use a masked vpmovzx and not have to expand this at all. llvm-svn: 352433
* [RuntimeDyld] load all sections with ProcessAllSectionsYonghong Song2019-01-281-0/+19
| | | | | | | | | | | | | | | | | | | | | | | This patch tried to address the following use case. . bcc (https://github.com/iovisor/bcc) utilizes llvm JIT to compile for BTF target. . with -g, .BTF and .BTF.ext sections (BPF debug info) will be generated by LLVM. . .BTF does not have relocations and .BTF.ext has some relocations. . With ProcessAllSections, .BTF.ext is loaded by JIT dynamic linker and is available to application. But .BTF is not loaded. The bcc application needs both .BTF.ext and .BTF for debugging purpose, and .BTF is not loaded. This patch addressed this issue by iterating over all sections and loading any missing sections, after symbol/relocation processing in loadObjectImpl(). Signed-off-by: Yonghong Song <yhs@fb.com> Differential Revision: https://reviews.llvm.org/D55943 llvm-svn: 352432
* [ARM] Deduplicate table generated CC analysis codeReid Kleckner2019-01-286-275/+324
| | | | | | | Create ARMCallingConv.cpp and emit code for calling convention analysis from there. llvm-svn: 352431
* [AArch64] Include AArch64GenCallingConv.inc onceReid Kleckner2019-01-286-129/+171
| | | | | | | | | | | | | | | | | | | | Summary: Avoids duplicating generated static helpers for calling convention analysis. This also means you can modify AArch64CallingConv.td without recompiling the AArch64ISelLowering.cpp monolith, so it provides faster incremental rebuilds. Saves 12K in llc.exe, but adds a new object file, which is large. Reviewers: efriedma, t.p.northover Subscribers: mgorny, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D56948 llvm-svn: 352430
* [GlobalISel][AArch64] Add legalization for G_FLOGJessica Paquette2019-01-283-2/+9
| | | | | | | | | | This adds support for legalizing G_FLOG into a RTLib call. It adds a legalizer test, and updates the existing floating point tests. https://reviews.llvm.org/D57347 llvm-svn: 352429
* AMDGPU: Add DS append/consume intrinsicsMatt Arsenault2019-01-284-17/+94
| | | | | | | | | | | | | | | Since these pass the pointer in m0 unlike other DS instructions, these need to worry about whether the address is uniform or not. This assumes the address is dynamically uniform, and just uses readfirstlane to get a copy into an SGPR. I don't know if these have the same 16-bit add for the addressing mode offset problem on SI or not, but I've just assumed they do. Also includes some misc. changes to avoid test differences between the LDS and GDS versions. llvm-svn: 352422
* [GlobalISel][AArch64] Add instruction selection support for @llvm.log10Jessica Paquette2019-01-283-2/+9
| | | | | | | | | | This adds instruction selection support for @llvm.log10 in AArch64. It teaches GISel to lower it to a library call, updates the relevant tests, and adds a legalizer test for log10. https://reviews.llvm.org/D57341 llvm-svn: 352418
* [AliasSetTracker] Cleanup more comments. [NFCI]Alina Sbirlea2019-01-281-4/+6
| | | | llvm-svn: 352416
* [MC] Do not consider .ifdef/.ifndef as a useScott Linder2019-01-281-2/+2
| | | | | | | | This is allowed by GAS and seems correct. Differential Revision: https://reviews.llvm.org/D55439 llvm-svn: 352414
* [AArch64] Add 'apple-latest' CPU aliasFrancis Visoiu Mistrih2019-01-281-0/+3
| | | | | | | | | | | | | | The 'apple-latest' alias is supposed to provide a CPU that contains the latest Apple processor model supported by LLVM. This is supposed to be used by tools like lldb to provide a target that supports most of the CPU features. For now, this is mapped to Cyclone. Differential Revision: https://reviews.llvm.org/D56384 llvm-svn: 352412
* [GlobalISel] Add ISel support for @llvm.lifetime.start and @llvm.lifetime.endJessica Paquette2019-01-281-6/+27
| | | | | | | | | | | | | | | | | | This adds ISel support for lifetime markers in opt levels above O0. It also updates the arm64-irtranslator test, and updates some AArch64 tests that use them for added coverage. It also adds a testcase taken from the X86 codegen tests which verified a bug caused by lifetime markers + stack colouring in the past. This is intended to make sure that GISel doesn't re-introduce the bug. (This is basically a straight copy from what SelectionDAG does in SelectionDAGBuilder.cpp) https://reviews.llvm.org/D57187 llvm-svn: 352410
* [CodeGen][X86] Expand UADDSAT to NOT+UMIN+ADDNikita Popov2019-01-282-0/+13
| | | | | | | | | Followup to D56636, this time handling the UADDSAT case by expanding uadd.sat(a, b) to umin(a, ~b) + b. Differential Revision: https://reviews.llvm.org/D56869 llvm-svn: 352409
* [CodeExtractor] Add support for the `swifterror` attributeVedant Kumar2019-01-281-2/+15
| | | | | | | When passing a `swifterror` argument or alloca as an input to an extraction region, mark the input parameter `swifterror`. llvm-svn: 352408
* [AliasSetTracker] Cleanup comments. [NFCI]Alina Sbirlea2019-01-281-5/+8
| | | | llvm-svn: 352406
* [GlobalISel][AArch64] Add instruction selection support for G_FCOS and G_FSINJessica Paquette2019-01-283-2/+33
| | | | | | | | | | | | This contains all of the legalizer changes from D57197 necessary to select G_FCOS and G_FSIN. It also updates several existing IR tests in test/CodeGen/AArch64 that verify that we correctly lower the G_FCOS and G_FSIN instructions. https://reviews.llvm.org/D57197 3/3 llvm-svn: 352402
* [GlobalISel][AArch64] Add IRTranslator support for G_FCOS and G_FSINJessica Paquette2019-01-281-0/+10
| | | | | | | | | This adds IRTranslator support for the G_FCOS and G_FSIN generic instructions. https://reviews.llvm.org/D57197 2/3 llvm-svn: 352401
* [AliasSetTracker] Update signature to aliasesPointer [NFCI].Alina Sbirlea2019-01-281-11/+13
| | | | llvm-svn: 352399
* [NFC] TLI query with default(on) behavior wrt DAG combines for fmin/fmax ↵Michael Berg2019-01-281-3/+7
| | | | | | target control llvm-svn: 352396
* [SimpleLoopUnswitch] Early check exit for trivial unswitch with MemorySSA.Alina Sbirlea2019-01-281-0/+4
| | | | | | | | | | | | | | | Summary: If MemorySSA is avaiable, we can skip checking all instructions if block has any Defs. (volatile loads are also Defs). We still need to check all instructions for "canThrow", even if no Defs are found. Reviewers: chandlerc Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits Differential Revision: https://reviews.llvm.org/D57129 llvm-svn: 352393
* [X86][AVX] Remove lowerShuffleByMerging128BitLanes 2-lane restrictionSimon Pilgrim2019-01-281-7/+10
| | | | | | | | First step towards adding support for 64-bit unary "sublane" handling (a bit like lowerShuffleAsRepeatedMaskAndLanePermute). This allows us to add lowerV64I8Shuffle handling. llvm-svn: 352389
* [x86] allow more shuffle splitting to avoid vpermps (PR40434)Sanjay Patel2019-01-281-1/+3
| | | | | | | | | | | | | | | This is tricky to make optimal: sometimes we're better off using a single wider op, but other times it makes more sense to combine a narrow ops to achieve the same result. This solves the case from: https://bugs.llvm.org/show_bug.cgi?id=40434 There's potentially a similar change for vectors with 64-bit elements, but it needs adjustments similar to rL352333 to avoid creating infinite loops. llvm-svn: 352380
* Remove no longer needed Arm specific LICENSE.TXT file.Arnaud A. de Grandmaison2019-01-281-47/+0
| | | | | | | | | As the codebase is now under the Apache 2.0 license with LLVM Exceptions, and all Arm's contributions, past or future, are under that new license, this Arm specific LICENSE.TXT is no longer needed, thus removing it. llvm-svn: 352376
* [mips] Support for +abs2008 attributeAleksandar Beserminji2019-01-287-5/+91
| | | | | | | | | | | | | | | | Instruction abs.[ds] is not generating correct result when working with NaNs for revisions prior mips32r6 and mips64r6. To generate a sequence which always produce a correct result, but also to allow user more control on how his code is compiled, attribute +abs2008 is added, so user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Differential Revision: https://reviews.llvm.org/D35983 llvm-svn: 352370
* [AMDGPU] Add intrinsics for 16 bit interpolationTim Corringham2019-01-286-3/+96
| | | | | | | | | | | | | | | | | | | Summary: Added the intrinsics llvm.amdgcn.interp.p1.f16() and llvm.amdgcn.interp.p2.f16() and related LIT test. The p1 intrinsic generates code appropriate for both 16 and 32 bank LDS. Reviewers: #amdgpu, dstuttard, arsenm, tpr Reviewed By: #amdgpu, arsenm Subscribers: jvesely, mgorny, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46754 llvm-svn: 352357
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-283-2/+70
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* [DebugInfo][DAG] Avoid re-ordering of DBG_VALUEsJeremy Morse2019-01-281-21/+50
| | | | | | | | | | | | | | | | This patch improves the placement of DBG_VALUEs when by SelectionDAG, which as documented in PR40427 can go very wrong. At the core of this is ProcessSourceNode, which assumes the last instruction in a BB is the start of the last processed IR instruction, which isn't always true. Instead, use a helper function to call InstrEmitter::EmitNode, that records before-and-after iterators and determines the first of any new instruction created during emission. This is passed to ProcessSourceNode, which can then make more elightened decisions about ordering for DBG_VALUE placement. Differential revision: https://reviews.llvm.org/D57163 llvm-svn: 352350
* [ARM GlobalISel] Support integer division for Thumb2Diana Picus2019-01-281-19/+21
| | | | | | | | | Support G_SDIV, G_UDIV, G_SREM and G_UREM. The only significant difference between arm and thumb mode is that we need to check a different subtarget feature. llvm-svn: 352346
* [X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types ↵Craig Topper2019-01-283-74/+26
| | | | | | | | for the mask argument. Remove and autoupgrade the old intrinsics llvm-svn: 352343
* [AArch64][GlobalISel] Teach RBS about G_FNEG default mapping.Amara Emerson2019-01-281-0/+1
| | | | llvm-svn: 352340
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