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* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-023-0/+86
| | | | | | | | | | | SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
* Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen2013-04-021-0/+6
| | | | | | | | | | | The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 llvm-svn: 178524
* Add support for 64-bit calling convention.Jakob Stoklund Olesen2013-04-023-11/+115
| | | | | | | | | | | | This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. llvm-svn: 178523
* Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen2013-04-026-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. llvm-svn: 178522
* Fix typo in PPCISelLoweringHal Finkel2013-04-021-1/+1
| | | | | | Thanks to Bill Schmidt for finding this in review of r178480. llvm-svn: 178521
* The divide unit is not pipeline, but it is still buffered.Andrew Trick2013-04-022-4/+4
| | | | | | | | | | | | | | | | | | | | Buffered means a later divide may be executed out-of-order while a prior divide is sitting (buffered) in a reservation station. You can tell it's not pipelined, because operations that use it reserve it for more than one cycle: def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> { let Latency = 25; let ResourceCycles = [1, 10]; } We don't currently distinguish between an unpipeline operation and one that is split into multiple micro-ops requiring the same unit. Except that the later may have NumMicroOps > 1 if they also consume issue/dispatch resources. llvm-svn: 178519
* Target/R600: Fix CMake build to add missing files.NAKAMURA Takumi2013-04-011-0/+3
| | | | llvm-svn: 178508
* Mips direct object exception handling regressionJack Carter2013-04-011-3/+4
| | | | | | | | | | | | | | | | | Revision 177141 caused a regression in all but mips64 little endian. That is because none of the other Mips targets had test cases checking the contents of the .eh_frame section. This patch fixes both the llvm code and adds an assembler test case to include the current 4 flavors. The test cases unfortunately rely on llvm-objdump. A preferable method would be to use a pretty printer output such as what readelf -wf <elf_file> would give. I also changed the name of the test case to correct a typo. llvm-svn: 178506
* R600: Add support for native control flowVincent Lejeune2013-04-015-1/+386
| | | | llvm-svn: 178505
* R600/SI: Share code recording ShaderTypeAttribute between generationsVincent Lejeune2013-04-016-28/+60
| | | | llvm-svn: 178504
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-016-10/+397
| | | | llvm-svn: 178503
* Fix top-comment header and some indentationEli Bendersky2013-04-012-3/+3
| | | | llvm-svn: 178492
* Fix a bad assert in PPCTargetLoweringHal Finkel2013-04-011-2/+2
| | | | llvm-svn: 178489
* Correct assertion conditionShuxin Yang2013-04-011-1/+1
| | | | llvm-svn: 178484
* Merge load/store sequences with adresses: base + index + offsetArnold Schwaighofer2013-04-011-25/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We would also like to merge sequences that involve a variable index like in the example below. int index = *idx++ int i0 = c[index+0]; int i1 = c[index+1]; b[0] = i0; b[1] = i1; By extending the parsing of the base pointer to handle dags that contain a base, index, and offset we can handle examples like the one above. The dag for the code above will look something like: (load (i64 add (i64 copyfromreg %c) (i64 signextend (i8 load %index)))) (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) The code that parses the tree ignores the intermediate sign extensions. However, if there is a sign extension it needs to be on all indexes. (load (i64 add (i64 copyfromreg %c) (i64 signextend (add (i8 load %index) (i8 1)))) vs (load (i64 add (i64 copyfromreg %c) (i64 signextend (i32 add (i32 signextend (i8 load %index)) (i32 1))))) radar://13536387 llvm-svn: 178483
* Add more PPC floating-point conversion instructionsHal Finkel2013-04-017-33/+134
| | | | | | | | | The P7 and A2 have additional floating-point conversion instructions which allow a direct two-instruction sequence (plus load/store) to convert from all combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores, only some combinations were directly available). llvm-svn: 178480
* Use ImmToIdxMap.count in PPCRegisterInfoHal Finkel2013-04-011-2/+1
| | | | | | | Code improvement suggested by Jakob (in review of r178450). No functionality change intended. llvm-svn: 178473
* Add the PPC popcntw instructionHal Finkel2013-04-012-1/+8
| | | | | | | | | The popcntw instruction is available whenever the popcntd instruction is available, and performs a separate popcnt on the lower and upper 32-bits. Ignoring the high-order count, this can be used for the 32-bit input case (saving on the explicit zero extension otherwise required to use popcntd). llvm-svn: 178470
* Add support for vector data types in the LLVM interpreter.Nadav Rotem2013-04-013-3/+182
| | | | | | | Patch by: Veselov, Yuri <Yuri.Veselov@intel.com> llvm-svn: 178469
* Treat PPCISD::STFIWX like the memory opcode that it isHal Finkel2013-04-012-6/+13
| | | | | | | | | | | PPCISD::STFIWX is really a memory opcode, and so it should come after FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create nodes using it. No functionality change intended (although there could be optimization benefits from preserving the MMO information). llvm-svn: 178468
* Remove unused typedef.Duncan Sands2013-04-011-1/+0
| | | | llvm-svn: 178462
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-04-014-41/+85
| | | | | | | | | | | | | Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. llvm-svn: 178460
* X86TTI: Add accurate costs for itofp operations, based on the actual ↵Benjamin Kramer2013-04-011-4/+27
| | | | | | instruction counts. llvm-svn: 178459
* Whitespace cleanupJoe Abbey2013-04-012-2/+2
| | | | llvm-svn: 178454
* R600: Emit native instructions for texVincent Lejeune2013-03-312-115/+197
| | | | llvm-svn: 178452
* There is no longer any need to silence this compiler warning as the warning hasDuncan Sands2013-03-311-1/+1
| | | | | | been turned off globally. llvm-svn: 178451
* Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfoHal Finkel2013-03-312-20/+6
| | | | | | | | | | | ImmToIdxMap should be a DenseMap (not a std::map) because there is no ordering requirement. Also, we don't need a separate list of instructions for noImmForm in eliminateFrameIndex, because this list is essentially the complement of the keys in ImmToIdxMap. No functionality change intended. llvm-svn: 178450
* X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.Benjamin Kramer2013-03-311-0/+1
| | | | | | A vector sext + sitofp is a lot cheaper than 8 scalar conversions. llvm-svn: 178448
* Add the PPC lfiwax instructionHal Finkel2013-03-317-22/+68
| | | | | | | | | This instruction is available on modern PPC64 CPUs, and is now used to improve the SINT_TO_FP lowering (by eliminating the need for the separate sign extension instruction and decreasing the amount of needed stack space). llvm-svn: 178446
* Cleanup PPC(64) i32 -> float/double conversionHal Finkel2013-03-315-42/+9
| | | | | | | | | | | | | | | The existing SINT_TO_FP code for i32 -> float/double conversion was disabled because it relied on broken EXTSW_32/STD_32 instruction definitions. The original intent had been to enable these 64-bit instructions to be used on CPUs that support them even in 32-bit mode. Unfortunately, this form of lying to the infrastructure was buggy (as explained in the FIXME comment) and had therefore been disabled. This re-enables this functionality, using regular DAG nodes, but only when compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead) are removed. llvm-svn: 178438
* DAGCombine: visitXOR can replace a node without returning it, bail out in ↵Benjamin Kramer2013-03-301-3/+3
| | | | | | | | that case. Fixes the crash reported in PR15608. llvm-svn: 178429
* Change '@SECREL' suffix to GAS-compatible '@SECREL32'.Benjamin Kramer2013-03-302-2/+2
| | | | | | | | | | '@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'. With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here). Patch by David Nadlinger! Differential Revision: http://llvm-reviews.chandlerc.com/D429 llvm-svn: 178427
* Put private class into an anonmyous namespace.Benjamin Kramer2013-03-301-0/+2
| | | | llvm-svn: 178420
* [NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.Justin Holewinski2013-03-302-14/+2
| | | | llvm-svn: 178417
* [NVPTX] Add NVVMReflect pass to allow compile-time selection ofJustin Holewinski2013-03-303-0/+201
| | | | | | | | | | | | | | | | specific code paths. This allows us to write code like: if (__nvvm_reflect("FOO")) // Do something else // Do something else and compile into a library, then give "FOO" a value at kernel compile-time so the check becomes a no-op. llvm-svn: 178416
* [NVPTX] Run clang-format on all NVPTX sources.Justin Holewinski2013-03-3031-1956/+2298
| | | | | | | Hopefully this resolves any outstanding style issues and gives us an automated way of ensuring we conform to the style guidelines. llvm-svn: 178415
* Implement XOR reassociation. It is based on following rules:Shuxin Yang2013-03-301-1/+325
| | | | | | | | | | | | | | | rule 1: (x | c1) ^ c2 => (x & ~c1) ^ (c1^c2), only useful when c1=c2 rule 2: (x & c1) ^ (x & c2) = (x & (c1^c2)) rule 3: (x | c1) ^ (x | c2) = (x & c3) ^ c3 where c3 = c1 ^ c2 rule 4: (x | c1) ^ (x & c2) => (x & c3) ^ c1, where c3 = ~c1 ^ c2 It reduces an application's size (in terms of # of instructions) by 8.9%. Reviwed by Pete Cooper. Thanks a lot! rdar://13212115 llvm-svn: 178409
* [mips] Add patterns for DSP indexed load instructions.Akira Hatanaka2013-03-302-13/+42
| | | | llvm-svn: 178408
* [mips] Define reg+imm load/store pattern templates.Akira Hatanaka2013-03-302-16/+18
| | | | llvm-svn: 178407
* [mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka2013-03-303-236/+192
| | | | | | | Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. llvm-svn: 178406
* Remove unused variables.Akira Hatanaka2013-03-301-2/+0
| | | | llvm-svn: 178405
* [mips] Move the code which does dag-combine for multiply-add/sub nodes toAkira Hatanaka2013-03-303-186/+199
| | | | | | | | | derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. llvm-svn: 178404
* [mips] Fix definitions of multiply, multiply-add/sub and divide instructions.Akira Hatanaka2013-03-307-70/+199
| | | | | | | | | The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. llvm-svn: 178403
* [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd.Akira Hatanaka2013-03-301-18/+7
| | | | llvm-svn: 178396
* Fix indentation.Akira Hatanaka2013-03-301-26/+26
| | | | llvm-svn: 178395
* [mips] Add mips-specific nodes which will be used to select multiply and divideAkira Hatanaka2013-03-302-0/+18
| | | | | | instructions. llvm-svn: 178394
* [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function isAkira Hatanaka2013-03-301-0/+9
| | | | | | called in several places in ScheduleDAGRRList.cpp. llvm-svn: 178393
* [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStackAkira Hatanaka2013-03-301-0/+18
| | | | | | to handle accumulator registers. llvm-svn: 178392
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