summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [LoopUnswitch] Fix a simple bug which disables loop unswitch for select ↵Wei Mi2017-08-291-4/+2
| | | | | | | | | | | | statement This is to fix PR34257. rL309059 takes an early return when FindLIVLoopCondition fails to find a loop invariant condition. This is wrong and it will disable loop unswitch for select. The patch fixes the bug. Differential Revision: https://reviews.llvm.org/D36985 llvm-svn: 312045
* [dwarfdump] Pretty print location expressions and location listsReid Kleckner2017-08-296-81/+482
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Based on Fred's patch here: https://reviews.llvm.org/D6771 I can't seem to commandeer the old review, so I'm creating a new one. With that change the locations exrpessions are pretty printed inline in the DIE tree. The output looks like this for debug_loc entries: DW_AT_location [DW_FORM_data4] (0x00000000 0x0000000000000001 - 0x000000000000000b: DW_OP_consts +3 0x000000000000000b - 0x0000000000000012: DW_OP_consts +7 0x0000000000000012 - 0x000000000000001b: DW_OP_reg0 RAX, DW_OP_piece 0x4 0x000000000000001b - 0x0000000000000024: DW_OP_breg5 RDI+0) And like this for debug_loc.dwo entries: DW_AT_location [DW_FORM_sec_offset] (0x00000000 Addr idx 2 (w/ length 190): DW_OP_consts +0, DW_OP_stack_value Addr idx 3 (w/ length 23): DW_OP_reg0 RAX, DW_OP_piece 0x4) Simple locations without ranges are printed inline: DW_AT_location [DW_FORM_block1] (DW_OP_reg4 RSI, DW_OP_piece 0x4, DW_OP_bit_piece 0x20 0x0) The debug_loc(.dwo) dumping in changed accordingly to factor the code. Reviewers: dblaikie, aprantl, friss Subscribers: mgorny, javed.absar, hiraditya, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D37123 llvm-svn: 312042
* AMDGPU: Fix typoMatt Arsenault2017-08-291-2/+3
| | | | llvm-svn: 312040
* [NFC] clang-format llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cppBob Haarman2017-08-291-2/+4
| | | | llvm-svn: 312035
* Reland r311957 [codeview] support more DW_OPs for more complete debug infoBob Haarman2017-08-294-86/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some variables show up in Visual Studio as "optimized out" even in -O0 -Od builds. This change fixes two issues that would cause this to happen. The first issue is that not all DIExpressions we generate were recognized by the CodeView writer. This has been addressed by adding support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second issue is that we had no way to encode DW_OP_deref in CodeView. We get around that by changinge the type we encode in the debug info to be a reference to the type in the source code. This fixes PR34261. The reland adds two extra checks to the original: It checks if the DbgVariableLocation is valid before checking any of its fields, and it only emits ranges with nonzero registers. Reviewers: aprantl, rnk, zturner Reviewed By: rnk Subscribers: mgorny, llvm-commits, aprantl, hiraditya Differential Revision: https://reviews.llvm.org/D36907 llvm-svn: 312034
* [FunctionImport] Avoid unused variable warnings in Release buildsBenjamin Kramer2017-08-291-0/+2
| | | | | | Just skip the entire block in NDEBUG. No functionality change intended. llvm-svn: 312031
* [SimplifyCFG] Fix for PR34219: Preserve alignment after merging conditional ↵Alexey Bataev2017-08-291-5/+30
| | | | | | | | | | | | | | | | | | stores. Summary: If SimplifyCFG pass is able to merge conditional stores into single one, it loses the alignment. This may lead to incorrect codegen. Patch sets the alignment of the new instruction if it is set in the original one. Reviewers: jmolloy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36841 llvm-svn: 312030
* [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzerMatt Morehouse2017-08-291-9/+21
| | | | | | | | | | | | | | | | | | Summary: - Don't sanitize __sancov_lowest_stack. - Don't instrument leaf functions. - Add CoverageStackDepth to Fuzzer and FuzzerNoLink. - Disable stack depth tracking on Mac. Reviewers: vitalybuka, kcc, george.karpenkov Reviewed By: kcc Subscribers: kubamracek, cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37156 llvm-svn: 312026
* [InstCombine] Support vector splats in transformZExtICmpCraig Topper2017-08-291-7/+7
| | | | | | | | | | This patch adds splat support to transformZExtICmp. The test cases are vector versions of tests that failed when commenting out parts of the existing scalar code. One test didn't vectorize optimize properly due to another bug so a TODO has been added. Differential Revision: https://reviews.llvm.org/D37253 llvm-svn: 312023
* [DAG] Bound loop dependence check in merge optimization.Hans Wennborg2017-08-291-5/+17
| | | | | | | | | | | | | The loop dependence check looks for dependencies between store merge candidates not captured by the chain sub-DAG doing a check of predecessors which may be very large. Conservatively bound number of nodes checked for compilation time. (Resolves PR34326). Landing on behalf of Nirav Dave to unblock the 5.0.0 release. Differential Revision: https://reviews.llvm.org/D37220 llvm-svn: 312022
* [ThinLTO] Clean up stale alias import handlingTeresa Johnson2017-08-291-30/+2
| | | | | | | | | | | | | | | | Summary: Remove some code that was no longer needed. The first FIXME is stale since we long ago started using the index to drive importing, rather than doing force importing based on linkage type. And now with r309278, we no longer import any aliases. Reviewers: dblaikie Subscribers: inglorion, llvm-commits Differential Revision: https://reviews.llvm.org/D37266 llvm-svn: 312019
* [PGO] Fixed non-determinism with DenseSet storing function importing info.Ana Pazos2017-08-291-2/+7
| | | | | | | | | | | | | | | | | | | | Summary: r296498 introduced a DenseSet to store function importing info. Using this container causes a test failure in test/Transform/SampleProfile/import.ll when in Reverse Iteration mode. This patch orders IDs before iterating through this container. Reviewers: danielcdh, mgrang Reviewed By: danielcdh Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37246 llvm-svn: 312012
* [X86] Fix copy pasto from r311841. Call getOnesVector instead of getZeroVector.Craig Topper2017-08-291-1/+1
| | | | llvm-svn: 312006
* Add null check for promoted direct callDehao Chen2017-08-291-2/+2
| | | | | | | | | | | | | | Summary: We originally assume that in pgo-icp, the promoted direct call will never be null after strip point casts. However, stripPointerCasts is so smart that it could possibly return the value of the function call if it knows that the return value is always an argument. In this case, the returned value cannot cast to Instruction. In this patch, null check is added to ensure null pointer will not be accessed. Reviewers: tejohnson, xur, davidxl, djasper Reviewed By: tejohnson Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D37252 llvm-svn: 312005
* [Instruction] add moveAfter() convenience function; NFCISanjay Patel2017-08-294-16/+10
| | | | | | | | | As suggested in D37121, here's a wrapper for removeFromParent() + insertAfter(), but implemented using moveBefore() for symmetry/efficiency. Differential Revision: https://reviews.llvm.org/D37239 llvm-svn: 312001
* [ARM] - Tidy-up ARMAsmPrinter.cppJaved Absar2017-08-291-10/+8
| | | | | | | | | Change to range-loop where missing. Reviwewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37199 llvm-svn: 311993
* [ARM] GlobalISel: Select globals in PIC modeDiana Picus2017-08-294-7/+37
| | | | | | | | | | | | | | Support the selection of G_GLOBAL_VALUE in the PIC relocation model. For simplicity we use the same pseudoinstructions for both Darwin and ELF: (MOV|LDRLIT)_ga_pcrel(_ldr). This is new for ELF, so it requires a small update to the ARM pseudo expansion pass to make sure it adds the correct constant pool modifier and add-current-address in the case of ELF. Differential Revision: https://reviews.llvm.org/D36507 llvm-svn: 311992
* Revert "The current version of LLVM X86 disassembler incorrectly interprets ↵Eric Christopher2017-08-292-71/+17
| | | | | | | | some possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs." temporarily while some regressions are addressed. This reverts commit r311882. llvm-svn: 311987
* [LSR] Fix Shadow IV in case of integer overflowMax Kazantsev2017-08-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | When LSR processes code like int accumulator = 0; for (int i = 0; i < N; i++) { accummulator += i; use((double) accummulator); } It may decide to replace integer `accumulator` with a double Shadow IV to get rid of casts. The problem with that is that the `accumulator`'s value may overflow. Starting from this moment, the behavior of integer and double accumulators will differ. This patch strenghtens up the conditions of Shadow IV mechanism applicability. We only allow it for IVs that are proved to be `AddRec`s with `nsw`/`nuw` flag. Differential Revision: https://reviews.llvm.org/D37209 llvm-svn: 311986
* Mark Knights Landing as having slow two memory operand instructionsCraig Topper2017-08-296-20/+19
| | | | | | | | | | | | | | | | Summary: Knights Landing, because it is Atom derived, has slow two memory operand instructions. Mark the Knights Landing CPU model accordingly. Patch by David Zarzycki. Reviewers: craig.topper Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37224 llvm-svn: 311979
* Revert "[codeview] support more DW_OPs for more complete debug info"Bob Haarman2017-08-294-192/+86
| | | | | | This reverts commit e160912f53f047bc97e572add179e08e33f4df48. llvm-svn: 311977
* Revert "[codeview] don't try to emit variable locations without registers"Bob Haarman2017-08-291-1/+1
| | | | | | This reverts commit a256fbcacf448ee793d23552c46ed2971bf9eff5. llvm-svn: 311976
* [codeview] don't try to emit variable locations without registersBob Haarman2017-08-291-1/+1
| | | | | | | This fixes a problem introduced 311957, where the compiler would crash with "fatal error: error in backend: unknown codeview register". llvm-svn: 311969
* [InstCombine] Teach foldSelectICmpAndOr to handle vector splatsCraig Topper2017-08-291-6/+8
| | | | | | | | This was pretty close to working already. While I was here I went ahead and passed the ICmpInst pointer from the caller instead of doing a dyn_cast that can never fail. Differential Revision: https://reviews.llvm.org/D37237 llvm-svn: 311960
* [sanitizer-coverage] Mark the guard and 8-bit counter arrays as usedJustin Bogner2017-08-291-7/+14
| | | | | | | | | | | | | | In r311742 we marked the PCs array as used so it wouldn't be dead stripped, but left the guard and 8-bit counters arrays alone since these are referenced by the coverage instrumentation. This doesn't quite work if we want the indices of the PCs array to match the other arrays though, since elements can still end up being dead and disappear. Instead, we mark all three of these arrays as used so that they'll be consistent with one another. llvm-svn: 311959
* Revert "Revert r311552: [Bash-autocompletion] Add support for static ↵Yuka Takahashi2017-08-291-6/+19
| | | | | | | | | | | analyzer flags" This reverts commit 7c46b80c022e18d43c1fdafb117b0c409c5a6d1e. r311552 broke lld buildbot because I've changed OptionInfos type from ArrayRef to vector. However the bug is fixed, so I'll commit this again. llvm-svn: 311958
* [codeview] support more DW_OPs for more complete debug infoBob Haarman2017-08-294-86/+192
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Some variables show up in Visual Studio as "optimized out" even in -O0 -Od builds. This change fixes two issues that would cause this to happen. The first issue is that not all DIExpressions we generate were recognized by the CodeView writer. This has been addressed by adding support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second issue is that we had no way to encode DW_OP_deref in CodeView. We get around that by changinge the type we encode in the debug info to be a reference to the type in the source code. This fixes PR34261. Reviewers: aprantl, rnk, zturner Reviewed By: rnk Subscribers: mgorny, llvm-commits, aprantl, hiraditya Differential Revision: https://reviews.llvm.org/D36907 llvm-svn: 311957
* [sanitizer-coverage] Return the array from CreatePCArray. NFCJustin Bogner2017-08-281-9/+12
| | | | | | | | | | | Be more consistent with CreateFunctionLocalArrayInSection in the API of CreatePCArray, and assign the member variable in the caller like we do for the guard and 8-bit counter arrays. This also tweaks the order of method declarations to match the order of definitions in the file. llvm-svn: 311955
* [sanitizer-coverage] Clean up trailing whitespace. NFCJustin Bogner2017-08-281-6/+6
| | | | llvm-svn: 311954
* Fix a logic error in DwarfExpression::addMachineReg()Adrian Prantl2017-08-281-4/+3
| | | | | | | | | This fixes PR34323 and thus splitting undescribable registers into smaller, describable sub-registers. https://bugs.llvm.org/show_bug.cgi?id=34323 llvm-svn: 311951
* Remove an unnecessary const_cast.Adam Nemet2017-08-281-1/+2
| | | | | | I think that this is dating back to when emit used to take a const reference. llvm-svn: 311948
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-08-281-13/+34
| | | | | | | | Add new predicate to more accurately model the scheduling around branches and function calls and of loads and stores of pairs and integer multiplications. llvm-svn: 311944
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-08-283-46/+97
| | | | | | | | | Add new predicate to more accurately model the cost of arithmetic and logical operations shifted left. Differential revision: https://reviews.llvm.org/D37151 llvm-svn: 311943
* Define NetBSD/amd64 ASAN Shadow OffsetKamil Rytarowski2017-08-281-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Catch up after compiler-rt changes and define kNetBSD_ShadowOffset64 as (1ULL << 46). Sponsored by <The NetBSD Foundation> Reviewers: kcc, joerg, filcab, vitalybuka, eugenis Reviewed By: eugenis Subscribers: llvm-commits, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D37234 llvm-svn: 311941
* [InstCombine] Teach select01 helper of foldSelectIntoOp to handle vector splatsCraig Topper2017-08-281-7/+6
| | | | | | | | We were handling some vectors in foldSelectIntoOp, but not if the operand of the bin op was any kind of vector constant. This patch fixes it to treat vector splats the same as scalars. Differential Revision: https://reviews.llvm.org/D37232 llvm-svn: 311940
* [AArch64][Falkor] Avoid generating STRQro* instructionsGeoff Berry2017-08-284-10/+25
| | | | | | | | | | | | | | | Summary: STRQro* instructions are slower than the alternative ADD/STRQui expanded instructions on Falkor, so avoid generating them unless we're optimizing for code size. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37020 llvm-svn: 311931
* [LoopUnroll] Properly update loop structure in case of successful peeling.Davide Italiano2017-08-281-2/+13
| | | | | | | | | | | When peeling kicks in, it updates the loop preheader. Later, a successful full unroll of the loop needs to update a PHI which i-th argument comes from the loop preheader, so it'd better look at the correct block. Fixes PR33437. Differential Revision: https://reviews.llvm.org/D37153 llvm-svn: 311922
* Fix ARMv4 supportJoerg Sonnenberger2017-08-289-10/+35
| | | | | | | | | | | | | | | | | | ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
* [LoopUnroll] Add a cl::opt to force peeling, for testing purposes.Davide Italiano2017-08-281-0/+6
| | | | | | Will be used to test the patch proposed in D37153. llvm-svn: 311915
* [ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing.Geoff Berry2017-08-281-30/+19
| | | | | | | | | | | | | | | | | | | | | | Summary: ARMLoadStoreOpt::FixInvalidRegPairOp() was only checking if one of the load destination registers to be split overlapped with the base register if the base register was marked as killed. Since kill flags may not always be present, this can lead to incorrect code. This bug was exposed by my MachineCopyPropagation change D30751 breaking the sanitizer-x86_64-linux-android buildbot. Also clean up some dead code and add an assert that a register offset is never encountered by this code, since it does not handle them correctly. Reviewers: MatzeB, qcolombet, t.p.northover Subscribers: aemerson, javed.absar, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37164 llvm-svn: 311907
* Create PHI node for the return value only when the return value has uses.Taewook Oh2017-08-281-0/+3
| | | | | | | | | | | | | | | | | | | Summary: Currently, a phi node is created in the normal destination to unify the return values from promoted calls and the original indirect call. This patch makes this phi node to be created only when the return value has uses. This patch is necessary to generate valid code, as compiler crashes with the attached test case without this patch. Without this patch, an illegal phi node that has no incoming value from `entry`/`catch` is created in `cleanup` block. I think existing implementation is good as far as there is at least one use of the original indirect call. `insertCallRetPHI` creates a new phi node in the normal destination block only when the original indirect call dominates its use and the normal destination block. Otherwise, `fixupPHINodeForNormalDest` will handle the unification of return values naturally without creating a new phi node. However, if there's no use, `insertCallRetPHI` still creates a new phi node even when the original indirect call does not dominate the normal destination block, because `getCallRetPHINode` returns false. Reviewers: xur, davidxl, danielcdh Reviewed By: xur Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37176 llvm-svn: 311906
* [CodeView] Don't output S_UDT symbols for forward decls.Zachary Turner2017-08-282-16/+35
| | | | | | | | | | | | | | | | | | | | | | S_UDT symbols are the debugger's "index" for all the structs, typedefs, classes, and enums in a program. If any of those structs/classes don't have a complete declaration, or if there is a typedef to something that doesn't have a complete definition, then emitting the S_UDT is unhelpful because it doesn't give the debugger enough information to do anything useful. On the other hand, it results in a huge size blow-up in the resulting PDB, which is exacerbated by an order of magnitude when linking with /DEBUG:FASTLINK. With this patch, we drop S_UDT records for types that refer either directly or indirectly (e.g. through a typedef, pointer, etc) to a class/struct/union/enum without a complete definition. This brings us about 50% of the way towards parity with /DEBUG:FASTLINK PDBs generated from cl-compiled object files. Differential Revision: https://reviews.llvm.org/D37162 llvm-svn: 311904
* [Power9] Add new instructions for floating point status and control registers.Stefan Pintilie2017-08-282-0/+91
| | | | | | | | | Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl Differential Revision: https://reviews.llvm.org/D37167 llvm-svn: 311903
* [InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the ↵Craig Topper2017-08-281-1/+1
| | | | | | | | | | NSW flag when handling Add in SimplifyDemandedUseBits. This is a typo from r311789. This should fix PR34349. llvm-svn: 311902
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-283-0/+55
| | | | | | | Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
* [AMDGPU] Fix regression in AMDGPULibCalls allowing native for doublesStanislav Mekhanoshin2017-08-281-3/+3
| | | | | | | | | | | | | Under -cl-fast-relaxed-math we could use native_sqrt, but f64 was allowed to produce HSAIL's nsqrt instruction. HSAIL is not here and we stick with non-existing native_sqrt(double) as a result. Add check for f64 to not return native functions and also remove handling of f64 case for fold_sqrt. Differential Revision: https://reviews.llvm.org/D37223 llvm-svn: 311900
* [AMDGPU] computeKnownBitsForTargetNode for 24 bit mulStanislav Mekhanoshin2017-08-281-1/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D37168 llvm-svn: 311896
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-286-139/+141
| | | | llvm-svn: 311895
* [Hexagon] Move pre-RA DAG mutations to scheduler constructorKrzysztof Parzyszek2017-08-283-15/+15
| | | | llvm-svn: 311894
* [X86] Make 128/256-bit extract_subvector Legal instead of Custom. Move ↵Craig Topper2017-08-281-32/+25
| | | | | | | | | | | | combining with BUILD_VECTOR from Legalization to DAG combine EXTRACT_SUBVECTOR was marked Custom solely so we could combine it with BUILD_VECTOR operations to create smaller BUILD_VECTORS during Legalization. But that sort of combining should really be done by the DAG combiner. This patch adds the last piece of needed supported DAG combine to handle this. Once that's done we can make the EXTRACT_SUBVECTOR operations Legal. Differential Revision: https://reviews.llvm.org/D37197 llvm-svn: 311893
OpenPOWER on IntegriCloud