summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* InstCombineAndOrXor.cpp: Escape bracket in doxygen description. ↵NAKAMURA Takumi2012-11-151-1/+1
| | | | | | [-Wdocumentation] llvm-svn: 168013
* Add doInitialization and doFinalization methods to ModulePass's, to allow ↵Owen Anderson2012-11-152-0/+73
| | | | | | | | them to be re-initialized and reused on multiple Module's. Patch by Pedro Artigas. llvm-svn: 168008
* Remove unneeded #includes.Jakub Staszak2012-11-141-3/+0
| | | | llvm-svn: 168006
* NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]NAKAMURA Takumi2012-11-141-6/+4
| | | | llvm-svn: 168001
* Use reserve() to avoid vector reallocation.Jakub Staszak2012-11-141-0/+1
| | | | llvm-svn: 167991
* Remove the CellSPU port.Eric Christopher2012-11-1453-14685/+1
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* Fix invalid asserts, use llvm_unreachable instead.Jakub Staszak2012-11-141-3/+3
| | | | llvm-svn: 167976
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-144-233/+187
| | | | llvm-svn: 167974
* canJoinPhys method doesn't modify CoalescerPair. Make it const.Jakub Staszak2012-11-141-2/+2
| | | | llvm-svn: 167972
* Remove dead code.Chad Rosier2012-11-141-13/+0
| | | | llvm-svn: 167970
* Remove DOS line endings.Jakub Staszak2012-11-141-76/+76
| | | | llvm-svn: 167968
* X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer2012-11-141-7/+2
| | | | | | | | | | | | | | | | | | bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. llvm-svn: 167967
* Replace std::vector -> SmallVector in BBVectorizeHal Finkel2012-11-141-4/+4
| | | | | | | | | For now, this uses 8 on-stack elements. I'll need to do some profiling to see if this is the best number. Pointed out by Jakob in post-commit review. llvm-svn: 167966
* The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem2012-11-141-6/+7
| | | | | | | | | | | is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 llvm-svn: 167963
* [NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski2012-11-142-2/+61
| | | | | | | | | Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 llvm-svn: 167948
* Fix really stupid ARM EHABI info generation bug: we should not emitAnton Korobeynikov2012-11-141-11/+14
| | | | | | | eh table and handler data if there are no landing pads in the function. Patch by Logan Chien with some cleanups from me. llvm-svn: 167945
* Fix the largest offender of determinism in BBVectorizeHal Finkel2012-11-141-6/+6
| | | | | | | | | | | | | | | | | Iterating over the children of each node in the potential vectorization plan must happen in a deterministic order (because it affects which children are erased when two children conflict). There was no need for this data structure to be a map in the first place, so replacing it with a vector is a small change. I believe that this was the last remaining instance if iterating over the elements of a Dense* container where the iteration order could matter. There are some remaining iterations over std::*map containers where the order might matter, but so long as the Value* for instructions in a block increase with the order of the instructions in the block (or decrease) monotonically, then this will appear to be deterministic. llvm-svn: 167942
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-142-9/+42
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
* s/assert/llvm_unreachable/Matt Beaumont-Gay2012-11-141-3/+4
| | | | llvm-svn: 167936
* [TSan] fix indentationAlexey Samsonov2012-11-141-1/+1
| | | | llvm-svn: 167928
* Emit relocations from .debug_aranges to .debug_info for asm filesAlexey Samsonov2012-11-141-9/+19
| | | | llvm-svn: 167926
* Revert some redundant parts of r142605.Patrik Hägglund2012-11-141-21/+15
| | | | | | | | | This seems like redundant leftovers from r142288 - exposing TargetData::parseSpecifier to LLParser - which got reverted. Removes redunant td != NULL checks in parseSpecifier, and simplifies the interface to parseSpecifier and init. llvm-svn: 167924
* Set FFLOOR of vectors to expand to keep intruction selection from failing.Craig Topper2012-11-141-0/+1
| | | | llvm-svn: 167922
* Factor out an overly replicated typecast. No functional change.Craig Topper2012-11-141-65/+66
| | | | llvm-svn: 167916
* Set FFLOOR for vectors to expand on CellSPU to keep instruction selection ↵Craig Topper2012-11-141-1/+2
| | | | | | from failing on llvm.floor of a vector. llvm-svn: 167914
* Add newlines to end of debug messages.Craig Topper2012-11-141-6/+6
| | | | llvm-svn: 167913
* Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333.Rafael Espindola2012-11-141-1/+12
| | | | llvm-svn: 167912
* Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov2012-11-148-65/+77
| | | | | | | | Do some cleanup of the code while here. Inspired by patch by Logan Chien! llvm-svn: 167904
* Fix broken asserts. Also, spell 'indices' correctly.Matt Beaumont-Gay2012-11-141-6/+6
| | | | llvm-svn: 167894
* [Object] Fix endianess bug by refactoring Archive::Symbol::getMember.Michael J. Spencer2012-11-141-18/+32
| | | | llvm-svn: 167893
* use the getSplat API. Patch by Paul Redmond.Nadav Rotem2012-11-141-7/+1
| | | | llvm-svn: 167892
* Revert "Use the 'count' attribute instead of the 'upper_bound' attribute."Eric Christopher2012-11-132-6/+3
| | | | | | | | temporarily as it is breaking the gdb bots. This reverts commit r167806/e7ff4c14b157746b3e0228d2dce9f70712d1c126. llvm-svn: 167886
* Revert -join-splitedges to a boolean cmd line option.Andrew Trick2012-11-131-3/+2
| | | | llvm-svn: 167880
* The MachineScheduler does not currently require JoinSplitEdges.Andrew Trick2012-11-131-4/+4
| | | | | | | This option will eventually either be enabled unconditionally or replaced by a more general live range splitting optimization. llvm-svn: 167879
* [MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer2012-11-131-2/+13
| | | | llvm-svn: 167877
* Add (some) PowerPC TLS relocation types to ELF.h andUlrich Weigand2012-11-131-2/+18
| | | | | | | generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. llvm-svn: 167864
* Fix wrong PowerPC instruction opcodes for:Ulrich Weigand2012-11-132-4/+4
| | | | | | | | - lwaux - lhzux - stbu llvm-svn: 167863
* Fix wrong PowerPC instruction encodings due toUlrich Weigand2012-11-132-10/+10
| | | | | | | | | operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) llvm-svn: 167862
* Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand2012-11-133-14/+15
| | | | | | by using a new instruction format BForm_1. llvm-svn: 167861
* Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand2012-11-133-2/+22
| | | | | | using a new instruction format AForm_4. llvm-svn: 167860
* X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren2012-11-131-0/+12
| | | | | | | | | | | chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 llvm-svn: 167859
* Do not consider a machine instruction that uses and defines the sameUlrich Weigand2012-11-131-16/+44
| | | | | | | | | | physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. llvm-svn: 167855
* Adding changes to support GNU style archive library readingShankar Easwaran2012-11-131-26/+118
| | | | llvm-svn: 167853
* Fix -join-splitedges: my previous "cleanup" broke it.Andrew Trick2012-11-131-1/+1
| | | | | | | Working on reducing unit tests. This won't be enabled unless a subtarget enables misched. llvm-svn: 167851
* Revert 167755/167760. We don't want to emit crash diagnostics on ↵Chad Rosier2012-11-131-4/+1
| | | | | | command-line syntax errors. llvm-svn: 167849
* Codegen support for arbitrary vector getelementptrs.Duncan Sands2012-11-131-3/+3
| | | | llvm-svn: 167830
* Relax the restrictions on vector of pointer types, and vector getelementptr.Duncan Sands2012-11-136-57/+81
| | | | | | | | | | | | | | | Previously in a vector of pointers, the pointer couldn't be any pointer type, it had to be a pointer to an integer or floating point type. This is a hassle for dragonegg because the GCC vectorizer happily produces vectors of pointers where the pointer is a pointer to a struct or whatever. Vector getelementptr was restricted to just one index, but now that vectors of pointers can have any pointer type it is more natural to allow arbitrary vector getelementptrs. There is however the issue of struct GEPs, where if each lane chose different struct fields then from that point on each lane will be working down into unrelated types. This seems like too much pain for too little gain, so when you have a vector struct index all the elements are required to be the same. llvm-svn: 167828
* DependenceAnalysis: Print all dependency pairs when dumping. Update all ↵Benjamin Kramer2012-11-131-8/+5
| | | | | | | | testcases. Part of a patch by Preston Briggs. llvm-svn: 167827
* misched: Allow subtargets to enable misched and dependent options.Andrew Trick2012-11-135-14/+47
| | | | | | | | | | | | This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. llvm-svn: 167826
* Added RegisterCoalescer support for joining global copies first.Andrew Trick2012-11-131-20/+80
| | | | | | | | | | | | This adds the -join-globalcopies option which can be enabled by default once misched is also enabled. Ideally, the register coalescer would be able to split local live ranges in a way that produces copies that can be easily resolved by the scheduler. Until then, this heuristic should be good enough to at least allow the scheduler to run after coalescing. llvm-svn: 167825
OpenPOWER on IntegriCloud