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* [OptDiag] Take the IR Value as a const pointerAdam Nemet2016-07-201-2/+3
| | | | | | | | This helps because LoopAccessReport is passed around as a const reference and we derive the basic block passed as the Value parameter from the instruction in LoopAccessReport. llvm-svn: 276191
* [OptDiag] Wrap a long lineAdam Nemet2016-07-201-1/+2
| | | | llvm-svn: 276190
* [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.Artem Belevich2016-07-204-21/+21
| | | | | | | | After r276153 the pass applies to both kernels and regular functions. Differential Revision: https://reviews.llvm.org/D22583 llvm-svn: 276189
* GlobalISel: implement Legalization querying framework.Tim Northover2016-07-202-0/+129
| | | | | | | This adds an (incomplete, inefficient) framework for deciding what to do with some operation on a given type. llvm-svn: 276184
* [AArch64][FastISel] Select -O0 legal cmpxchg.Ahmed Bougacha2016-07-201-0/+55
| | | | | | | | | | | At -O0, cmpxchg survives AtomicExpand: it's mostly straightforward to select it in fast-isel, and let the pseudo be expanded later. extractvalues on the result are the tricky part: the generic logic only works for legal types (and it would be painful to make it support illegal types), so we can only support i32/i64 cmpxchg. llvm-svn: 276183
* [AArch64][FastISel] Select atomic stores into STLR.Ahmed Bougacha2016-07-201-3/+40
| | | | llvm-svn: 276182
* [GVNHoist] Don't hoist PHI nodesDavid Majnemer2016-07-201-4/+8
| | | | | | | | | We hoisted PHIs without respecting their special insertion point in the block, leading to verfier errors. This fixes PR28626. llvm-svn: 276181
* [SCCP] Zap multiple return values.Davide Italiano2016-07-201-9/+41
| | | | | | | | | We can replace the return values with undef if we replaced all the call uses with a constant/undef. Differential Revision: https://reviews.llvm.org/D22336 llvm-svn: 276174
* [LSV] Don't move stores across may-load instrs, and loosen restrictions on ↵Justin Lebar2016-07-201-2/+18
| | | | | | | | | | | | | | | | | | | | | moving loads. Summary: Previously we wouldn't move loads/stores across instructions that had side-effects, where that was defined as may-write or may-throw. But this is not sufficiently restrictive: Stores can't safely be moved across instructions that may load. This patch also adds a DEBUG check that all instructions in our chain are either loads or stores. Reviewers: asbirlea Subscribers: llvm-commits, jholewinski, arsenm, mzolotukhin Differential Revision: https://reviews.llvm.org/D22547 llvm-svn: 276171
* [LSV] Vectorize up to side-effecting instructions.Justin Lebar2016-07-201-7/+3
| | | | | | | | | | | | | | | Summary: Previously if we had a chain that contained a side-effecting instruction, we wouldn't vectorize it at all. Now we'll vectorize everything that comes before the side-effecting instruction. Reviewers: asbirlea Subscribers: arsenm, jholewinski, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22536 llvm-svn: 276170
* [MSSA] Add an overload for getClobberingMemoryAccess.George Burgess IV2016-07-201-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A seemingly common use for the walker's getClobberingMemoryAccess function is: ``` MemoryAccess *getClobber(MemorySSAWalker *W, MemoryUseOrDef *MUD) { const Instruction *I = MUD->getMemoryInst(); return W->getClobberingMemoryAccess(I); } ``` Which is kind of redundant, since walkers will ultimately query MSSA to find out which MemoryAccess `I` maps to (...which is always `MUD`). So, this patch adds an overload of getClobberingMemoryAccess that accepts MemoryAccesses directly. As a result, the Instruction overload of getClobberingMemoryAccess becomes a lightweight wrapper around our new overload. Additionally, this patch un`virtual`izes the Instruction overload of getClobberingMemoryAccess, since there doesn't seem to be a walker that benefits from that being virtual, and I can't think of how else one would implement it. Happy to make it virtual again if we would benefit from doing so. llvm-svn: 276169
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-2012-92/+156
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* Properly ifdef the use of cpuid.Alina Sbirlea2016-07-201-1/+6
| | | | llvm-svn: 276156
* [NVPTX] deal with all aggregate return types.Artem Belevich2016-07-201-6/+6
| | | | | | | | Fixes a crash in llvm_unreachable when a function has array return type. Differential Revision: https://reviews.llvm.org/D22524 llvm-svn: 276154
* [NVPTX] Improve lowering of byval args of device functions.Artem Belevich2016-07-203-32/+45
| | | | | | | | | | | | Avoid unnecessary spills of byval arguments of device functions to local space on SASS level and subsequent pointer conversion to generic address space that follows. Instead, make a local copy in IR, provide a way to access arguments directly, and let LLVM optimize the copy away when possible. Differential Review: https://reviews.llvm.org/D21421 llvm-svn: 276153
* [cpu-detection] Cleanup of Host.cpp.Alina Sbirlea2016-07-201-46/+48
| | | | | | | | | | | | | | Summary: Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model. x86 methods are still returning a bool. Reviewers: llvm-commits, echristo, craig.topper, sanjoy Subscribers: mehdi_amini Differential Revision: https://reviews.llvm.org/D22480 llvm-svn: 276149
* move decomposeBitTestICmp() to Transforms/Utils; NFCSanjay Patel2016-07-202-47/+44
| | | | | | | | As noted in https://reviews.llvm.org/D22537 , we can use this functionality in visitSelectInstWithICmp() and InstSimplify, but currently we have duplicated code. llvm-svn: 276140
* Use ValueOffsetPair to enhance value reuse during SCEV expansion.Wei Mi2016-07-202-33/+80
| | | | | | | | | | | | | | | | | | | | | | | In D12090, the ExprValueMap was added to reuse existing value during SCEV expansion. However, const folding and sext/zext distribution can make the reuse still difficult. A simplified case is: suppose we know S1 expands to V1 in ExprValueMap, and S1 = S2 + C_a S3 = S2 + C_b where C_a and C_b are different SCEVConstants. Then we'd like to expand S3 as V1 - C_a + C_b instead of expanding S2 literally. It is helpful when S2 is a complex SCEV expr and S2 has no entry in ExprValueMap, which is usually caused by the fact that S3 is generated from S1 after const folding. In order to do that, we represent ExprValueMap as a mapping from SCEV to ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a} into the ExprValueMap when we create SCEV for V1. When S3 is expanded, it will first expand S2 to V1 - C_a because of S2->{V1, C_a} in the map, then expand S3 to V1 - C_a + C_b. Differential Revision: https://reviews.llvm.org/D21313 llvm-svn: 276136
* fix documentation comments; NFCSanjay Patel2016-07-201-32/+0
| | | | llvm-svn: 276135
* AMDGPU: Fix bug causing crash due to invalid opencl version metadata.Yaxun Liu2016-07-201-9/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D22526 llvm-svn: 276119
* Revert "[InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))"Benjamin Kramer2016-07-201-8/+2
| | | | | | | | Makes InstCombine infloop when compiling v8. This reverts commit r275989 and r276105. llvm-svn: 276106
* [X86][SSE] Add cost model values for CTPOP of vectorsSimon Pilgrim2016-07-202-4/+29
| | | | | | | | This patch adds costs for the vectorized implementations of CTPOP, the default values were seriously underestimating the cost of these and was encouraging vectorization on targets where serialized use of POPCNT would be much better. Differential Revision: https://reviews.llvm.org/D22456 llvm-svn: 276104
* [ARM] Skip inline asm memory operands in DAGToDAGISelDiana Picus2016-07-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | Retry r275776 (no changes, we suspect the issue was with another commit). The current logic for handling inline asm operands in DAGToDAGISel interprets the operands by looking for constants, which should represent the flags describing the kind of operand we're dealing with (immediate, memory, register def etc). The operands representing actual data are skipped only if they are non-const, with the exception of immediate operands which are skipped explicitly when a flag describing an immediate is found. The oversight is that memory operands may be const too (e.g. for device drivers reading a fixed address), so we should explicitly skip the operand following a flag describing a memory operand. If we don't, we risk interpreting that constant as a flag, which is definitely not intended. Fixes PR26038 Differential Revision: https://reviews.llvm.org/D22103 llvm-svn: 276101
* [AVX512] Add a missing NoVLX to give priority to the AVX512 version of the ↵Craig Topper2016-07-201-1/+1
| | | | | | pattern. llvm-svn: 276088
* [X86] Use 'HasAVX1Only' to properly give priority to the AVX2 version ↵Craig Topper2016-07-201-1/+1
| | | | | | without relying on file ordering. llvm-svn: 276087
* [X86] Create some multiclasses to reduce the repeated patterns for ↵Craig Topper2016-07-201-171/+43
| | | | | | VEXTRACT(F/I)128/VINSERT(I/F)128. NFC llvm-svn: 276086
* [X86] Create some wrapper multiclasses to create AVX and SSE shift ↵Craig Topper2016-07-201-172/+90
| | | | | | instructions with less repeated code. NFC llvm-svn: 276085
* Revert "Disable this-return argument forwarding on ARM/AArch64"David Majnemer2016-07-202-16/+2
| | | | | | | | | Inference of the 'returned' attribute was fixed in r276008, lets try turning the backend support back on. This reverts commit r275677. llvm-svn: 276081
* [LV] Add hotness attribute to missed-optimization remarksAdam Nemet2016-07-201-11/+17
| | | | | | | The new OptimizationRemarkEmitter analysis pass is hooked up to both new and old PM passes. llvm-svn: 276080
* Revert "Revert r275883 and r275891. They seem to cause PR28608."Michael Zolotukhin2016-07-202-15/+69
| | | | | | | This reverts commit r276064, and thus reapplies r275891 and r275883 with a fix for PR28608. llvm-svn: 276077
* [LSV] Don't assume that loads/stores appear in address order in the BB.Justin Lebar2016-07-201-20/+40
| | | | | | | | | | | | | | | | Summary: getVectorizablePrefix previously didn't work properly in the face of aliasing loads/stores. It unwittingly assumed that the loads/stores appeared in the BB in address order. If they didn't, it would do the wrong thing. Reviewers: asbirlea, tstellarAMD Subscribers: arsenm, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D22535 llvm-svn: 276072
* Revert "RegScavenging: Add scavengeRegisterBackwards()"Matthias Braun2016-07-202-240/+108
| | | | | | | | | Reverting this commit for now as it seems to be causing failures on test-suite tests on the clang-ppc64le-linux-lnt bot. This reverts commit r276044. llvm-svn: 276068
* Codegen: Tail Duplication: Only duplicate into layout pred if it is a CFG Pred.Kyle Butt2016-07-201-0/+2
| | | | | | | | | Add a check that the layout predecessor of a block is an actual CFG predecssor of the block as well. No current code fails this check, but upcoming patches can trigger this, and it makes sense to separate it out. llvm-svn: 276066
* Revert r275883 and r275891. They seem to cause PR28608.Sean Silva2016-07-192-60/+13
| | | | | | | | | | | | Revert "[LoopSimplify] Update LCSSA after separating nested loops." This reverts commit r275891. Revert "[LCSSA] Post-process PHI-nodes created by SSAUpdate when constructing LCSSA form." This reverts commit r275883. llvm-svn: 276064
* [PM] Port LoopUnroll.Sean Silva2016-07-194-0/+43
| | | | | | | | | We just set PreserveLCSSA to always true since we don't have an analogous method `mustPreserveAnalysisID(LCSSA)`. Also port LoopInfo verifier pass to test LoopUnrollPass. llvm-svn: 276063
* Codegen: Factor out canTailDuplicateKyle Butt2016-07-191-9/+19
| | | | | | | | canTailDuplicate accepts two blocks and returns true if the first can be duplicated into the second successfully. Use this function to encapsulate the heuristic. llvm-svn: 276062
* Get rid of call to StringRef::substr that's never used.Justin Lebar2016-07-191-1/+0
| | | | | | | | | | | | Summary: substr doesn't modify the string, so this line has no effect. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22540 llvm-svn: 276057
* [LSV] Insert stores at the right point.Justin Lebar2016-07-191-30/+28
| | | | | | | | | | | | | | | | | | | | | Summary: Previously, the insertion point for stores was the last instruction in Chain *before calling getVectorizablePrefixEndIdx*. Thus if getVectorizablePrefixEndIdx didn't return Chain.size(), we still would insert at the last instruction in Chain. This patch changes our internal API a bit in an attempt to make it less prone to this sort of error. As a result, we end up recalculating the Chain's boundary instructions, but I think worrying about the speed hit of this is a premature optimization right now. Reviewers: asbirlea, tstellarAMD Subscribers: mzolotukhin, arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D22534 llvm-svn: 276056
* [LSV] Use make_range, and reformat a DEBUG message. NFCJustin Lebar2016-07-191-12/+15
| | | | | | | | | | | | | | | Summary: The DEBUG message was hard to read because two Values were being printed on the same line with only the delimiter "aliases". This change makes us print each Value on its own line. Reviewers: asbirlea Subscribers: llvm-commits, arsenm, mzolotukhin Differential Revision: https://reviews.llvm.org/D22533 llvm-svn: 276055
* [LSV] Nix two global (ish) variables in the LoadStoreVectorizer. NFCJustin Lebar2016-07-191-10/+12
| | | | | | | | | | Reviewers: asbirlea Subscribers: mzolotukhin, llvm-commits, arsenm Differential Revision: https://reviews.llvm.org/D22532 llvm-svn: 276054
* [libFuzzer] extend the messages printed by afl_driverKostya Serebryany2016-07-191-4/+12
| | | | llvm-svn: 276052
* AMDGPU: Change fdiv lowering based on !fpmath metadataMatt Arsenault2016-07-198-49/+227
| | | | | | | | | | | If 2.5 ulp is acceptable, denormals are not required, and isn't a reciprocal which will already be handled, replace with a faster fdiv. Simplify the lowering tests by using per function subtarget features. llvm-svn: 276051
* Fix unused variableDaniel Berlin2016-07-191-2/+1
| | | | llvm-svn: 276050
* Make GVN Hoisting obey optnone/bisect.Paul Robinson2016-07-191-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D22545 llvm-svn: 276048
* Make MemorySSA::dominates/locallydominates constant timeDaniel Berlin2016-07-191-16/+36
| | | | | | | | | | | | Summary: Make MemorySSA::dominates/locallydominates constant time Reviewers: george.burgess.iv, gberry Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22527 llvm-svn: 276046
* Add AIX support to Path.inc, Host.h, and CMake.Chandler Carruth2016-07-191-2/+3
| | | | | | | | Patch by Andrew Paprocki! Differential Revision: https://reviews.llvm.org/D18359 llvm-svn: 276045
* RegScavenging: Add scavengeRegisterBackwards()Matthias Braun2016-07-192-108/+240
| | | | | | | | | | | | | | This is a variant of scavengeRegister() that works for enterBasicBlockEnd()/backward(). The benefit of the backward mode is that it is not affected by incomplete kill flags. This patch also changes PrologEpilogInserter::doScavengeFrameVirtualRegs() to use the register scavenger in backwards mode. Differential Revision: http://reviews.llvm.org/D21885 llvm-svn: 276044
* RegisterScavenger: Introduce backward() mode.Matthias Braun2016-07-191-23/+84
| | | | | | | | | | | | | | | | This adds two pieces: - RegisterScavenger:::enterBasicBlockEnd() which behaves similar to enterBasicBlock() but starts tracking at the end of the basic block. - A RegisterScavenger::backward() method. It is subtly different from the existing unprocess() method which only considers uses with the kill flag set: If a value is dead at the end of a basic block with a last use inside the basic block, unprocess() will fail to mark it as live. However we cannot change/fix this behaviour because unprocess() needs to perform the exact reverse operation of forward(). Differential Revision: http://reviews.llvm.org/D21873 llvm-svn: 276043
* [AArch64] Properly validate the reciprocal estimation.Evandro Menezes2016-07-191-0/+6
| | | | | | | | Add check for legal data types when expanding into a Newton series. Differential Revision: https://reviews.llvm.org/D22267 llvm-svn: 276041
* [InstCombine] fold add(zext(xor X, C), C) --> sext X when C is INT_MIN in ↵Sanjay Patel2016-07-191-0/+10
| | | | | | | | | | | | | | | | | | | the source type The pattern may look more obviously like a sext if written as: define i32 @g(i16 %x) { %zext = zext i16 %x to i32 %xor = xor i32 %zext, 32768 %add = add i32 %xor, -32768 ret i32 %add } We already have that fold in visitAdd(). Differential Revision: https://reviews.llvm.org/D22477 llvm-svn: 276035
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