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* [InstCombine] add test and code comment to show potentially misguided icmp ↵Sanjay Patel2016-10-251-0/+3
| | | | | | trunc transform llvm-svn: 285075
* [X86][SSE] Add support for (V)PMOVSX* constant foldingSimon Pilgrim2016-10-251-13/+54
| | | | | | | | | | We already have (V)PMOVZX* combining support, this is the beginning of handling (V)PMOVSX* similarly - other combines in combineVSZext can be generalized in future patches. This unearthed an interesting bug in that we were generating illegal build vectors on 32-bit targets - it was proving difficult to create a test for it from PMOVZX, but it fired immediately with PMOVSX. I've created a more general form of the existing getConstVector to handle these cases - ideally this should be handled in non-target-specific code but I couldn't find an equivalent. Differential Revision: https://reviews.llvm.org/D25874 llvm-svn: 285072
* fix warningRafael Espindola2016-10-251-0/+1
| | | | llvm-svn: 285064
* [DAGCombine] Preserve shuffles when one of the vector operands is constantZvi Rackover2016-10-251-34/+75
| | | | | | | | | | | | | | | | | | | | Summary: Do *not* perform combines such as: vector_shuffle<4,1,2,3>(build_vector(Ud, C0, C1 C2), scalar_to_vector(X)) -> build_vector(X, C0, C1, C2) Keeping the shuffle allows lowering the constant build_vector to a materialized constant vector (such as a vector-load from the constant-pool or some other idiom). Reviewers: delena, igorb, spatel, mkuper, andreadb, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25524 llvm-svn: 285063
* Make the LTO comdat api more symbol table friendly.Rafael Espindola2016-10-251-2/+29
| | | | | | | | | | | | | | | | | | | | | | In an IR symbol table I would expect the comdats to be represented as: - A table of strings, one for each comdat name. - Each symbol has an optional index into that table. The natural api for accessing that would be InputFile: ArrayRef<StringRef> getComdatTable() const; Symbol: int getComdatIndex() const; This patch implements an API as close to that as possible. The implementation on top of the current IRObjectFile is a bit hackish, but should map just fine over a symbol table and is very convenient to use. llvm-svn: 285061
* Fix an unused warning in WebAssemblyInstPrinter with NDEBUG.Benjamin Kramer2016-10-251-0/+1
| | | | | | | | Patch by Sam McCall! Differential Revision: https://reviews.llvm.org/D25934 llvm-svn: 285055
* [AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG and ↵Craig Topper2016-10-251-11/+39
| | | | | | | | | | | | | | ZERO_EXTEND_VECTOR_INREG for 512-bit vectors to support vpmovzxbq and vpmovsxbq. Summary: The one tricky thing about this is that the sign/zero_extend_inreg uses v64i8 as an input type which isn't legal without BWI support. Though the vpmovsxbq and vpmovzxbq instructions themselves don't require BWI. To support this we need to add custom lowering for ZERO_EXTEND_VECTOR_INREG with v64i8 input. This can mostly reuse the existing sign extend code with a couple checks for sign extend vs zero extend added. Reviewers: delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25594 llvm-svn: 285053
* GlobalDCE: Restore a statement accidentally removed in r285048.Peter Collingbourne2016-10-251-0/+1
| | | | llvm-svn: 285052
* MachineInstrBundle: Pass iterators to getBundle(Start|End); NFCMatthias Braun2016-10-252-3/+3
| | | | | | | | This is a function to go backwards in a block to find the first instruction in a bundle, so iterator is a more natural choice for parameter/return rather than a reference to a MachineInstruction. llvm-svn: 285051
* IR: Deduplicate getParent() functions on derived classes of GlobalValue into ↵Peter Collingbourne2016-10-252-16/+0
| | | | | | the base class. NFCI. llvm-svn: 285050
* [libFuzzer] simplify the code for use_cmp, also use the position hint when ↵Kostya Serebryany2016-10-259-102/+130
| | | | | | available, add a test llvm-svn: 285049
* GlobalDCE: Deduplicate code. NFCI.Peter Collingbourne2016-10-251-35/+18
| | | | llvm-svn: 285048
* [WebAssembly] Reorder load/store operands to match binary encoding.Dan Gohman2016-10-254-294/+296
| | | | | | | The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
* [WebAssembly] Implement more WebAssembly binary encoding.Dan Gohman2016-10-2416-131/+126
| | | | | | | | | | | | This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
* CodeGen/Passes: Pass MachineFunction as functor arg; NFCMatthias Braun2016-10-243-13/+14
| | | | | | | | Passing a MachineFunction as argument is more natural and avoids an unnecessary round-trip through the logic determining the correct Subtarget because MachineFunction already has a reference anyway. llvm-svn: 285039
* Fix regression from my recent GlobalsAA fix.Eli Friedman2016-10-241-1/+3
| | | | | | | | | | | | | There are two fixes here: one, AnalyzeUsesOfPointer can't return false until it has checked all the uses of the pointer. Two, if a global uses another global, we have to assume the address of the first global escapes. Fixes https://llvm.org/bugs/show_bug.cgi?id=30707 . Differential Revision: https://reviews.llvm.org/D25798 llvm-svn: 285034
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
* Use MachineInstr::mop_iterator instead of MIOperands; NFCMatthias Braun2016-10-246-36/+36
| | | | | | | | (Const)?MIOperands is equivalent to the C++ style MachineInstr::mop_iterator. Use the latter for consistency except for a few callers of MIOperands::analyzePhysReg(). llvm-svn: 285029
* nother additional error check for an invalid Mach-O fileKevin Enderby2016-10-242-11/+34
| | | | | | | when contained in a Mach-O universal file and the cputypes in both headers don’t match. llvm-svn: 285026
* Use SDValue::getConstantOperandVal() helper. NFCI.Simon Pilgrim2016-10-241-4/+2
| | | | llvm-svn: 285025
* [WebAssembly] Fix a broken URL.Dan Gohman2016-10-241-1/+1
| | | | llvm-svn: 285017
* [WebAssembly] Define the `end` opcode value.Dan Gohman2016-10-241-2/+4
| | | | | | | CFGStackify differentiates between END_LOOP and END_BLOCK, but wasm itself doesn't. For now, just use the same opcode for both. llvm-svn: 285016
* [WebAssembly] Update opcode values according to recent spec changes.Dan Gohman2016-10-246-112/+112
| | | | | | This corresponds to the "0xd" opcode renumbering. llvm-svn: 285014
* [WebAssembly] Add an option to make get_local/set_local explicit.Dan Gohman2016-10-2422-177/+632
| | | | | | | | | | This patch adds a pass, controlled by an option and off by default for now, for making implicit get_local/set_local explicit. This simplifies emitting wasm with MC. Differential Revision: https://reviews.llvm.org/D25836 llvm-svn: 285009
* Merge two if conditions into one. NFCI.Davide Italiano2016-10-241-3/+2
| | | | llvm-svn: 285008
* Target: Change various section classifiers in TargetLoweringObjectFile to ↵Peter Collingbourne2016-10-2422-170/+188
| | | | | | | | | | | | | | | | take a GlobalObject. These functions are about classifying a global which will actually be emitted, so it does not make sense for them to take a GlobalValue which may for example be an alias. Change the Mach-O object writer and the Hexagon, Lanai and MIPS backends to look through aliases before using TargetLoweringObjectFile interfaces. These are functional changes but all appear to be bug fixes. Differential Revision: https://reviews.llvm.org/D25917 llvm-svn: 285006
* CodeGen: Do not add a global's address space to the folding set profile.Peter Collingbourne2016-10-241-2/+0
| | | | | | | It is already part of the type (which is part of the global, which is already being added), so there's no need to do it. llvm-svn: 285002
* add-discriminators: Fix handling of lexical scopes.Adrian Prantl2016-10-241-9/+13
| | | | | | | | | | | | | | | This fixes a bug in the handling of lexical scopes, when more than one scope is defined on the same line or functions are inlined into call sites that are on the same line as the function definition. This situation can easily happen in macro expansions. The problem is solved by introducing a SmallDenseMap<DIScope *, DILexicalBlockFile *, 1> that keeps track of all the different lexical scopes that share a line/file location. Fixes PR30681. llvm-svn: 284998
* Revert r284972 and remove other defaulted copy/move constructors/=Krzysztof Parzyszek2016-10-241-8/+0
| | | | | | | David Blaikie pointed out that we get them for free without having to write anything. llvm-svn: 284996
* [PPC] Generate positive FP zero using xor insn instead of loading from ↵Ehsan Amiri2016-10-245-0/+43
| | | | | | | | | | | constant area https://reviews.llvm.org/D23614 Currently we load +0.0 from constant area. That can change to be generated using XOR instruction. llvm-svn: 284995
* Revert r284580+r284917. ("Synthesize TBB/TBH instructions")Eli Friedman2016-10-243-180/+14
| | | | | | | The optimization has correctness issues, so reverting for now to fix tests on thumb1 targets. llvm-svn: 284993
* Removed FIXME from include ordering commentSimon Pilgrim2016-10-241-1/+1
| | | | | | Nothing to fix, it's just the way it has to be. llvm-svn: 284991
* Check the number of Args in LibCallsShrinkWrap.Rong Xu2016-10-241-0/+2
| | | | | | Some library fucntions can have no argument. llvm-svn: 284989
* [AArch64] Optionally use the Newton series for reciprocal estimationEvandro Menezes2016-10-245-0/+94
| | | | | | | | | Add support for estimating the square root or its reciprocal and division or reciprocal using the combiner generic Newton series. Differential revision: https://reviews.llvm.org/D25291 llvm-svn: 284986
* [EarlyCSE] Optimize MemoryPhis and reduce memory clobber queries w/ MemorySSAGeoff Berry2016-10-241-10/+44
| | | | | | | | | | | | | | | | | | | | | Summary: When using MemorySSA, re-optimize MemoryPhis when removing a store since this may create MemoryPhis with all identical arguments. Also, when using MemorySSA to check if two MemoryUses are reading from the same version of the heap, use the defining access instead of calling getClobberingAccess, since the latter can currently result in many more AA calls. Once the MemorySSA use optimization tracking changes are done, we can remove this limitation, which should result in more loads being CSE'd. Reviewers: dberlin Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D25881 llvm-svn: 284984
* [PPC] Better codegen for AND, ANY_EXT, SRL sequenceEhsan Amiri2016-10-242-0/+23
| | | | | | | | https://reviews.llvm.org/D24924 This improves the code generated for a sequence of AND, ANY_EXT, SRL instructions. This is a targetted fix for this special pattern. The pattern is generated by target independet dag combiner and so a more general fix may not be necessary. If we come across other similar cases, some ideas for handling it are discussed on the code review. llvm-svn: 284983
* AMDGPU: Fix Two Address problems with v_movreldNicolai Haehnle2016-10-243-27/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The v_movreld machine instruction is used with three operands that are in a sense tied to each other (the explicit VGPR_32 def and the implicit VGPR_NN def and use). There is no way to express that using the currently available operand bits, and indeed there are cases where the Two Address instructions pass does the wrong thing. This patch introduces a new set of pseudo instructions that are identical in intended semantics as v_movreld, but they only have two tied operands. Having to add a new set of pseudo instructions is admittedly annoying, but it's a fairly straightforward and solid approach. The only alternative I see is to try to teach the Two Address instructions pass about Three Address instructions, and I'm afraid that's trickier and is going to end up more fragile. Note that v_movrels does not suffer from this problem, and so this patch does not touch it. This fixes several GL45-CTS.shaders.indexing.* tests. Reviewers: tstellarAMD, arsenm Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25633 llvm-svn: 284980
* Revert 284971.Nico Weber2016-10-241-73/+38
| | | | | | | | | It seems to break selfhost on some bots, see e.g. http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/21 http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/20 http://lab.llvm.org:8011/builders/clang-ppc64be-linux-lnt/builds/22 llvm-svn: 284979
* [MC] Fix Various End Of Line Comment checkingsNirav Dave2016-10-242-340/+286
| | | | | | | | | | | | | Fix AsmParser lines to correctly handle end-of-line pre-processor comments parsing when '#' is not the assembly line comment prefix. Reviewers: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25567 llvm-svn: 284978
* [Chrono] Fix !HAVE_FUTIMENS buildPavel Labath2016-10-241-1/+2
| | | | | | | | If we don't have futimens(), we fall back to futimes(), which only supports microsecond timestamps. In that case, we need to explicitly cast away the extra precision in setLastModificationAndAccessTime(). llvm-svn: 284977
* Remove unused #includes of TimeValue.h. NFC.Pavel Labath2016-10-242-2/+0
| | | | llvm-svn: 284975
* [Object] Replace TimeValue with std::chronoPavel Labath2016-10-242-25/+27
| | | | | | | | | | | | | | | Summary: Most of the changes are very straight-forward. The only choice I had to make was to use second-precision time points in the Archive classes. I did this because the archive files use that precision in the on-disk representation anyway. Reviewers: rafael, zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25773 llvm-svn: 284974
* AArch64 ILP32 relocations for assembly and ELFJoel Jones2016-10-245-76/+159
| | | | | | | | | | | | | | | | | | | Summary: Add relocations for AArch64 ILP32. Includes: - Addition of definitions for R_AARCH32_* - Definition of new -target-abi: ilp32 - Definition of data layout string - Tests for added relocations. Not comprehensive, but matches existing tests for 64-bit. Renames "CHECK-OBJ" to "CHECK-OBJ-LP64". - Tests for llvm-readobj Reviewers: zatrazz, peter.smith, echristo, t.p.northover Subscribers: aemerson, rengolin, mehdi_amini Differential Revision: https://reviews.llvm.org/D25159 llvm-svn: 284973
* [RDF] Add default move constructors/assignment operatorsKrzysztof Parzyszek2016-10-241-2/+6
| | | | llvm-svn: 284972
* [JumpThreading] Unfold selects that depend on the same conditionPablo Barrio2016-10-241-38/+73
| | | | | | | | | | | | | | | | | | Summary: These are good candidates for jump threading. This enables later opts (such as InstCombine) to combine instructions from the selects with instructions out of the selects. SimplifyCFG will fold the select again if unfolding wasn't worth it. Patch by James Molloy and Pablo Barrio. Reviewers: reames, bkramer, mcrosier, gberry, haicheng, jmolloy, sebpop Subscribers: jojo, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D25477 llvm-svn: 284971
* Fix windows builds by swapping windows.h and wincrypt.h ordering.Simon Pilgrim2016-10-241-1/+1
| | | | | | We need to include windows.h first even though it breaks default include ordering rules llvm-svn: 284968
* Remove TimeValue usage from llvm/SupportPavel Labath2016-10-249-93/+125
| | | | | | | | | | | | | | | | | Summary: This is a follow-up to D25416. It removes all usages of TimeValue from llvm/Support library (except for the actual TimeValue declaration), and replaces them with appropriate usages of std::chrono. To facilitate this, I have added small utility functions for converting time points and durations into appropriate OS-specific types (FILETIME, struct timespec, ...). Reviewers: zturner, mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25730 llvm-svn: 284966
* [mips] synci microMIPS instruction definition.Simon Dardis2016-10-243-3/+15
| | | | | | | | | | | | | Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci as not being part of microMIPS. This does not cover the sync instruction alias, as that will be handled with a different patch. Add sync to the valid tests for microMIPS. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D25795 llvm-svn: 284962
* [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR.Craig Topper2016-10-242-53/+16
| | | | | | Clang patch to replace 512-bit vector and 64-bit element versions with native IR will follow. llvm-svn: 284955
* [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constantSanjay Patel2016-10-231-43/+32
| | | | llvm-svn: 284953
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