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* R600/SI: Fix verifier error when producing v_madmk_f32Matt Arsenault2015-04-241-0/+3
| | | | | | Copy the kill flags when swapping the operands. llvm-svn: 235687
* R600/RegisterCoalescer: Enable more rematerialization/add missing testcaseMatthias Braun2015-04-241-2/+2
| | | | | | | This enables the rematerialization of some R600 MOV instructions in the RegisterCoalescer and adds a testcase for r235668. llvm-svn: 235675
* Fix a couple of typos in comments.Michael Zolotukhin2015-04-241-3/+3
| | | | llvm-svn: 235674
* RegisterCoalescer: implicit phsreg uses are fine when rematerializingMatthias Braun2015-04-241-2/+2
| | | | | | | The target hooks should have already checked them. This change is necessary to enable the remateriailzation on R600. llvm-svn: 235673
* Revert accidentally committed "MC: Allow targets to stop symbol name quoting"Matt Arsenault2015-04-233-6/+3
| | | | llvm-svn: 235672
* R600/SI: Special case v_mov_b32 as really rematerializableMatt Arsenault2015-04-232-0/+17
| | | | | | | This should be fixed to properly understand all rematerializable instructions while ignoring implicit reads of exec. llvm-svn: 235671
* MC: Allow targets to stop symbol name quotingMatt Arsenault2015-04-233-3/+6
| | | | | | | | | Currently symbol names are printed in quotes if it contains something outside of the arbitrary set of characters that isAcceptableChar tests for. On somem targets, it is never OK to print a symbol name in quotes so allow targets to opt out of this behavior. llvm-svn: 235670
* RegisterCoalescer: Avoid unnecessary register class widening for some ↵Matthias Braun2015-04-231-3/+25
| | | | | | | | | | | rematerializations I couldn't provide a testcase as none of the public targets has wide register classes with alot of subregisters and at the same time an instruction which "ReMaterializable" and "AsCheapAsAMove" (could probably be added for R600). llvm-svn: 235668
* Re-commit "[SEH] Remove the old __C_specific_handler code now that ↵Reid Kleckner2015-04-234-121/+2
| | | | | | | | | | WinEHPrepare works" This reverts commit r235617. r235649 should have addressed the problems. llvm-svn: 235667
* [PowerPC] Support register name prefixes for vector registersHal Finkel2015-04-231-0/+8
| | | | | | | Match binutils by supporting the optional register name prefix for new vector registers ("vs" for VSX registers and "q" for QPX registers). llvm-svn: 235665
* [PowerPC] Use sync inst alias when printingHal Finkel2015-04-231-1/+1
| | | | | | | So long as the choice between printing msync and sync is not ambiguous, we can print 'sync 0' and just 'sync'. llvm-svn: 235663
* R600: Correctly lower CONCAT_VECTOR nodes with more than 2 operandsTom Stellard2015-04-231-4/+2
| | | | llvm-svn: 235662
* Fix comment for NoCommonBits.Michael Zolotukhin2015-04-231-1/+2
| | | | | | | Maybe there is a better wording, but at least it should be technically correct now. llvm-svn: 235660
* [PowerPC] Add asm/disasm support for dcbt with hintHal Finkel2015-04-234-8/+123
| | | | | | | | | | | | | | | | | | Add assembler/disassembler support for dcbt/dcbtst (and aliases) with the hint field specified (non-zero). Unforunately, the syntax for this instruction is special in that it differs for server vs. embedded cores: dcbt ra, rb, th [server] dcbt th, ra, rb [embedded] where th can be omitted when it is 0. dcbtst is the same. Thus we need to play games in the parser and the printer to flip the operands around on the embedded cores. We'll use the server syntax as the default (binutils currently uses the embedded form by default, but IBM is changing that). We also stop marking dcbtst as having unmodeled side effects (this is not necessary, it is just a hint like dcbt -- noticed by inspection, so no separate test case). llvm-svn: 235657
* [WinEH] Ignore filter clauses while mapping landing pad blocks.Andrew Kaylor2015-04-231-0/+6
| | | | llvm-svn: 235656
* Remove trivial assert to fix NDEBUG Werror buildsReid Kleckner2015-04-231-2/+0
| | | | llvm-svn: 235652
* Recommit r235458: [opaque pointer type] Avoid using ↵David Blaikie2015-04-236-32/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PointerType::getElementType for a few cases of CallInst (reverted in r235533) Original commit message: "Calls to llvm::Value::mutateType are becoming extra-sensitive now that instructions have extra type information that will not be derived from operands or result type (alloca, gep, load, call/invoke, etc... ). The special-handling for mutateType will get more complicated as this work continues - it might be worth making mutateType virtual & pushing the complexity down into the classes that need special handling. But with only two significant uses of mutateType (vectorization and linking) this seems OK for now. Totally open to ideas/suggestions/improvements, of course. With this, and a bunch of exceptions, we can roundtrip an indirect call site through bitcode and IR. (a direct call site is actually trickier... I haven't figured out how to deal with the IR deserializer's lazy construction of Function/GlobalVariable decl's based on the type of the entity which means looking through the "pointer to T" type referring to the global)" The remapping done in ValueMapper for LTO was insufficient as the types weren't correctly mapped (though I was using the post-mapped operands, some of those operands might not have been mapped yet so the type wouldn't be post-mapped yet). Instead use the pre-mapped type and explicitly map all the types. llvm-svn: 235651
* [WinEH] Replace more lpad value uses with undefReid Kleckner2015-04-231-9/+20
| | | | | | | | | | | | | | | | | | | | | We were asserting on code like this: extern "C" unsigned long _exception_code(); void might_crash(unsigned long); void foo() { __try { might_crash(0); } __except(1) { might_crash(_exception_code()); } } Gtest and many other libraries get the exception code from the __except block. What's supposed to happen here is that EAX is live into the __except block, and it contains the exception code. Eventually we'll represent that as a use of the landingpad ehptr value, but for now we can replace it with undef. llvm-svn: 235649
* [MachineCopyPropagation] Handle undef flags conservatively so that we do notQuentin Colombet2015-04-231-1/+5
| | | | | | | | | | | | | | | | | | | | | remove copies that are useful after breaking some hardware dependencies. In other words, handle this kind of situations conservatively by assuming reg2 is redefined by the undef flag. reg1 = copy reg2 = inst reg2<undef> reg2 = copy reg1 Copy propagation used to remove the last copy. This is incorrect because the undef flag on reg2 in inst, allows next passes to put whatever trashed value in reg2 that may help. In practice we end up with this code: reg1 = copy reg2 reg2 = 0 = inst reg2<undef> reg2 = copy reg1 This fixes PR21743. llvm-svn: 235647
* Unbreak buildKrzysztof Parzyszek2015-04-231-1/+1
| | | | llvm-svn: 235646
* [Hexagon] Minor cleanup in HexagonFrameLoweringKrzysztof Parzyszek2015-04-231-6/+2
| | | | llvm-svn: 235645
* R600/SI: Fix indirect addressing with a negative constant offsetTom Stellard2015-04-231-16/+55
| | | | | | | | | | | When the base register index of the vector plus the constant offset was less than zero, we were passing the wrong base register to the indirect addressing instruction. In this case, we need to set the base register to v0 and then add the computed (negative) index to m0. llvm-svn: 235641
* Thumb2: When applying branch optimizations, visit branches in reverse order.Peter Collingbourne2015-04-231-2/+7
| | | | | | | | | | | | The order in which branches appear in ImmBranches is approximately their order within the function body. By visiting later branches first, we reduce the distance between earlier forward branches and their targets, making it more likely that the cbn?z optimization, which can only apply to forward branches, will succeed for those earlier branches. Differential Revision: http://reviews.llvm.org/D9185 llvm-svn: 235640
* ARM: When re-creating a branch via InsertBranch, preserve CPSR flags.Peter Collingbourne2015-04-231-2/+4
| | | | | | | | | | | | | In particular, this preserves the kill flag, which allows the Thumb2 cbn?z optimization to be applied in cases where a branch has been re-created after the live variables analysis pass, e.g. by the machine block placement pass. This appears to be low risk; a number of other targets seem to already be doing something similar, e.g. AArch64, PowerPC. Differential Revision: http://reviews.llvm.org/D9184 llvm-svn: 235639
* Thumb2: When optimizing for size, do not if-convert branches involving ↵Peter Collingbourne2015-04-231-0/+27
| | | | | | | | | | | comparisons with zero. This allows the constant island pass to lower these branches to cbn?z instructions, resulting in a shorter instruction sequence. Differential Revision: http://reviews.llvm.org/D9183 llvm-svn: 235638
* ARM: When spilling extra registers for alignment, prefer low registers on ↵Peter Collingbourne2015-04-231-2/+2
| | | | | | | | | | | all Thumb targets. This makes it more likely that we can use the 16-bit push and pop instructions on Thumb-2, saving around 4 bytes per function. Differential Revision: http://reviews.llvm.org/D9165 llvm-svn: 235637
* ARM: Only enforce 4-byte alignment on Thumb-2 functions with constant pools.Peter Collingbourne2015-04-231-18/+1
| | | | | | | | | | | | | | | | | This appears to have been introduced back in r76698 as part of an unrelated change. I can find no official ARM documentation stating that Thumb-2 functions require 4-byte alignment; in fact, ARM documentation appears to contradict this (see, e.g., ARM Architecture Reference Manual Thumb-2 Supplement, section 2.6.1: "Thumb-2 enforces 16-bit alignment on all instructions."). Also remove code that sets alignment for ARM functions, which is redundant with code in the MachineFunction constructor, and remove the hidden -arm-align-constant-islands flag, which has been enabled by default since r146739 (Dec 2011) and has probably received sufficient testing by now. Differential Revision: http://reviews.llvm.org/D9138 llvm-svn: 235636
* [Hexagon] Fix compiler warnings in release buildKrzysztof Parzyszek2015-04-232-1/+6
| | | | | | Patch by Aditya Nandakumar. llvm-svn: 235635
* [getUnderlyingOjbects] Analyze loop PHIs further to remove false positivesAdam Nemet2015-04-232-11/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifically, if a pointer accesses different underlying objects in each iteration, don't look through the phi node defining the pointer. The motivating case is the underlyling-objects-2.ll testcase. Consider the loop nest: int **A; for (i) for (j) A[i][j] = A[i-1][j] * B[j] This loop is transformed by Load-PRE to stash away A[i] for the next iteration of the outer loop: Curr = A[0]; // Prev_0 for (i: 1..N) { Prev = Curr; // Prev = PHI (Prev_0, Curr) Curr = A[i]; for (j: 0..N) Curr[j] = Prev[j] * B[j] } Since A[i] and A[i-1] are likely to be independent pointers, getUnderlyingObjects should not assume that Curr and Prev share the same underlying object in the inner loop. If it did we would try to dependence-analyze Curr and Prev and the analysis of the corresponding SCEVs would fail with non-constant distance. To fix this, the getUnderlyingObjects API is extended with an optional LoopInfo parameter. This is effectively what controls whether we want the above behavior or the original. Currently, I only changed to use this approach for LoopAccessAnalysis. The other testcase is to guard the opposite case where we do want to look through the loop PHI. If we step through an array by incrementing a pointer, the underlying object is the incoming value of the phi as the loop is entered. Fixes rdar://problem/19566729 llvm-svn: 235634
* [NVPTX] run SeparateConstOffsetFromGEP before SLSRJingyue Wu2015-04-231-4/+6
| | | | | | | | | | | | | | | | | | Summary: We pick this order because SeparateConstOffsetFromGEP may create more opportunities for SLSR. Test Plan: reassociate-geps-and-slsr.ll no performance regression on internal benchmarks Reviewers: meheff Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D9230 llvm-svn: 235632
* R600/SI: Add assembler support for all CI and VI VOP1 instructionsTom Stellard2015-04-236-11/+71
| | | | llvm-svn: 235629
* R600/SI: v_mov_fed_b32 does not exist on VITom Stellard2015-04-231-1/+1
| | | | llvm-svn: 235628
* R600/SI: Use a better error message for unsupported instructions in the ↵Tom Stellard2015-04-231-1/+1
| | | | | | assembler llvm-svn: 235627
* R600/SI: Improve AsmParser support for forced e64 encodingTom Stellard2015-04-231-5/+45
| | | | | | | We can now force e64 encoding even when the operands would be legal for e32 encoding. llvm-svn: 235626
* [WinEH] Handle stubs for outlined functions that have only unreached ↵Andrew Kaylor2015-04-231-9/+16
| | | | | | terminators. llvm-svn: 235618
* Revert "[SEH] Remove the old __C_specific_handler code now that WinEHPrepare ↵Reid Kleckner2015-04-234-2/+121
| | | | | | | | | | works" We still have some "uses remain after removal" issues in -O0 builds. This reverts commit r235557. llvm-svn: 235617
* [PowerPC] Enable printing instructions using aliasesHal Finkel2015-04-232-2/+8
| | | | | | | | | | | TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
* Move DIContext.h to common DebugInfo location.Zachary Turner2015-04-234-22/+5
| | | | | | | | | | This will enable us to create a PDBContext so as to expose some amount of debug info functionality through a common interace. Differential Revision: http://reviews.llvm.org/D9205 Reviewed by: Alexey Samsonov llvm-svn: 235612
* Move Value.isDereferenceablePointer to ValueTracking [NFC]Philip Reames2015-04-237-141/+152
| | | | | | | | | | | Move isDereferenceablePointer function to Analysis. This function recursively tracks dereferencability over a chain of values like other functions in ValueTracking. This refactoring is motivated by further changes to support dereferenceable_or_null attribute (http://reviews.llvm.org/D8650). isDereferenceablePointer will be extended to perform context-sensitive analysis and IR is not a good place to have such functionality. Patch by: Artur Pilipenko <apilipenko@azulsystems.com> Differential Revision: reviews.llvm.org/D9075 llvm-svn: 235611
* [AArch64] Add nvcast patterns for v4f16 and v8f16Pirama Arumuga Nainar2015-04-231-0/+8
| | | | | | | | | | | | | | | | | | Summary: Constant stores of f16 vectors can create NvCast nodes from various operand types to v4f16 or v8f16 depending on patterns in the stored constants. This patch adds nvcast rules with v4f16 and v8f16 values. AArchISelLowering::LowerBUILD_VECTOR has the details on which constant patterns generate the nvcast nodes. Reviewers: jmolloy, srhines, ab Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9201 llvm-svn: 235610
* [AArch64] Handle vec4, vec8, vec16 *itofp for halfPirama Arumuga Nainar2015-04-231-0/+10
| | | | | | | | | | | | | | | | | | | | | | Summary: Set operation action for SINT_TO_FP and UINT_TO_FP nodes with v4i32, v8i8, v8i16 inputs to allow promotion of v4f16 results. Add tests for sitofp and uitofp for vec4, vec8, vec16, and i8, i16, i32, and i64 vectors. Only missing tests are for v16i8 and v16i16 as the shift operations are too complicated to write a proper check sequence. The conversions from v4i64 to v4f16 do not depend on this patch - v4i64 is split and the conversion gets handled while lowering v2i64. I am adding a test here for completeness. Reviewers: aemerson, rengolin, ab, jmolloy, srhines Subscribers: rengolin, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D9166 llvm-svn: 235609
* Re-commit r235560: Switch lowering: extract jump tables and bit tests before ↵Hans Wennborg2015-04-234-765/+904
| | | | | | | | | | | building binary tree (PR22262) Third time's the charm. The previous commit was reverted as a reverse for-loop in SelectionDAGBuilder::lowerWorkItem did 'I--' on an iterator at the beginning of a vector, causing asserts when using debugging iterators. This commit fixes that. llvm-svn: 235608
* [Hexagon] Shrink-wrap stack frame (Hexagon-specific)Krzysztof Parzyszek2015-04-233-386/+562
| | | | llvm-svn: 235603
* [mips] [IAS] Move NOP emission after pseudo-instruction expansion. NFC.Toma Tabacu2015-04-231-11/+9
| | | | | | As suggested in the review for http://reviews.llvm.org/D8537. llvm-svn: 235601
* Revert r235560; this commit was causing several failed assertions in Debug ↵Aaron Ballman2015-04-234-903/+765
| | | | | | builds using MSVC's STL. The iterator is being used outside of its valid range. llvm-svn: 235597
* Be more strict about the operand for the array type in BitcodeReaderFilipe Cabecinhas2015-04-231-0/+3
| | | | | | | | | | | | Summary: Bug found with AFL fuzz. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9016 llvm-svn: 235596
* Verify sizes when trying to read a BitcodeAbbrevOpFilipe Cabecinhas2015-04-231-0/+9
| | | | | | | | | | | | | | | | Summary: Make sure the abbrev operands are valid and that we can read/skip them afterwards. Bug found with AFL fuzz. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9030 llvm-svn: 235595
* [DAGCombiner] Remove extra bitcasts surrounding vector shuffles Simon Pilgrim2015-04-231-0/+45
| | | | | | | | Patch to remove extra bitcasts from shuffles, this is often a legacy of XformToShuffleWithZero being used to combine bitmaskings (of float vectors bitcast to integer vectors) into shuffles: bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1) Differential Revision: http://reviews.llvm.org/D9097 llvm-svn: 235578
* Move common loop utility function isInductionPHI into LoopUtils.cppKarthik Bhat2015-04-232-43/+46
| | | | | | | This patch refactors the definition of common utility function "isInductionPHI" to LoopUtils.cpp. This fixes compilation error when configured with -DBUILD_SHARED_LIBS=ON llvm-svn: 235577
* Add support to interchange loops with reductions.Karthik Bhat2015-04-232-80/+227
| | | | | | | This patch enables interchanging of tightly nested loops with reductions. Differential Revision: http://reviews.llvm.org/D8314 llvm-svn: 235571
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