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* Cache interval iterators in SplitEditor::addTruncSimpleRange so we only have toJakob Stoklund Olesen2010-10-071-10/+20
| | | | | | do one find(). llvm-svn: 115929
* Clean up debug printing.Jakob Stoklund Olesen2010-10-071-15/+19
| | | | llvm-svn: 115928
* Next step on the getting-rid-of-static-ctors train: begin adding per-libraryOwen Anderson2010-10-074-2/+88
| | | | | | | initialization functions that initialize the set of passes implemented in that library. Add C bindings for these functions as well. llvm-svn: 115927
* Fix a warning when building with clang++.Owen Anderson2010-10-071-2/+3
| | | | llvm-svn: 115924
* Add the missing cases to the type->registerclass conversion function.Kalle Raiskila2010-10-071-0/+14
| | | | llvm-svn: 115921
* Implement two virtual functions in SPUTargetLowering.Kalle Raiskila2010-10-072-0/+31
| | | | | | | | | | Before the implementation of isLegalAddressingMode, some rare cases of code were miscompiled if optimized with the LoopStrengthReduce pass. It is unclear (to me) if LSR is "allowed" to produce wrong code with a bad TargetLowering, or if the bug is elsewhere and this patch just hides it. llvm-svn: 115919
* Minor cosmetic change: fix DOSish \r\n.NAKAMURA Takumi2010-10-071-4/+4
| | | | llvm-svn: 115910
* MC-COFF: Fix symbol aliases. Fixes PR8251.Michael J. Spencer2010-10-071-5/+36
| | | | llvm-svn: 115909
* Use the correct register class for load instructions - fixesEric Christopher2010-10-071-1/+8
| | | | | | compilation of MultiSource/Benchmarks/Bullet. llvm-svn: 115907
* Use the correct register class here.Eric Christopher2010-10-071-1/+3
| | | | llvm-svn: 115906
* Use the thumb2 conditional move instruction.Eric Christopher2010-10-071-1/+1
| | | | llvm-svn: 115905
* Remove in-progress assertion, add TODO.Eric Christopher2010-10-071-1/+1
| | | | llvm-svn: 115904
* Move the pass initialization helper functions into the llvm namespace, and addOwen Anderson2010-10-073-13/+13
| | | | | | | a header declaring them all. This is also where we will declare per-library pass-set initializer functions down the road. llvm-svn: 115900
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of ↵Evan Cheng2010-10-077-42/+143
| | | | | | vldr / vstr, etc. llvm-svn: 115898
* add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,Chris Lattner2010-10-071-178/+18
| | | | | | allowing us to convert ADD over. deletes 160 lines of .td file. llvm-svn: 115897
* Fix a few issues in ArithBinOpEFLAGS that made it specific to and.Chris Lattner2010-10-071-497/+18
| | | | | | | | | Start using ArithBinOpEFLAGS for OR, XOR, and SUB. This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all defined exactly the same way instead of being close relatives. llvm-svn: 115896
* Convert 'and' to single instance of a multipatternChris Lattner2010-10-071-50/+63
| | | | | | | | | | | which instantiates the 34 versions of and all in one swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not be required, but tblgen's feeble brain explodes when I use Or4<BaseOpc>.V in the multipattern. No change in the generated .inc files. llvm-svn: 115893
* Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.Jim Grosbach2010-10-072-7/+20
| | | | llvm-svn: 115890
* add a new BinOpAI class to represent the immediate form that directly acts ↵Chris Lattner2010-10-071-10/+16
| | | | | | | | | | on EAX. This does change the generated .inc files to include the implicit use/def of eax. Since these instructions are only generated by the assembler and disassembler it doesn't actually matter though. llvm-svn: 115885
* Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.Jim Grosbach2010-10-072-8/+23
| | | | llvm-svn: 115884
* add a bunch of classes for other common patterns.Chris Lattner2010-10-071-60/+51
| | | | | | As usual, no change in generated .inc files. llvm-svn: 115882
* Since the Hello pass is built as a loadable dynamic library, don't try to ↵Owen Anderson2010-10-071-4/+3
| | | | | | convert it to new-style registration yet. llvm-svn: 115881
* Define a new BinOpRI8 class and use it to define the imm8 versions of and.Chris Lattner2010-10-071-27/+43
| | | | llvm-svn: 115880
* Constrain the offset register to a *_NOSP register class when inserting LEAJakob Stoklund Olesen2010-10-071-2/+35
| | | | | | | | instructions. This unbreaks the machine code verifier and fixes PR8317. llvm-svn: 115879
* add the pattern operator to match to X86TypeInfo, use this to Chris Lattner2010-10-071-11/+11
| | | | | | convert AND64ri32 to use BinOpRI. llvm-svn: 115878
* Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.Jakob Stoklund Olesen2010-10-061-1/+6
| | | | | | This function looks like it is about ready to be generated by TebleGen. llvm-svn: 115876
* Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.Jakob Stoklund Olesen2010-10-062-7/+16
| | | | | | | | This function is intended to be used when inserting a machine instruction that trivially restricts the legal registers, like LEA requiring a GR32_NOSP argument. llvm-svn: 115875
* Skip unused registers when verifying LiveIntervals.Jakob Stoklund Olesen2010-10-061-0/+5
| | | | llvm-svn: 115874
* remove trailing whitespaceJim Grosbach2010-10-061-5/+5
| | | | llvm-svn: 115860
* First in a sequence of ARM/MC/*ELF* specific work.Jason W Kim2010-10-062-39/+60
| | | | | | | | | Lifted the EmitRawText calls to ARMAsmPrinter::emitAttribute() Added ARMAsmPrinter::emitAttributes() (plural s). TODO: .cpu attribute needs to be refactored llvm-svn: 115859
* Another case of 256 sections not being enough :-)Rafael Espindola2010-10-061-1/+1
| | | | llvm-svn: 115858
* Appease the clang self-host buildbot by providing a correct instantiation.Owen Anderson2010-10-061-3/+3
| | | | llvm-svn: 115857
* Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.Jim Grosbach2010-10-063-7/+9
| | | | llvm-svn: 115853
* Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).Jim Grosbach2010-10-064-21/+12
| | | | llvm-svn: 115845
* Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-neededJim Grosbach2010-10-062-40/+3
| | | | | | "lane" operand modifier. llvm-svn: 115843
* Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually beJim Grosbach2010-10-062-7/+28
| | | | | | pseudo instructions. llvm-svn: 115840
* Get binding and visibility info from the the alias, but Type from the symbolRafael Espindola2010-10-061-3/+25
| | | | | | being aliased. llvm-svn: 115836
* Hide analysis group registration behind a macro, just like pass registration.Owen Anderson2010-10-064-4/+4
| | | | llvm-svn: 115835
* Add support for DW_TAG_unspecified_parameters.Devang Patel2010-10-062-7/+29
| | | | llvm-svn: 115833
* Add a 'pattern' arg to the ARM PseudoNeonI class.Jim Grosbach2010-10-062-7/+9
| | | | llvm-svn: 115831
* MC: Add missing forward in MCLoggingStreamer.Michael J. Spencer2010-10-061-0/+1
| | | | llvm-svn: 115830
* Revert "RequiresUnique" patch. This should be handled at a lower level.Bill Wendling2010-10-061-37/+7
| | | | llvm-svn: 115827
* If a symbol is global, reloc against it even if it is in a mergeable section.Rafael Espindola2010-10-061-3/+3
| | | | llvm-svn: 115817
* Remove unused variables.Nick Lewycky2010-10-061-3/+0
| | | | llvm-svn: 115802
* target operand flag values aren't a bitmaskJim Grosbach2010-10-061-2/+2
| | | | llvm-svn: 115798
* Make sure weak symbols are listed after the local ones.Rafael Espindola2010-10-062-2/+4
| | | | llvm-svn: 115795
* Correctly handle GOTPCREL relocations.Rafael Espindola2010-10-061-3/+6
| | | | llvm-svn: 115793
* ComputeLinearIndex doesn't need its TLI argument.Dan Gohman2010-10-062-9/+7
| | | | llvm-svn: 115792
* Change RequiresMerge to RequiresUnique. It's a better description of what thisBill Wendling2010-10-061-7/+8
| | | | | | | | fix is trying to accomplish. This code could still use some polishing. llvm-svn: 115759
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-0612-65/+335
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
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