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* R600: Add support for 24-bit MAD instructionsTom Stellard2013-07-232-2/+12
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186923
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-234-5/+75
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186922
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-234-11/+39
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186921
* R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cppTom Stellard2013-07-232-1/+1
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186920
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-234-49/+160
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* R600: Use KCache for kernel argumentsTom Stellard2013-07-234-49/+22
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186918
* R600: Simplify assembly for KCache registers using the TableGen !add operatorTom Stellard2013-07-231-4/+4
| | | | | | | | | | | | | Before: MOV * T0.W, KC0[131-128].Y After: MOV * T0.W, KC0[3].Y Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186917
* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-233-11/+27
| | | | | | | | A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186916
* R600: Use correct LoadExtType when lowering kernel argumentsTom Stellard2013-07-231-1/+9
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186915
* R600: Clean up extended load patternsTom Stellard2013-07-234-15/+31
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600: Expand vector FNEGTom Stellard2013-07-231-0/+3
| | | | llvm-svn: 186913
* Revert r186907 to fix bots.Craig Topper2013-07-231-1/+1
| | | | llvm-svn: 186910
* Don't let x86 asm printer use the no operand movsd alias. It should use the ↵Craig Topper2013-07-231-1/+1
| | | | | | normal movsl instead. llvm-svn: 186907
* Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix ↵Craig Topper2013-07-231-0/+7
| | | | | | | | to their 32-bit forms. This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency. llvm-svn: 186904
* Debug Info Finder: use processDeclare and processValue to list debug infoManman Ren2013-07-232-1/+36
| | | | | | | | | | | MDNodes used by DbgDeclareInst and DbgValueInst. Another 16 testing cases failed and they are disabled with -disable-debug-info-verifier. A total of 34 cases are disabled with -disable-debug-info-verifier and will be corrected. llvm-svn: 186902
* Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, ↵Craig Topper2013-07-231-4/+4
| | | | | | | | %reg. It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied. llvm-svn: 186900
* Suppress argumentless aliases for some x86 FP operations from being used by ↵Craig Topper2013-07-231-14/+14
| | | | | | the asm writer. Prefer to use the explicit %st(1) form. llvm-svn: 186897
* Remove extraneous null statement. No functionality change!Nick Lewycky2013-07-221-1/+1
| | | | llvm-svn: 186893
* Use switch instead of if. No functionality change.Jakub Staszak2013-07-221-14/+17
| | | | llvm-svn: 186892
* Remove trailing spaces.Jakub Staszak2013-07-221-37/+37
| | | | llvm-svn: 186890
* Typo.Eric Christopher2013-07-221-1/+1
| | | | llvm-svn: 186886
* 80-column tidying. Formatting choices by clang-format.Eric Christopher2013-07-221-14/+16
| | | | llvm-svn: 186885
* When we vectorize across multiple basic blocks we may vectorize PHINodes ↵Nadav Rotem2013-07-221-3/+31
| | | | | | that create a cycle. We already break the cycle on phi-nodes, but arithmetic operations are still uplicated. This patch adds code that checks if the operation that we are vectorizing was vectorized during the visit of the operands and uses this value if it can. llvm-svn: 186883
* OldPtr is llvm::Instruction. Remove unneeded cast<>.Jakub Staszak2013-07-221-1/+1
| | | | llvm-svn: 186880
* Silence gcc warning.Richard Trieu2013-07-221-1/+1
| | | | llvm-svn: 186879
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-222-15/+34
| | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
* Change tabs to spaces.Jakub Staszak2013-07-221-2/+2
| | | | llvm-svn: 186877
* [stackprotector] Changed isNoopBitcast/sameNoopInput to take ↵Michael Gottesman2013-07-221-2/+2
| | | | | | | | | | TargetLoweringBase instead of TargetLowering. Both functions only use functionality from TargetLoweringBase. rdar://13935163 llvm-svn: 186874
* Recommit r186813: More Intel syntax alias fixes. With the addition of ↵Craig Topper2013-07-221-28/+28
| | | | | | suppressing some of the aliases from being emitted by the asm printer. llvm-svn: 186869
* [stackprotector] Refactored ssp prologue creation code into its own helper ↵Michael Gottesman2013-07-221-35/+41
| | | | | | | | | | function. No functionality change. rdar://13935163 llvm-svn: 186868
* Debug Info Finder: add processScope to actually handle the Scope.Manman Ren2013-07-221-3/+23
| | | | | | Instead of just adding the scope to the list, we actually handle the scope. llvm-svn: 186867
* Recommit r186217 with testcase fix:Bill Wendling2013-07-221-7/+19
| | | | | | | | | Use the function attributes to pass along the stack protector buffer size. Now that we have robust function attributes, don't use a command line option to specify the stack protecto buffer size. llvm-svn: 186863
* [mips] Fix MipsAsmParser::parseCCRRegs.Akira Hatanaka2013-07-221-17/+10
| | | | | | | | Enable parsing all 32 floating point control registers $0-31 and stop trying to parse floating point condition code register $fcc0. Also, return ParseFail if the operand being parsed is not in the expected format. llvm-svn: 186861
* Fix spelling and grammarMatt Arsenault2013-07-221-12/+12
| | | | llvm-svn: 186858
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-223-12/+5
| | | | | | | the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. llvm-svn: 186855
* Formatting.Eric Christopher2013-07-221-1/+1
| | | | llvm-svn: 186851
* Fix an obvious typo in the loop vectorizer where the cost model uses the ↵Nadav Rotem2013-07-221-2/+2
| | | | | | | | wrong variable. The variable BlockCost is ignored. We don't have tests for the effect of if-conversion loops because it requires a big test (that includes if-converted loops) and it is difficult to find and balance a loop to do the right thing. llvm-svn: 186845
* [NVPTX] Remove unused prototypesJustin Holewinski2013-07-221-3/+0
| | | | llvm-svn: 186844
* Option parsing: allow aliases in groupsHans Wennborg2013-07-221-6/+4
| | | | | | | | | Option aliases in option groups were previously disallowed by an assert. As far as I can tell, there was no technical reason for this, and I would like to be able to put cl.exe compatible options in their own group for Clang, so let's change the assert. llvm-svn: 186838
* This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-224-25/+62
| | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset llvm-svn: 186831
* [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and appendJustin Holewinski2013-07-223-56/+61
| | | | | | .ftz to instructions if the nvptx-f32ftz attribute is set to "true" llvm-svn: 186820
* Revert "More Intel syntax alias fixes."Tim Northover2013-07-221-28/+28
| | | | | | This reverts commit r186813, which broke the bots. llvm-svn: 186818
* Fix typo. Change %cl to CL in Intel pattern.Craig Topper2013-07-221-1/+1
| | | | llvm-svn: 186815
* More Intel syntax alias fixes.Craig Topper2013-07-223-19/+19
| | | | llvm-svn: 186814
* More Intel syntax alias fixes.Craig Topper2013-07-221-28/+28
| | | | llvm-svn: 186813
* Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.Craig Topper2013-07-221-6/+6
| | | | llvm-svn: 186812
* Add Intel variants to aliases for some FP instructions.Craig Topper2013-07-221-8/+8
| | | | llvm-svn: 186811
* ARM: remove now unneeded custom Asm convertersTim Northover2013-07-224-415/+16
| | | | | | | | After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. llvm-svn: 186810
* Reverse operands for Intel syntax form of 'bt' alias.Craig Topper2013-07-221-1/+2
| | | | llvm-svn: 186809
* Delete unused helper functions.Nadav Rotem2013-07-221-32/+0
| | | | llvm-svn: 186808
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