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* Statistic/Timer: Include timers in PrintStatisticsJSON().Matthias Braun2016-11-182-27/+67
| | | | | | Differential Revision: https://reviews.llvm.org/D25588 llvm-svn: 287370
* Timer: Track name and description.Matthias Braun2016-11-1812-75/+120
| | | | | | | | | | | | | The previously used "names" are rather descriptions (they use multiple words and contain spaces), use short programming language identifier like strings for the "names" which should be used when exporting to machine parseable formats. Also removed a unused TimerGroup from Hexxagon. Differential Revision: https://reviews.llvm.org/D25583 llvm-svn: 287369
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-182-2/+6
| | | | | | | | | | | | Fixes PR28751. Reviewers: MatzeB, qcolombet Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D26775 llvm-svn: 287368
* AMDGPU: Fix unused variable warningMatt Arsenault2016-11-181-5/+4
| | | | llvm-svn: 287362
* [LTO] Add option to generate optimization recordsAdam Nemet2016-11-181-0/+34
| | | | | | | | | | It is used to drive this from the clang driver via -mllvm. Same option name is used as in opt. Differential Revision: https://reviews.llvm.org/D26832 llvm-svn: 287356
* IRMover: Avoid accidentally mapping types from the destination module (PR30799)Hans Wennborg2016-11-181-0/+8
| | | | | | | | | | | | | | During Module linking, it's possible for SrcM->getIdentifiedStructTypes(); to return types that are actually defined in the destination module (DstM). Depending on how the bitcode file was read, getIdentifiedStructTypes() might do a walk over all values, including metadata nodes, looking for types. In my case, a debug info metadata node was shared between the two modules, and it referred to a type defined in the destination module (see test case). Differential Revision: https://reviews.llvm.org/D26212 llvm-svn: 287353
* Add link-time detection of LLVM_ABI_BREAKING_CHECKS mismatchMehdi Amini2016-11-181-0/+16
| | | | | | | | | | | | | | | | | | | | | Summary: LLVM will define a symbol, either EnableABIBreakingChecks or DisableABIBreakingChecks depending on the configuration setting for LLVM_ABI_BREAKING_CHECKS. The llvm-config.h header will add weak references to these symbols in every clients that includes this header. This should ensure that a mismatch triggers a link failure (or a load time failure for DSO). On MSVC, the pragma "detect_mismatch" is used instead. Reviewers: rnk, jroelofs Subscribers: llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D26841 llvm-svn: 287352
* [PPC] limit line width to 80 charactersEhsan Amiri2016-11-181-1/+2
| | | | | | NFC. Forgot to fix this in the original commit. llvm-svn: 287350
* [mips][msa] Implement f16 supportSimon Dardis2016-11-184-0/+418
| | | | | | | | | | | | | | | The MIPS MSA ASE provides instructions to convert to and from half precision floating point. This patch teaches the MIPS backend to treat f16 as a legal type and how to promote such values to f32 for the usual set of operations. As a result of this, the fexup[lr].w intrinsics no longer crash LLVM during type legalization. Reviewers: zoran.jovanvoic, vkalintiris Differential Revision: https://reviews.llvm.org/D26398 llvm-svn: 287349
* GlobalISel: Fix unconditional fallback with global isel abort is disabledTom Stellard2016-11-181-1/+1
| | | | | | | | | | Reviewers: t.p.northover, ab, qcolombet Subscribers: mehdi_amini, vkalintiris, wdng, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D26765 llvm-svn: 287344
* AMDGPU/SI: Remove zero_extend patterns for i16 ops selected to 32-bit instsTom Stellard2016-11-181-3/+14
| | | | | | | | | | | | | | Summary: The 32-bit instructions don't zero the high 16-bits like the 16-bit instructions do. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D26828 llvm-svn: 287342
* [simplifycfg][loop-simplify] Preserve loop metadata in 2 transformations.Florian Hahn2016-11-182-1/+20
| | | | | | | | | | | | | insertUniqueBackedgeBlock in lib/Transforms/Utils/LoopSimplify.cpp now propagates existing llvm.loop metadata to newly the added backedge. llvm::TryToSimplifyUncondBranchFromEmptyBlock in lib/Transforms/Utils/Local.cpp now propagates existing llvm.loop metadata to the branch instructions in the predecessor blocks of the empty block that is removed. Differential Revision: https://reviews.llvm.org/D26495 llvm-svn: 287341
* Cleanup function with clang-format. NFCI.Simon Pilgrim2016-11-181-3/+1
| | | | llvm-svn: 287340
* AMDGPU: Fix legalization of MUBUF instructions in shadersNicolai Haehnle2016-11-181-5/+13
| | | | | | | | | | | | | | | | | | | | | | Summary: The addr64-based legalization is incorrect for MUBUF instructions with idxen set as well as for BUFFER_LOAD/STORE_FORMAT_* instructions. This affects e.g. shaders that access buffer textures. Since we never actually need the addr64-legalization in shaders, this patch takes the easy route and keys off the calling convention. If this ever affects (non-OpenGL) compute, the type of legalization needs to be chosen based on some TSFlag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98664 Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26747 llvm-svn: 287339
* Fix spelling mistakes in MIPS target comments. NFC.Simon Pilgrim2016-11-183-4/+4
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287338
* [Power9] Add patterns for vnegd, vnegwEhsan Amiri2016-11-181-2/+7
| | | | | | | Exploit new instructions by adding patterns to .td file. https://reviews.llvm.org/D26551 llvm-svn: 287334
* Fix spelling mistakes in AMDGPU target comments. NFC.Simon Pilgrim2016-11-185-11/+11
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287333
* Fix typo in comment. NFC.Simon Pilgrim2016-11-181-1/+1
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287331
* [PPC][DAGCombine] Convert SETCC to subtract when the result is zero extendedEhsan Amiri2016-11-182-1/+88
| | | | | | | | | | | | | | | | | When we see a SETCC whose only users are zero extend operations, we can replace it with a subtraction. This results in doing all calculations in GPRs and avoids CR use. Currently we do this only for ULT, ULE, UGT and UGE condition codes. There are ways that this can be extended. For example for signed condition codes. In that case we will be introducing additional sign extend instructions, so more careful profitability analysis may be required. Another direction to extend this is for equal, not equal conditions. Also when users of SETCC are any_ext or sign_ext, we might be able to do something similar. llvm-svn: 287329
* [InstCombine][AVX-512] Teach InstCombineCalls how to handle the intrinsics ↵Craig Topper2016-11-181-0/+18
| | | | | | | | for variable shift with 16-bit elements. This is a straightforward extension of the existing support for 32/64-bit element types. Just needed to add the additional instrinsics to the switches. llvm-svn: 287316
* [AVX-512] Replace masked 16-bit element variable shift intrinsics with new ↵Craig Topper2016-11-182-25/+36
| | | | | | | | | | unmasked versions and selects. The same thing was done to 32-bit and 64-bit element sizes previously. This will allow us to support these shuffls in InstCombineCalls along with the other variable shift intrinsics. llvm-svn: 287312
* AMDGPU: Move redundant setting of inst propertiesMatt Arsenault2016-11-181-3/+1
| | | | llvm-svn: 287311
* AMDGPU: Fix crash on illegal type for inlineasmMatt Arsenault2016-11-181-0/+2
| | | | | | | There are still crashes on non-MVT types in other places. llvm-svn: 287310
* Object: Simplify; remove unnecessary use of unique_ptr.Peter Collingbourne2016-11-181-4/+4
| | | | llvm-svn: 287305
* MachineOperand: Add dump() methodMatthias Braun2016-11-181-0/+6
| | | | llvm-svn: 287302
* convert bpf assembler to look like kernel verifier outputAlexei Starovoitov2016-11-183-57/+69
| | | | | | | | | | since bpf instruction set was introduced people learned to read and understand kernel verifier output whereas llvm asm output stayed obscure and unknown. Convert llvm to emit assembler text similar to kernel to avoid this discrepancy Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 287300
* [AVX-512] Support FCOPYSIGN for v16f32 and v8f64Craig Topper2016-11-181-1/+2
| | | | | | | | | | | | | | | Summary: This extends FCOPYSIGN support to 512-bit vectors. I've also added tests to show what the 128-bit and 256-bit cases look like with broadcast loads. Reviewers: delena, zvi, RKSimon, spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26791 llvm-svn: 287298
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-179-12/+12
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287248
* Fix spelling mistakes in X86 target comments. NFC.Simon Pilgrim2016-11-173-5/+5
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287247
* [asan] Turn on Mach-O global metadata liveness tracking by defaultAnna Zaks2016-11-171-1/+1
| | | | | | | | | | | | | | | | This patch turns on the metadata liveness tracking since all known issues have been resolved. The future has been implemented in https://reviews.llvm.org/D16737 and enables support of dead code stripping option on Mach-O platforms. As part of enabling the feature, I also plan on reverting the following patch to compiler-rt: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160704/369910.html Differential Revision: https://reviews.llvm.org/D26772 llvm-svn: 287235
* Revert "AMDGPU: Enable ConstrainCopy DAG mutation"Konstantin Zhuravlyov2016-11-171-3/+0
| | | | | | | | This reverts commit r287146. This breaks few conformance tests. llvm-svn: 287233
* [SCEV] limit recursion depth of CompareSCEVComplexityDaniil Fukalov2016-11-171-17/+44
| | | | | | | | | | | | | | | Summary: CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled loop) and runs almost infinite time. Added cache of "equal" SCEV pairs to earlier cutoff of further estimation. Recursion depth limit was also introduced as a parameter. Reviewers: sanjoy Subscribers: mzolotukhin, tstellarAMD, llvm-commits Differential Revision: https://reviews.llvm.org/D26389 llvm-svn: 287232
* Wdocumentation fixSimon Pilgrim2016-11-171-5/+5
| | | | llvm-svn: 287224
* [X86][SSE] Improve lowering of vXi64 multiply with known zero 32-bit halvesSimon Pilgrim2016-11-171-19/+43
| | | | | | | | | | | | | | vXi64 multiplication is lowered into 3 calls of vpmuludq with the upper/lower 32-bit halves. If any of these halves are zero then we can remove individual calls. Although there was isBuildVectorAllZeros code to do this I don't think it ever worked (maybe just for constant folded cases that don't seem to be tested for any longer). This requires additional X86ISD support for computeKnownBitsForTargetNode, so far I've just added support for X86ISD::VZEXT (VPMOVZX* - helping the AVX2+ cases). Partial fix for PR30845 Differential Revision: https://reviews.llvm.org/D26590 llvm-svn: 287223
* Fix spelling in comment. NFC.Simon Pilgrim2016-11-171-1/+1
| | | | llvm-svn: 287222
* [ARM] Relax restriction on variadic functions for tailcall optimizationPablo Barrio2016-11-171-5/+0
| | | | | | | | | | | | | | Summary: Variadic functions can be treated in the same way as normal functions with respect to the number and types of parameters. Reviewers: grosbach, olista01, t.p.northover, rengolin Subscribers: javed.absar, aemerson, llvm-commits Differential Revision: https://reviews.llvm.org/D26748 llvm-svn: 287219
* [X86] RegCall - Handling v64i1 in 32/64 bit targetOren Ben Simhon2016-11-175-91/+357
| | | | | | | | | | Register Calling Convention defines a new behavior for v64i1 types. This type should be saved in GPR. However for 32 bit machine we need to split the value into 2 GPRs (because each is 32 bit). Differential Revision: https://reviews.llvm.org/D26181 llvm-svn: 287217
* Delete dead code and add asserts instead; NFCSanjoy Das2016-11-171-7/+3
| | | | llvm-svn: 287214
* [ImplicitNullCheck] Fix an edge case where we were hoisting incorrectlySanjoy Das2016-11-171-1/+19
| | | | | | | | | | | | | | | ImplicitNullCheck keeps track of one instruction that the memory operation depends on that it also hoists with the memory operation. When hoisting this dependency, it would sometimes clobber a live-in value to the basic block we were hoisting the two things out of. Fix this by explicitly looking for such dependencies. I also noticed two redundant checks on `MO.isDef()` in IsMIOperandSafe. They're redundant since register MachineOperands are either Defs or Uses -- there is no third kind. I'll change the checks to asserts in a later commit. llvm-svn: 287213
* [X86] Fix formatting. NFCCraig Topper2016-11-171-2/+2
| | | | llvm-svn: 287211
* [XRay] Support AArch64 in LLVMDean Michael Berris2016-11-173-1/+126
| | | | | | | | | | | | | | | | | | This patch adds XRay support in LLVM for AArch64 targets. This patch is one of a series: Clang: https://reviews.llvm.org/D26415 compiler-rt: https://reviews.llvm.org/D26413 Author: rSerge Reviewers: rengolin, dberris Subscribers: amehsan, aemerson, llvm-commits, iid_iunknown Differential Revision: https://reviews.llvm.org/D26412 llvm-svn: 287209
* [CMake] NFC. Updating CMake dependency specificationsChris Bieneman2016-11-1722-44/+66
| | | | | | This patch updates a bunch of places where add_dependencies was being explicitly called to add dependencies on intrinsics_gen to instead use the DEPENDS named parameter. This cleanup is needed for a patch I'm working on to add a dependency debugging mode to the build system. llvm-svn: 287206
* [AMDGPU] Custom lower f16 = fp_round f64Konstantin Zhuravlyov2016-11-172-0/+23
| | | | llvm-svn: 287203
* [AMDGPU] Promote f16/i16 conversions to f32/i32Konstantin Zhuravlyov2016-11-172-58/+8
| | | | llvm-svn: 287201
* [AMDGPU] Expand `br_cc` for f16Konstantin Zhuravlyov2016-11-171-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26732 llvm-svn: 287199
* Use profile info to adjust loop unroll threshold.Dehao Chen2016-11-172-0/+52
| | | | | | | | | | | | | | Summary: For flat loop, even if it is hot, it is not a good idea to unroll in runtime, thus we set a lower partial unroll threshold. For hot loop, we set a higher unroll threshold and allows expensive tripcount computation to allow more aggressive unrolling. Reviewers: davidxl, mzolotukhin Subscribers: sanjoy, mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D26527 llvm-svn: 287186
* Introduce GlobalSplit pass.Peter Collingbourne2016-11-164-0/+171
| | | | | | | | | This pass splits globals into elements using inrange annotations on getelementptr indices. Differential Revision: https://reviews.llvm.org/D22295 llvm-svn: 287178
* [AVR] Wrap all methods in the pseudo expansion pass in an anon namespaceDylan McKay2016-11-161-2/+2
| | | | | | | The '-fpermissive' compiler flag complains if the template specializations used in the class are used in a different namespace. llvm-svn: 287176
* [AVR] Remove unused method from AVRTargetMachineDylan McKay2016-11-161-3/+0
| | | | llvm-svn: 287173
* [x86] allow FP-logic ops when one operand is FP and result is FPSanjay Patel2016-11-161-14/+26
| | | | | | | | | | | | | | We save an inter-register file move this way. If there's any CPU where the FP logic is slower, we could transform this back to int-logic in MachineCombiner. This helps, but doesn't solve, PR6137: https://llvm.org/bugs/show_bug.cgi?id=6137 The 'andn' test shows that we're missing a pattern match to recognize the xor with -1 constant as a 'not' op. llvm-svn: 287171
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