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* 80-colNadav Rotem2013-02-141-1/+2
| | | | llvm-svn: 175189
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
| | | | | | This patch doesn't introduce any functionality changes. llvm-svn: 175187
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-142-6/+150
| | | | | | | | inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
| | | | | | | | This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175182
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
| | | | | | | | | This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175180
* AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover2013-02-141-4/+4
| | | | llvm-svn: 175176
* Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola2013-02-141-40/+19
| | | | llvm-svn: 175173
* AArch64: stop claiming that NEON registers are usable for now.Tim Northover2013-02-141-11/+0
| | | | | | | | | | If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. llvm-svn: 175172
* AArch64: add block comments where missingTim Northover2013-02-1419-11/+86
| | | | | | Only comments affected. No code change at all. llvm-svn: 175169
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-4/+8
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Workaround an MSan false positive.Evgeniy Stepanov2013-02-141-0/+2
| | | | llvm-svn: 175156
* Add some legality checks for SETCC before introducing it in the DAG combiner ↵Owen Anderson2013-02-141-2/+6
| | | | | | post-operand legalization. llvm-svn: 175149
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-3/+17
| | | | | | Added a test. llvm-svn: 175144
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
| | | | | | | Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. llvm-svn: 175139
* Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola2013-02-142-1/+7
| | | | llvm-svn: 175133
* RegisterCoalescer::reMaterializeTrivialDef() can constrain the destinationCameron Zwarich2013-02-141-1/+1
| | | | | | register class to match the defining instruction. llvm-svn: 175130
* Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky2013-02-141-8/+30
| | | | | | 'and' instructions. This is a pattern that shows up a lot in ubsan binaries. llvm-svn: 175128
* Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-143-87/+73
| | | | | | | | | up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
* Fix RegisterCoalescer::rematerializeTrivialDef() so that it works on flippedCameron Zwarich2013-02-141-10/+10
| | | | | | | CoalescerPairs. Also, make it take a CoalescerPair directly like other methods of RegisterCoalescer. llvm-svn: 175123
* Fix some issues with rematerialization in RegisterCoalescer when the destinationCameron Zwarich2013-02-141-0/+10
| | | | | | | | | | | | of the copy is a subregister def. The current code assumes that it can do a full def of the destination register, but it is not checking that the def operand is read-undef. It also doesn't clear the subregister index of the destination in the new instruction to reflect the full subregister def. These issues were found running 'make check' with my next commit that enables rematerialization in more cases. llvm-svn: 175122
* Don't assume the mangling of static functions.Rafael Espindola2013-02-141-6/+0
| | | | llvm-svn: 175121
* Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola2013-02-141-1/+1
| | | | | | | | | | | | | | Since functions with internal linkage don't have language linkage, it is valid to overload them: extern "C" { static int foo(); static int foo(int); } So we mangle them. llvm-svn: 175120
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-132-150/+6
| | | | llvm-svn: 175107
* Retain the name of the new internal global that's been shrunk.Bill Wendling2013-02-131-2/+5
| | | | | | | | | It's possible (e.g. after an LTO build) that an internal global may be used for debugging purposes. If that's the case appending a '.b' to it makes it hard to find that variable. Steal the name from the old GV before deleting it so that they can find that variable again. llvm-svn: 175104
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
| | | | llvm-svn: 175102
* R600: Add support for 128-bit parametersTom Stellard2013-02-132-0/+5
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* Don't build tail calls to functions with three inreg arguments on x86-32 PIC.Nick Lewycky2013-02-131-5/+11
| | | | | | Fixes PR15250! llvm-svn: 175092
* Bug fix 13622: Add paired register support for inline asm with 64-bit data ↵Weiming Zhao2013-02-132-6/+150
| | | | | | on ARM llvm-svn: 175088
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-136-1052/+224
| | | | | | instead of redefining separate instructions for them. llvm-svn: 175086
* [ms-inline-asm] Add support for memory references that have non-immediateChad Rosier2013-02-131-13/+18
| | | | | | | displacements. rdar://12974533 llvm-svn: 175083
* [ms-inline asm] Add a comment about the determinism of the rewrite sort.Chad Rosier2013-02-131-0/+2
| | | | llvm-svn: 175082
* LoopVectorize: Simplify code for clarity.Benjamin Kramer2013-02-131-10/+8
| | | | | | No functionality change. llvm-svn: 175076
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-133-3/+46
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* Clean up LDV, no functionality change.Manman Ren2013-02-132-64/+19
| | | | | | | | Remove dead functions: renameRegister Move private member variables from LDV to Impl Remove ssp/uwtable from testing case llvm-svn: 175072
* MIsched: HazardRecognizers are created for each DAG. Free them.Andrew Trick2013-02-132-2/+9
| | | | llvm-svn: 175067
* [ms-inline-asm] Use an array_pod_sort, rather than a std:sort.Chad Rosier2013-02-131-3/+10
| | | | llvm-svn: 175063
* Metadata for annotating loops as parallel. The first consumer for this Pekka Jaaskelainen2013-02-132-0/+58
| | | | | | | | metadata is the loop vectorizer. See the documentation update for more info. llvm-svn: 175060
* Add registration for PPC-specific passes to allow the IR to be dumpedKrzysztof Parzyszek2013-02-133-3/+41
| | | | | | via -print-after-all. llvm-svn: 175058
* X86: Disable generation of rep;movsl when %esi is used as a base pointer.Benjamin Kramer2013-02-131-0/+8
| | | | | | | | | | | This happens when there is both stack realignment and a dynamic alloca in the function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the base pointer and the next register spill will write into oblivion. Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas and freebsd a 4 byte stack alignment. llvm-svn: 175057
* Use array_pod_sort.Bill Wendling2013-02-131-1/+1
| | | | llvm-svn: 175048
* Add some accessor and query methods for retrieving Attribute objects and such.Bill Wendling2013-02-132-0/+45
| | | | llvm-svn: 175046
* Make jumptables work for -staticReed Kotler2013-02-131-0/+2
| | | | llvm-svn: 175044
* Prevent insertion of "vzeroupper" before call that preserves YMM registers, ↵Elena Demikhovsky2013-02-131-0/+10
| | | | | | since a caller uses preserved registers across the call. llvm-svn: 175043
* Check i1 as well as i8 variables for 8 bit registers for x86 inlineEric Christopher2013-02-131-1/+1
| | | | | | assembly. llvm-svn: 175036
* [tsan] disable load widening in ThreadSanitizer modeKostya Serebryany2013-02-131-0/+6
| | | | llvm-svn: 175034
* [asan] fix confusing indentationKostya Serebryany2013-02-131-1/+2
| | | | llvm-svn: 175033
* Fix comment.Eric Christopher2013-02-131-2/+2
| | | | llvm-svn: 175024
* Debug Info: LiveDebugVarible can remove DBG_VALUEs, make sure we emit them back.Manman Ren2013-02-133-14/+16
| | | | | | | | | | | | | | RegisterCoalescer used to depend on LiveDebugVariable. LDV removes DBG_VALUEs without emitting them at the end. We fix this by removing LDV from RegisterCoalescer. Also add an assertion to make sure we call emitDebugValues if DBG_VALUEs are removed at runOnMachineFunction. rdar://problem/13183203 Reviewed by Andy & Jakob llvm-svn: 175023
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