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* Expand VMOVQQQQ pseudo instructions.Bob Wilson2011-08-131-0/+46
| | | | | | | Apparently we never added code to expand these pseudo instructions, and in over a year, no one has noticed. Our register allocator must be awesome! llvm-svn: 137551
* Remove the last improper use of getGlobalContext() from LLVM.Nick Lewycky2011-08-131-18/+1
| | | | | | | | | | | | This caused a race condition where a thread calls ~LLVMContextImpl which calls Module::dropAllReferences which calls begin() on an empty ilist that would create the sentinel, which racily accesses the global context. This can not be fixed by locking inside createSentinel because the lock would need to be shared with all users of the global context, including those that reside outside LLVM's own code. llvm-svn: 137546
* Move "atomic" and "volatile" designations on instructions after the opcodeEli Friedman2011-08-123-48/+83
| | | | | | | | | | of the instruction. Note that this change affects the existing non-atomic load and store instructions; the parser now accepts both forms, and the change is noted in the release notes. llvm-svn: 137527
* ARM STR_POST_IMM offset encoding fix in load/store optimizer.Jim Grosbach2011-08-121-13/+10
| | | | | | | | | Tidy up the code a bit and push the definition of the value next to the uses to try to minimize this sort of issue from arising again while I'm at it. rdar://9945172 llvm-svn: 137525
* Fix comment!Bruno Cardoso Lopes2011-08-121-3/+3
| | | | llvm-svn: 137521
* The VPERM2F128 is a AVX instruction which permutes between two 256-bitBruno Cardoso Lopes2011-08-127-0/+132
| | | | | | | | vectors. It operates on 128-bit elements instead of regular scalar types. Recognize shuffles that are suitable for VPERM2F128 and teach the x86 legalizer how to handle them. llvm-svn: 137519
* Move code around and add commentsBruno Cardoso Lopes2011-08-121-11/+13
| | | | llvm-svn: 137518
* Define unaligned load and store. Akira Hatanaka2011-08-124-2/+35
| | | | llvm-svn: 137515
* ARM expansion of pre-indexed store pseudos should maintain memoperands.Jim Grosbach2011-08-121-1/+3
| | | | | | Partial fix for rdar://9945172. llvm-svn: 137513
* Add checks for the landingpad instruction's clause values to make sure thatBill Wendling2011-08-121-0/+10
| | | | | | they're the correct type. llvm-svn: 137511
* Fix some remaining issues with decoding ARM-mode memory instructions, and ↵Owen Anderson2011-08-122-20/+12
| | | | | | add another batch of tests. llvm-svn: 137502
* Initial commit of the 'landingpad' instruction.Bill Wendling2011-08-1215-10/+303
| | | | | | | | | | | | This implements the 'landingpad' instruction. It's used to indicate that a basic block is a landing pad. There are several restrictions on its use (see LangRef.html for more detail). These restrictions allow the exception handling code to gather the information it needs in a much more sane way. This patch has the definition, implementation, C interface, parsing, and bitcode support in it. llvm-svn: 137501
* Fix decoding of ARM-mode STRH.Owen Anderson2011-08-123-0/+6
| | | | llvm-svn: 137499
* Specify fixed bit in the LDRBT encoding, which allows us to distinguish it ↵Owen Anderson2011-08-121-1/+3
| | | | | | from certain USAT16 encodings. llvm-svn: 137494
* Fix decoding of pre-indexed stores.Owen Anderson2011-08-122-0/+43
| | | | llvm-svn: 137487
* Use ArrayRef.Devang Patel2011-08-121-6/+6
| | | | llvm-svn: 137485
* When constant double 0.0 is lowered, make sure 0 is copied directly from an Akira Hatanaka2011-08-121-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | integer register to a floating point register. It is not valid to interpret the value of a floating pointer register as part of a double precision floating point value after a single precision floating point computational or move instruction stores its result to the register. - In the test case, the following code is generated before this patch is applied: mtc1 $zero, $f2 ; unformatted copy to $f2 mov.s $f0, $f2 ; $f0 is in single format sdc1 $f12, 0($sp) mov.s $f1, $f2 ; $f1 is in single format c.eq.d $f12, $f0 ; $f0 cannot be interpreted as double - The following code is generated after this patch is applied: mtc1 $zero, $f0 ; unformatted copy to $f0 mtc1 $zero, $f1 ; unformatted copy to $f1 c.eq.d $f12, $f0 ; $f0 can be interpreted as double Bhanu Chetlapalli and Chris Dearman at MIPS technologies reported this bug and provided the test case. llvm-svn: 137484
* add ifdef's to let people easily remove these dead api for testing.Chris Lattner2011-08-121-8/+10
| | | | llvm-svn: 137483
* switch to the new struct api.Chris Lattner2011-08-121-3/+3
| | | | llvm-svn: 137482
* switch to the new struct apis.Chris Lattner2011-08-124-9/+9
| | | | llvm-svn: 137481
* switch to use the new api for structtypes.Chris Lattner2011-08-127-18/+18
| | | | llvm-svn: 137480
* forward to the correct constructor.Chris Lattner2011-08-121-3/+2
| | | | llvm-svn: 137479
* Provide fast path as Jakob suggested.Devang Patel2011-08-121-0/+12
| | | | llvm-svn: 137478
* Separate decoding for STREXD and LDREXD to make each work better.Owen Anderson2011-08-122-7/+24
| | | | llvm-svn: 137476
* add two missing function implsChris Lattner2011-08-121-0/+11
| | | | llvm-svn: 137470
* add new accessors to reflect new terminology in struct types.Chris Lattner2011-08-121-2/+44
| | | | llvm-svn: 137468
* Revert r137310 because it does not optimize any code on ToTNadav Rotem2011-08-121-32/+0
| | | | llvm-svn: 137466
* Whitespace and formatting. No functional change intended.Chad Rosier2011-08-121-10/+9
| | | | llvm-svn: 137463
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-1218-14/+29
| | | | | | when building with assertions disabled. llvm-svn: 137460
* MachOWriter: Don't crash on fixups with arithmetic, emit a relocation ↵Benjamin Kramer2011-08-121-2/+6
| | | | | | instead. This matches what as does. llvm-svn: 137414
* findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.Andrew Trick2011-08-121-2/+2
| | | | | | Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it. llvm-svn: 137404
* Don't convert objc_autoreleaseReturnValue to objc_autorelease if the resultDan Gohman2011-08-121-6/+13
| | | | | | is returned through a bitcast. llvm-svn: 137402
* Don't let arbitrary calls disrupt nested retain+release pairs ifDan Gohman2011-08-121-56/+78
| | | | | | | | | the retains and releases all use the same SSA pointer value. Also, don't let CFG hazards disrupt nested retain+release pair optimizations. llvm-svn: 137399
* Use an actual reverse-CFG reverse-postorder for the bottom-up traversal,Dan Gohman2011-08-121-16/+30
| | | | | | | rather than plain postorder, so that CFG constructs like single-exit loops are reliably visited in a sensible order. llvm-svn: 137398
* Simplify the interference checking code a bit.Jakob Stoklund Olesen2011-08-122-112/+42
| | | | | | | This is possible now that we now longer provide an interface to iterate the interference overlaps. llvm-svn: 137397
* ARM vector compare to zero instruction assembly parsing support.Jim Grosbach2011-08-111-0/+15
| | | | llvm-svn: 137389
* Allow loop unrolling to get known trip counts from ScalarEvolution.Andrew Trick2011-08-112-7/+80
| | | | | | | | | | | | | SCEV unrolling can unroll loops with arbitrary induction variables. It is a prerequisite for -disable-iv-rewrite performance. It is also easily handles loops of arbitrary structure including multiple exits and is generally more robust. This is under a temporary option to avoid affecting default behavior for the next couple of weeks. It is needed so that I can checkin unit tests for updateUnloop. llvm-svn: 137384
* Remove the InterferenceResult class.Jakob Stoklund Olesen2011-08-111-32/+0
| | | | llvm-svn: 137381
* Eliminate the last use of InterferenceResult.Jakob Stoklund Olesen2011-08-112-63/+57
| | | | | | | | The Query class now holds two iterators instead of an InterferenceResult instance. The iterators are used as bookmarks for repeated collectInterferingVRegs calls. llvm-svn: 137380
* Enclose directive .cprestore with .set macro and nomacro to silence assemblerAkira Hatanaka2011-08-111-3/+9
| | | | | | warning. llvm-svn: 137378
* Remove no-longer-true comments. These are for the assembler, also.Jim Grosbach2011-08-111-52/+24
| | | | llvm-svn: 137375
* ARM STRT assembly parsing and encoding.Jim Grosbach2011-08-112-14/+30
| | | | llvm-svn: 137372
* Make the USAT16 operand decoder auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137371
* Add another accidentally omitted predicate operand.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137370
* Add missing predicate operand on SMLA and friends.Owen Anderson2011-08-111-0/+2
| | | | llvm-svn: 137368
* ARM load shifted register pre-index fix shift value asm parser encoding.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137367
* Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.Owen Anderson2011-08-111-2/+4
| | | | llvm-svn: 137364
* Making SEL decodings auto-generate-able.Owen Anderson2011-08-111-2/+2
| | | | llvm-svn: 137363
* Add a dag combine to xform 256-bit shuffles into simple vectorBruno Cardoso Lopes2011-08-111-1/+54
| | | | | | | inserts and extracts. This simple combine makes us generate only 1 instruction instead of 11 in the v8 case. llvm-svn: 137362
* Tidy up comment.Jim Grosbach2011-08-111-2/+1
| | | | llvm-svn: 137359
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