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* [TTI][X86] update costs of interleaved load\store of i64\doubleMohammed Agabaria2017-11-161-0/+6
| | | | | | | | | | | | This patch contains more accurate cost of interelaved load\store of stride 2 for the types int64\double on AVX2. Reviewers: delena, RKSimon, craig.topper, dorit Reviewed By: dorit Differential Revision: https://reviews.llvm.org/D40008 llvm-svn: 318385
* [MachineRegisterInfo] Avoid having dbg.values affect code generationMikael Holmen2017-11-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Use use_nodbg_empty() rather than use_empty() in MachineRegisterInfo::EmitLiveInCopies() when determining if a livein register has any uses or not. Otherwise a single dbg.value can make us generate different code, meaning -g would affect code generation. Found when compiling code for my out-of-tree target. Unfortunately I haven't been able to reproduce the problem on X86 or any of the other in-tree targets that I tried, so no test case. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39044 llvm-svn: 318382
* [IRCE] Fix SCEVExpander's usage in IRCEMax Kazantsev2017-11-161-0/+14
| | | | | | | | | | | | When expanding exit conditions for pre- and postloops, we may end up expanding a recurrency from the loop to in its loop's preheader. This produces incorrect IR. This patch ensures that IRCE uses SCEVExpander correctly and only expands code which is safe to expand in this particular location. Differentian Revision: https://reviews.llvm.org/D39234 llvm-svn: 318381
* [X86] Update TTI to report that v1iX/v1fX types aren't legal for masked ↵Craig Topper2017-11-161-2/+10
| | | | | | | | gather/scatter/load/store. The type legalizer will try to scalarize these operations if it sees them, but there is no handling for scalarizing them. This leads to a fatal error. With this change they will now be scalarized by the mem intrinsic scalarizing pass before SelectionDAG. llvm-svn: 318380
* [SelectionDAG] Use report_fatal_error instead of llvm_unreachable in some ↵Craig Topper2017-11-161-1/+2
| | | | | | | | | | code that can be reached if targets don't configure things correctly. For example, this is currently reachable by X86 if you use a masked store intrinsic with a v1iX type. Using a fatal error seems like a better user experience if someone were to encounter this on a release build. There are several other similar places that have been converted from unreachable to fatal error previously. llvm-svn: 318379
* [SCEV][NFC] Introduce isSafeToExpandAt function to SCEVExpanderMax Kazantsev2017-11-161-0/+5
| | | | | | | | | | | This function checks that: 1) It is safe to expand a SCEV; 2) It is OK to materialize it at the specified location. For example, attempt to expand a loop's AddRec to the same loop's preheader should fail. Differential Revision: https://reviews.llvm.org/D39236 llvm-svn: 318377
* Fix thinko in last commit.Eric Christopher2017-11-161-1/+1
| | | | llvm-svn: 318374
* Add NDEBUG checks around LLVM_DUMP_METHOD functions for Wunused-function ↵Eric Christopher2017-11-162-2/+8
| | | | | | warnings. llvm-svn: 318373
* Fix APInt bit size in processDbgDeclaresYaxun Liu2017-11-161-1/+1
| | | | | | | | | | | | | processDbgDeclares assumes pointer size is the same for different addr spaces. It uses pointer size for addr space 0 for all pointers, which causes assertion in stripAndAccumulateInBoundsConstantOffsets for amdgcn---amdgiz since pointer in addr space 5 has different size than in addr space 0. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40085 llvm-svn: 318370
* [asan] Fallback to non-ifunc dynamic shadow on android<22.Evgeniy Stepanov2017-11-161-1/+3
| | | | | | | | | | | | Summary: Android < 22 does not support ifunc. Reviewers: pcc Subscribers: srhines, kubamracek, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40116 llvm-svn: 318369
* [X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup ↵Craig Topper2017-11-161-26/+28
| | | | | | after type legalization. llvm-svn: 318368
* LTO: clarify why we need to gracefully handle sys::fs::rename failuresBob Haarman2017-11-161-7/+9
| | | | | | | | | | | | Reviewers: pcc, rafael Reviewed By: pcc Subscribers: mehdi_amini, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D40094 llvm-svn: 318362
* bpf: enable llvm-objdump to print out symbolized jmp targetYonghong Song2017-11-161-0/+34
| | | | | | | | | | | | | | | | | | Add hook in BPF backend so that llvm-objdump can print out the jmp target with label names, e.g., ... if r1 != 2 goto 6 <LBB0_2> ... goto 7 <LBB0_4> ... LBB0_2: ... LBB0_4: ... Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 318358
* [globalisel][tablegen] Generate rule coverage and use it to identify ↵Daniel Sanders2017-11-168-28/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | untested rules Summary: This patch adds a LLVM_ENABLE_GISEL_COV which, like LLVM_ENABLE_DAGISEL_COV, causes TableGen to instrument the generated table to collect rule coverage information. However, LLVM_ENABLE_GISEL_COV goes a bit further than LLVM_ENABLE_DAGISEL_COV. The information is written to files (${CMAKE_BINARY_DIR}/gisel-coverage-* by default). These files can then be concatenated into ${LLVM_GISEL_COV_PREFIX}-all after which TableGen will read this information and use it to emit warnings about untested rules. This technique could also be used by SelectionDAG and can be further extended to detect hot rules and give them priority over colder rules. Usage: * Enable LLVM_ENABLE_GISEL_COV in CMake * Build the compiler and run some tests * cat gisel-coverage-[0-9]* > gisel-coverage-all * Delete lib/Target/*/*GenGlobalISel.inc* * Build the compiler Known issues: * ${LLVM_GISEL_COV_PREFIX}-all must be generated as a manual step due to a lack of a portable 'cat' command. It should be the concatenation of all ${LLVM_GISEL_COV_PREFIX}-[0-9]* files. * There's no mechanism to discard coverage information when the ruleset changes Depends on D39742 Reviewers: ab, qcolombet, t.p.northover, aditya_nandakumar, rovka Reviewed By: rovka Subscribers: vsk, arsenm, nhaehnle, mgorny, kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D39747 llvm-svn: 318356
* Try to fix WebAssembly build after r318352Reid Kleckner2017-11-161-2/+2
| | | | llvm-svn: 318355
* [GVNHoist] Fix a signed/unsigned comparison warning that occurs in 32-bit ↵Craig Topper2017-11-161-1/+1
| | | | | | | | builds with gcc. std::distance returns ptrdiff_t which is signed. 64-bit builds don't notice because type promotion widens the unsigned first. llvm-svn: 318354
* [CodeGen] Fix the branch probability assertion in r318202Rong Xu2017-11-161-2/+4
| | | | | | | Due to integer precision, we might have numerator greater than denominator in the branch probability scaling. Add a check to prevent this from happening. llvm-svn: 318353
* Add backend name to Target to enable runtime info to be fed back into TableGenDaniel Sanders2017-11-1515-38/+42
| | | | | | | | | | | | | | | | | | | | | | Summary: Make it possible to feed runtime information back to tablegen to enable profile-guided tablegen-eration, detection of untested tablegen definitions, etc. Being a cross-compiler by nature, LLVM will potentially collect data for multiple architectures (e.g. when running 'ninja check'). We therefore need a way for TableGen to figure out what data applies to the backend it is generating at the time. This patch achieves that by including the name of the 'def X : Target ...' for the backend in the TargetRegistry. Reviewers: qcolombet Reviewed By: qcolombet Subscribers: jholewinski, arsenm, jyknight, aditya_nandakumar, sdardis, nemanjai, ab, nhaehnle, t.p.northover, javed.absar, qcolombet, llvm-commits, fedor.sergeev Differential Revision: https://reviews.llvm.org/D39742 llvm-svn: 318352
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-4/+14
| | | | | | Fix the modeling of FP stores. llvm-svn: 318351
* [GISel][NFC]: Move getOpcodeDef from the LegalizationArtifactCombiner into ↵Aditya Nandakumar2017-11-151-0/+16
| | | | | | GlobalISel/Utils for use elsewhere llvm-svn: 318350
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-155-9/+146
| | | | | | | | | | | | | | | Use VOP3 add/addc like usual. This has some tradeoffs. Inline immediates fold a little better, but other constants are worse off. SIShrinkInstructions could be made smarter to handle these cases. This allows us to avoid selecting scalar adds where we need to track the carry in scc and replace its users. This makes it easier to use the carryless VALU adds. llvm-svn: 318340
* [AArch64] Refactor the loads and stores optimizerEvandro Menezes2017-11-151-143/+143
| | | | | | | | | Move remaining inline matching of instructions of some optimizations into separate functions, like in the other optimizations. Otherwise, NFC. Differential revision: https://reviews.llvm.org/D40090 llvm-svn: 318335
* [X86] Add some explanatory comments to the ProcessorFeatures enum in Host.cpp.Craig Topper2017-11-151-1/+4
| | | | llvm-svn: 318331
* [X86] Add a return to the end of a switch to prevent an accidental ↵Craig Topper2017-11-151-0/+1
| | | | | | fallthrough in the future. llvm-svn: 318330
* [InstCombine] trunc (binop X, C) --> binop (trunc X, C')Sanjay Patel2017-11-151-4/+17
| | | | | | | | | Note that one-use and shouldChangeType() are checked ahead of the switch. Without the narrowing folds, we can produce inferior vector code as shown in PR35299: https://bugs.llvm.org/show_bug.cgi?id=35299 llvm-svn: 318323
* Use TempFile in lto caching.Rafael Espindola2017-11-152-30/+46
| | | | | | | | | | This requires a small change to TempFile: allowing a discard after a failed keep. With this the cache now handles signals and reuses a fd instead of reopening the file. llvm-svn: 318322
* [PowerPC] Implement mayBeEmittedAsTailCall for PPCSean Fertile2017-11-152-0/+39
| | | | | | | | | Implements TargetLowering callback 'mayBeEmittedAsTailCall' that enables CodeGenPrepare to duplicate returns when they might enable a tail-call. Differential Revision: https://reviews.llvm.org/D39777 llvm-svn: 318321
* [InstCombine] Salvage debug info during initial DCEReid Kleckner2017-11-151-0/+1
| | | | | | | | | | | InstCombine salvages debug info for every instruction it erases from its worklist, but it wasn't doing it during its initial DCE when populating its worklist. This fixes that. This should help improve availability of 'this' in optimized debug info when casts are necessary. llvm-svn: 318320
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-151-17/+14
| | | | | | | Fix the modeling of loads and stores using the pre or post indexed addressing modes. llvm-svn: 318312
* [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule classSimon Pilgrim2017-11-152-32/+31
| | | | | | | | Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default. Differential Revision: https://reviews.llvm.org/D39899 llvm-svn: 318308
* [SLP] Added more missed optimization remarksAdam Nemet2017-11-151-14/+74
| | | | | | | | | | | | | | | | | | | | Summary: Added more remarks to SLP pass, in particular "missed" optimization remarks. Also proposed several tests for new functionality. Patch by Vladimir Miloserdov! For reference you may look at: https://reviews.llvm.org/rL302811 Reviewers: anemet, fhahn Reviewed By: anemet Subscribers: javed.absar, lattner, petecoup, yakush, llvm-commits Differential Revision: https://reviews.llvm.org/D38367 llvm-svn: 318307
* [PowerPC] Split out the tailcall calling convention checks. NFC.Sean Fertile2017-11-151-11/+19
| | | | | | | | Move the calling convention checks for tail-call eligibility for the 64-bit SysV ABI into a separate function. This is so that it can be shared with 'mayBeEmittedAsTailCall' in a subsequent change. llvm-svn: 318305
* [(new) Pass Manager] instantiate SimplifyCFG with the same options as the old PMSanjay Patel2017-11-151-2/+7
| | | | | | | | | | | | | | | | | | This is a recommit of r316869 which was speculatively reverted with r317444 and subsequently shown to not be the cause of PR35210. That crash should be fixed after r318237. Original commit message: The old PM sets the options of what used to be known as "latesimplifycfg" on the instantiation after the vectorizers have run, so that's what we'redoing here. FWIW, there's a later SimplifyCFGPass instantiation in both PMs where we do not set the "late" options. I'm not sure if that's intentional or not. Differential Revision: https://reviews.llvm.org/D39407 llvm-svn: 318299
* [Reassociate] simplify code; NFCISanjay Patel2017-11-151-6/+3
| | | | llvm-svn: 318298
* [AArch64][SVE] Asm: Report SVE parsing diagnostics only onceSander de Smalen2017-11-151-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Prevent an issue where a diagnostic is reported multiple times by bailing out with a ParseFail if an invalid SVE register element qualifier/suffix is specified, for example: <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ... <stdin>:10:18: error: invalid sve vector kind qualifier add z20.h, z2.h, z31.x ^ Reviewers: fhahn, rengolin Reviewed By: rengolin Subscribers: aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D39894 llvm-svn: 318297
* [mips] Improve genConstMult() to work with arbitrary precisionPetar Jovanovic2017-11-151-11/+9
| | | | | | | | | | | APInt is now used instead of uint64_t in function genConstMult() allowing multiplication optimizations with constants of arbitrary length. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38130 llvm-svn: 318296
* [ARM] Split Arm jump table branch into i12 and rs suffixed versionsMomchil Velikov2017-11-155-210/+33
| | | | | | | | | This is a refactoring/cleanup of Arm `addrmode2` operand class. The patch removes it completely. Differential Revision: https://reviews.llvm.org/D39832 llvm-svn: 318291
* [DebugInfo] Fix potential CU mismatch for SubprogramScopeDIEs.Jonas Devlieghere2017-11-152-8/+17
| | | | | | | | | | | | | | | | | In constructAbstractSubprogramScopeDIE there can be a potential mismatch between `this` and the CU of ContextDIE when a scope is shared between two DISubprograms belonging to a different CU. In that case, `this` is the CU that was specified in the IR, but the CU of ContextDIE is that of the first subprogram that was emitted. This patch fixes the mismatch by looking up the CU of ContextDIE, and switching to use that. This fixes PR35212 (https://bugs.llvm.org/show_bug.cgi?id=35212) Patch by Philip Craig! Differential revision: https://reviews.llvm.org/D39981 llvm-svn: 318289
* [Lint] Don't warn about passing alloca'd value to tail call if using byvalMikael Holmen2017-11-151-8/+17
| | | | | | | | | | | | | | | | | | | Summary: This fixes PR35241. When using byval, the data is effectively copied as part of the call anyway, so the pointer returned by the alloca will not be leaked to the callee and thus there is no reason to issue a warning. Reviewers: rnk Reviewed By: rnk Subscribers: Ka-Ka, llvm-commits Differential Revision: https://reviews.llvm.org/D40009 llvm-svn: 318279
* [X86] Redefine the 128-bit version of VPGATHERQD and VGATHERQPS to use a VK2 ↵Craig Topper2017-11-153-14/+24
| | | | | | | | | | mask instead of a VK4 mask. This allows us to remove extra extend creation during lowering and more accurately reflects the semantics of the instruction. While there add an extra output VT to X86 masked gather node to better match the isel pattern predicate. Currently we're exploiting the fact that the isel table doesn't count how many output results a node actually has if the result type of any can be inferred from the first result and the type constraints defined in tablegen. I think we might ultimately want to lower all MGATHER/MSCATTER to an X86ISD node with the extra mask result and stop relying on this hole in the isel checking. llvm-svn: 318278
* NFC Remove default argument of DataLayout::getPointerABIAlignmentFangrui Song2017-11-153-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D40005 llvm-svn: 318272
* [X86] Add getHostCPUName support for the Gemini Lake model number which also ↵Craig Topper2017-11-151-2/+3
| | | | | | uses Goldmont. llvm-svn: 318271
* [X86] Add getHostCPUName support for cannonlake.Craig Topper2017-11-151-7/+21
| | | | | | This adds an explicit model number check and fallback path to the unknown family 6 detection. llvm-svn: 318270
* [InstCombine] Simplify binops that are only used by a select and are fed by ↵Craig Topper2017-11-151-0/+40
| | | | | | | | | | | | | | | | | | | a select with the same condition. Summary: This patch optimizes a binop sandwiched between 2 selects with the same condition. Since we know its only used by the select we can propagate the appropriate input value from the earlier select. As I'm writing this I realize I may need to avoid doing this for division in case the select was protecting a divide by zero? Reviewers: spatel, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39999 llvm-svn: 318267
* [PowerPC] fix up in redundant compare eliminationHiroshi Inoue2017-11-151-2/+6
| | | | | | This patch fixes a potential problem in my previous commit (https://reviews.llvm.org/rL312514) by introducing an additional check. llvm-svn: 318266
* AMDGPU: Add separate definitions for DS insts without m0 useMatt Arsenault2017-11-151-154/+207
| | | | llvm-svn: 318246
* AMDGPU: Don't use MUBUF vaddr if address may overflowMatt Arsenault2017-11-156-2/+60
| | | | | | | Effectively revert r263964. Before we would not allow this if vaddr was not known to be positive. llvm-svn: 318240
* Revert r318193 "[SLPVectorizer] Failure to beneficially vectorize 'copyable' ↵Hans Wennborg2017-11-151-318/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | elements in integer binary ops." It crashes building sqlite; see reply on the llvm-commits thread. > [SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in integer binary ops. > > Patch tries to improve vectorization of the following code: > > void add1(int * __restrict dst, const int * __restrict src) { > *dst++ = *src++; > *dst++ = *src++ + 1; > *dst++ = *src++ + 2; > *dst++ = *src++ + 3; > } > Allows to vectorize even if the very first operation is not a binary add, but just a load. > > Fixed issues related to previous commit. > > Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev > > Reviewed By: ABataev, RKSimon > > Subscribers: llvm-commits, RKSimon > > Differential Revision: https://reviews.llvm.org/D28907 llvm-svn: 318239
* [LoopRotate] processLoop should return true even if it just simplified the ↵Craig Topper2017-11-151-1/+1
| | | | | | | | | | | | | | loop latch without making any other changes Simplifying a loop latch changes the IR and we need to make sure the pass manager knows to invalidate analysis passes if that happened. PR35210 discovered a case where we failed to invalidate the post dominator tree after this simplification because we no changes other than simplifying the loop latch. Fixes PR35210. Differential Revision: https://reviews.llvm.org/D40035 llvm-svn: 318237
* [asan] Prevent rematerialization of &__asan_shadow.Evgeniy Stepanov2017-11-151-12/+30
| | | | | | | | | | | | | | | | | | | | Summary: In the mode when ASan shadow base is computed as the address of an external global (__asan_shadow, currently on android/arm32 only), regalloc prefers to rematerialize this value to save register spills. Even in -Os. On arm32 it is rather expensive (2 loads + 1 constant pool entry). This changes adds an inline asm in the function prologue to suppress this behavior. It reduces AsanTest binary size by 7%. Reviewers: pcc, vitalybuka Subscribers: aemerson, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40048 llvm-svn: 318235
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