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* PowerPC: Remove ADDIL patterns.Ulrich Weigand2013-03-264-20/+13
| | | | | | | | | | | | | | The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L, which describe the same instruction, except that they accept a symbolLo[64] operand instead of a s16imm[64] operand. This duplication confuses the asm parser, and it actually not really needed, since symbolLo[64] already accepts immediate operands anyway. So this commit removes the duplicate patterns. No change in generated code. llvm-svn: 178004
* PowerPC: Use CCBITRC operand for ISEL patterns.Ulrich Weigand2013-03-265-46/+19
| | | | | | | | | | | | This commit changes the ISEL patterns to use a CCBITRC operand instead of a "pred" operand. This matches the actual instruction text more directly, and simplifies use of ISEL with the asm parser. In addition, this change allows some simplification of handling the "pred" operand, as this is now only used by BCC. No change in generated code. llvm-svn: 178003
* PowerPC: Simplify BLR pattern.Ulrich Weigand2013-03-263-12/+6
| | | | | | | | | | | | | | | | | The BLR pattern cannot be recognized by the asm parser in its current form. This complexity is due to an apparent attempt to enable conditional BLR variants. However, none of those can ever be generated by current code; the pattern is only ever created using the default "pred" operand. To simplify the pattern and allow it to be recognized by the parser, this commit removes those attempts at conditional BLR support. When we later come back to actually add real conditional BLR, this should probably be done via a fully generic conditional branch pattern. No change in generated code. llvm-svn: 178002
* PowerPC: Move some 64-bit branch patterns.Ulrich Weigand2013-03-261-17/+18
| | | | | | | | | | | | In PPCInstr64Bit.td, some branch patterns appear in a different sequence than the corresponding 32-bit patterns in PPCInstrInfo.td. To simplify future changes that affect both files, this commit moves those patterns to rearrange them into a similar sequence. No effect on generated code. llvm-svn: 178001
* R600: fix DenseMap with pointer key iteration in the structurizerChristian Konig2013-03-261-2/+4
| | | | | | | | | Use a MapVector on types where the iteration order matters. Otherwise we doesn't always produce a deterministic output. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 177999
* Fix SCEV forgetMemoizedResults should search and destroy backedge exprs.Andrew Trick2013-03-261-0/+30
| | | | | | | | | | | | | | | Fixes PR15570: SEGV: SCEV back-edge info invalid after dead code removal. Indvars creates a SCEV expression for the loop's back edge taken count, then determines that the comparison is always true and removes it. When loop-unroll asks for the expression, it contains a NULL SCEVUnknkown (as a CallbackVH). forgetMemoizedResults should invalidate the loop back edges expression. llvm-svn: 177986
* Split out the IRReader header and the utility functions it provides intoChandler Carruth2013-03-267-2/+121
| | | | | | | | | | | | | | | | | | | | | | | | its own library. These functions are bridging between the bitcode reader and the ll parser which are in different libraries. Previously we didn't have any good library to do this, and instead played fast and loose with a "header only" set of interfaces in the Support library. This really doesn't work well as evidenced by the recent attempt to add timing logic to the these routines. As part of this, make them normal functions rather than weird inline functions, and sink the implementation into the library. Also clean up the header to be nice and minimal. This requires updating lots of build system dependencies to specify that the IRReader library is needed, and several source files to not implicitly rely upon the header file to transitively include all manner of other headers. If you are using IRReader.h, this commit will break you (the header moved) and you'll need to also update your library usage to include 'irreader'. I will commit the corresponding change to Clang momentarily. llvm-svn: 177971
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-264-24/+70
| | | | | | | | Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. llvm-svn: 177968
* ARM Scheduler Model: Partial implementation of the new machine scheduler modelArnold Schwaighofer2013-03-261-0/+57
| | | | | | | | | | This is very much work in progress. Please send me a note if you start to depend on the added abstract read/write resources. They are subject to change until further notice. The old itinerary is still the default. llvm-svn: 177967
* Add missing file to cmake build.Nick Lewycky2013-03-261-0/+1
| | | | llvm-svn: 177963
* Add a new watchdog timer interface. The interface does not permit handling ↵Nick Lewycky2013-03-265-1/+86
| | | | | | | | | timeouts, so it's only really useful if you're going to crash anyways. Use it in the pretty stack trace printer to kill the compiler if we hang while printing the stack trace. llvm-svn: 177962
* [ObjCARC Annotations] Added support for displaying the state of pointers at ↵Michael Gottesman2013-03-262-4/+147
| | | | | | | | | | | | | | | | | | | | | | | the bottom/top of BBs of the ARC dataflow analysis for both bottomup and topdown analyses. This will allow for verification and analysis of the merge function of the data flow analyses in the ARC optimizer. The actual implementation of this feature is by introducing calls to the functions llvm.arc.annotation.{bottomup,topdown}.{bbstart,bbend} which are only declared. Each such call takes in a pointer to a global with the same name as the pointer whose provenance is being tracked and a pointer whose name is one of our Sequence states and points to a string that contains the same name. To ensure that the optimizer does not consider these annotations in any way, I made it so that the annotations are considered to be of IC_None type. A test case is included for this commit and the previous ObjCARCAnnotation commit. llvm-svn: 177952
* [ObjCARC Annotations] Implemented ARC annotation metadata to expose the ARC ↵Michael Gottesman2013-03-261-5/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | data flow analysis state in the IR via metadata. Previously the inner works of the data flow analysis in ObjCARCOpts was hard to get out of the optimizer for analysis of bugs or testing. All of the current ARC unit tests are based off of testing the effect of the data flow analysis (i.e. what statements are removed or moved, etc.). This creates weakness in the current unit testing regimem since we are not actually testing what effects various instructions have on the modeled pointer state. Additionally in order to analyze a bug in the optimizer, one would need to track by hand what the optimizer was actually doing either through use of DEBUG statements or through the usage of a debugger, both yielding large loses in developer productivity. This patch deals with these two issues by providing ARC annotation metadata that annotates instructions with the state changes that they cause in various pointers as well as provides metadata to annotate provenance sources. Specifically, we introduce the following metadata types: 1. llvm.arc.annotation.bottomup. 2. llvm.arc.annotation.topdown. 3. llvm.arc.annotation.provenancesource. llvm.arc.annotation.{bottomup,topdown}: These annotations describes a state change in a pointer when we are visiting instructions bottomup/topdown respectively. The output format for both is the same: !1 = metadata !{metadata !"(test,%x)", metadata !"S_Release", metadata !"S_Use"} The first element is a string tuple with the following format: (function,variable name) The second two elements of the metadata show the previous state of the pointer (in this case S_Release) and the new state of the pointer (S_Use). We write the metadata in such a manner to ensure that it is easy for outside tools to parse. This is important since I am currently working on a tool for taking this information and pretty printing it besides the IR and that can be used for LIT style testing via the generation of an index. llvm.arc.annotation.provenancesource: This metadata is used to annotate instructions which act as provenance sources, i.e. ones that introduce a new (from the optimizer's perspective) non-argument pointer to track. This enables cross-referencing in between provenance sources and the state changes that occur to them. This is still a work in progress. Additionally I plan on committing later today additions to the annotations that annotate at the top/bottom of basic blocks the state of the various pointers being tracked. *NOTE* The metadata support is conditionally compiled into libObjCARCOpts only when we are producing a debug build of llvm/clang and even so are disabled by default. To enable the annotation metadata, pass in -enable-objc-arc-annotations to opt. llvm-svn: 177951
* Revise alignment checking/calculation on 256-bit unaligned memory accessMichael Liao2013-03-251-7/+6
| | | | | | | | | - It's still considered aligned when the specified alignment is larger than the natural alignment; - The new alignment for the high 128-bit vector should be min(16, alignment) as the pointer is advanced by 16, a power-of-2 offset. llvm-svn: 177947
* Enhance folding of (extract_subvec (insert_subvec V1, V2, IIdx), EIdx)Michael Liao2013-03-251-21/+29
| | | | | | | | - Handle the case where the result of 'insert_subvect' is bitcasted before 'extract_subvec'. This removes the redundant insertf128/extractf128 pair on unaligned 256-bit vector load/store on vectors of non 64-bit integer. llvm-svn: 177945
* Add a scheduling model for Intel Sandy Bridge microarchitecture.Jakob Stoklund Olesen2013-03-251-0/+123
| | | | | | | The model isn't hooked up by this patch because the instruction set isn't fully annotated yet. llvm-svn: 177942
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-255-78/+76
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. llvm-svn: 177937
* Annotate X86InstrCompiler.td with SchedRW lists.Jakob Stoklund Olesen2013-03-251-10/+20
| | | | llvm-svn: 177936
* Annotate shifts and rotates with SchedRW lists.Jakob Stoklund Olesen2013-03-251-17/+37
| | | | llvm-svn: 177935
* Disable some unsafe-fp-math DAG-combine transformation after legalization.Shuxin Yang2013-03-251-5/+17
| | | | | | | | | | | | | | For instance, following transformation will be disabled: x + x + x => 3.0f * x; The problem of these transformations is that it introduces a FP constant, which following Instruction-Selection pass cannot handle. Reviewed by Nadav, thanks a lot! rdar://13445387 llvm-svn: 177933
* Couple more sets of tidying.Eric Christopher2013-03-251-5/+5
| | | | llvm-svn: 177920
* X86DisassemblerDecoder.c: Make this C89-compliant.NAKAMURA Takumi2013-03-251-1/+1
| | | | llvm-svn: 177910
* Whitespace.NAKAMURA Takumi2013-03-251-160/+160
| | | | llvm-svn: 177909
* Fix a bug in fast-math fadd/fsub simplification. Shuxin Yang2013-03-251-10/+43
| | | | | | | | | | | The problem is that the code mistakenly took for granted that following constructor is able to create an APFloat from a *SIGNED* integer: APFloat::APFloat(const fltSemantics &ourSemantics, integerPart value) rdar://13486998 llvm-svn: 177906
* Fix comment.Akira Hatanaka2013-03-251-3/+3
| | | | llvm-svn: 177899
* Formatting.Eric Christopher2013-03-251-4/+4
| | | | llvm-svn: 177898
* Use direct types in PowerPC instruction patterns.Ulrich Weigand2013-03-252-270/+262
| | | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in instruction patterns, along the lines of Jakob Stoklund Olesen's changes in r177835 for Sparc. llvm-svn: 177890
* Use direct types in PowerPC Pat patterns.Ulrich Weigand2013-03-252-113/+113
| | | | | | | | | This commit updates the PowerPC back-end (PPCInstrInfo.td and PPCInstr64Bit.td) to use types instead of register classes in Pat patterns, along the lines of Jakob Stoklund Olesen's changes in r177829 for Sparc. llvm-svn: 177889
* x86 -- add the XTEST instructionDave Zarzycki2013-03-254-31/+30
| | | | llvm-svn: 177888
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-7/+20
| | | | | | This fixes Apple bug: 13493622 llvm-svn: 177887
* Remove assert. There may be target-dependent attributes left.Bill Wendling2013-03-251-1/+0
| | | | llvm-svn: 177878
* [arm load/store optimizer] When trying to merge a base update load/store, makeChad Rosier2013-03-251-1/+1
| | | | | | | | | | | sure the base register and would-be writeback register don't conflict for stores. This was already being done for loads. Unfortunately, it is rather difficult to create a test case for this issue. It was exposed in 450.soplex at LTO and requires unlucky register allocation. <rdar://13394908> llvm-svn: 177874
* Teach cmake about the new Erlang GC files.Duncan Sands2013-03-252-0/+2
| | | | llvm-svn: 177869
* Add a GC plugin for ErlangYiannis Tsiouris2013-03-252-0/+201
| | | | llvm-svn: 177867
* Address issues found by Duncan during post-commit review of r177856.Arnaud A. de Grandmaison2013-03-251-32/+19
| | | | llvm-svn: 177863
* InstCombine: simplify comparisons to zero of (shl %x, Cst) or (mul %x, Cst)Arnaud A. de Grandmaison2013-03-251-0/+83
| | | | | | | | This simplification happens at 2 places : - using the nsw attribute when the shl / mul is used by a sign test - when the shl / mul is compared for (in)equality to zero llvm-svn: 177856
* Changed isNullOrUndef => IsNullOrUndef and isNoopInstruction => ↵Michael Gottesman2013-03-253-14/+14
| | | | | | IsNoopInstruction so that all helper functions are named similarly in ObjCARC.h. llvm-svn: 177855
* [NVPTX] Fix handling of vector argumentsJustin Holewinski2013-03-242-7/+56
| | | | llvm-svn: 177847
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. llvm-svn: 177845
* Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen2013-03-241-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; llvm-svn: 177843
* Minor cleanups. No functionality change.Jakub Staszak2013-03-241-6/+7
| | | | llvm-svn: 177837
* Use dyn_cast instead of isa && cast.Jakub Staszak2013-03-241-8/+6
| | | | | | No functionality change. llvm-svn: 177836
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-241-81/+68
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. llvm-svn: 177835
* PPC ZERO register needs a register number of 0.Hal Finkel2013-03-231-0/+1
| | | | | | | | | In order for the new ZERO register to be used with MC, etc. we need to specify its register number (0). Thanks to Kai for reporting the problem! llvm-svn: 177833
* Note in PPCFunctionInfo VRSAVE spillsHal Finkel2013-03-234-14/+34
| | | | | | | | | | | | In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. llvm-svn: 177832
* MCize the bcl instruction in PPCAsmPrinterHal Finkel2013-03-231-4/+5
| | | | | | | | | I recently added a BCL instruction definition as part of implementing SjLj support. This can also be used to MCize bcl emission in the asm printer. No functionality change intended. llvm-svn: 177830
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. llvm-svn: 177829
* Cleanup some unused reg. scavenger parameters in PPCRegisterInfoHal Finkel2013-03-232-33/+19
| | | | | | | | | | | These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. llvm-svn: 177827
* Remove dead PPC LR spilling codeHal Finkel2013-03-231-30/+8
| | | | | | | | | | The LR register is unconditionally reserved, and its spilling and restoration is handled by the prologue/epilogue code. As a result, it is never explicitly spilled by the register allocator. No functionality change intended. llvm-svn: 177823
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-231-1/+0
| | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. llvm-svn: 177820
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