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* Remove unused variable.Rafael Espindola2015-07-131-1/+0
| | | | | | Sorry I missed it in the previous commit. llvm-svn: 242032
* Aliases don't have available_externally linkage.Rafael Espindola2015-07-131-11/+0
| | | | | | | Allowing that is probably a good idea, but currently we don't, so this is dead code. llvm-svn: 242031
* Don't change the visibility when converting a definition to a declaration.Rafael Espindola2015-07-132-3/+1
| | | | llvm-svn: 242030
* Removing several -Wunused-but-set-variable warnings; NFC intended.Aaron Ballman2015-07-131-26/+0
| | | | llvm-svn: 242028
* Print the visibility of available_externally functions.Rafael Espindola2015-07-131-1/+1
| | | | | | We were already printing it for declarations, but not available_externally. llvm-svn: 242027
* Revert r241981 "Revert "Revert r236894 "[BasicAA] Fix zext & sext handling"""Manuel Klimek2015-07-131-199/+60
| | | | | | The repros from PR23626 still fail. llvm-svn: 242025
* AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long ↵Elena Demikhovsky2015-07-134-152/+436
| | | | | | | | | | | | types. In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch. I temporary removed the old intrinsics test (just to split this patch). Half types are not covered here. Differential Revision: http://reviews.llvm.org/D11134 llvm-svn: 242023
* [LSR] don't attempt to promote ephemeral values to indvarsJingyue Wu2015-07-131-1/+16
| | | | | | | | | | | | | | | | | Summary: This at least saves compile time. I also encountered a case where ephemeral values affect whether other variables are promoted, causing performance issues. It may be a bug in LSR, but I didn't manage to reduce it yet. Anyhow, I believe it's in general not worth considering ephemeral values in LSR. Reviewers: atrick, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11115 llvm-svn: 242011
* [InstSimplify] Teach InstSimplify how to simplify extractelementDavid Majnemer2015-07-133-58/+109
| | | | llvm-svn: 242008
* [InstSimplify] Teach InstSimplify how to simplify extractvalueDavid Majnemer2015-07-132-10/+44
| | | | llvm-svn: 242007
* [ARM] Add support for nest attribute using r12Renato Golin2015-07-121-0/+3
| | | | | | | | | | | | | | | | Register r12 ('ip') is used by GCC for this purpose and hence is used here. As discussed on the GCC mailing list, the register choice is an ABI issue and so choosing the same register as GCC means __builtin_call_with_static_chain is compatible. A similar patch has just gone in the AArch64 backend, so this is just the ARM counterpart, following the same discussion. Patch by Stephen Cross. llvm-svn: 241996
* [X86][SSE] (V)PMINSB is commutable.Simon Pilgrim2015-07-121-3/+0
| | | | | | (V)PMINSB is no different to the other (V)PMIN/(V)PMAX B/D/W instructions - it is fully commutable. llvm-svn: 241994
* Trim trailing whitespaces. NFC.Simon Pilgrim2015-07-121-3/+3
| | | | llvm-svn: 241990
* [X86][SSE] Vectorized v4i32 non-uniform shifts.Simon Pilgrim2015-07-122-23/+70
| | | | | | | | | | While the v4i32 shl operation is already vectorized using a cvttps2dq/pmulld pattern, the lshr/ashr opeations are still scalarized. This patch adds vectorization support for non-uniform v4i32 shift operations - it splats constant shift amounts to allow them to use the immediate sse shift instructions, or extracts/zero-extends non-constant shift amounts. The individual results are then blended together. Differential Revision: http://reviews.llvm.org/D11063 llvm-svn: 241989
* [LICM] Don't try to sink values out of loops without any exitsDavid Majnemer2015-07-121-1/+12
| | | | | | | | | | | | | There is no suitable basic block to sink instructions in loops without exits. The only way an instruction in a loop without exits can be used is as an incoming value to a PHI. In such cases, the incoming block for the corresponding value is unreachable. This fixes PR24013. Differential Revision: http://reviews.llvm.org/D10903 llvm-svn: 241987
* [PowerPC] Make use of the TargetRecip systemHal Finkel2015-07-123-15/+47
| | | | | | | | | | r238842 added the TargetRecip system for controlling use of reciprocal estimates for sqrt and division using a set of parameters that can be set by the frontend. Clang now supports a sophisticated -mrecip option, and this will allow that option to effectively control the relevant code-generation functionality of the PPC backend. llvm-svn: 241985
* [PowerPC] Support the nest parameter attributeHal Finkel2015-07-123-16/+51
| | | | | | | | | | | | | This adds support for the 'nest' attribute, which allows the static chain register to be set for functions calls under non-Darwin PPC/PPC64 targets. r11 is the chain register (which the PPC64 ELF ABI calls the "environment pointer"). For indirect calls under PPC64 ELFv1, this would normally be loaded from the function descriptor, but providing an explicit 'nest' parameter will override that process and use the value provided. This allows __builtin_call_with_static_chain to work as expected on PowerPC. llvm-svn: 241984
* Revert "Revert r236894 "[BasicAA] Fix zext & sext handling""Hal Finkel2015-07-111-60/+199
| | | | | | | | | | | r236894 caused PR23626 (Clang miscompiles webkit's base64 decoder), and was reverted in r237984. This reapplies the patch with an additional test case for PR23626 and the associated fix (both scales and offsets in the BasicAliasAnalysis::constantOffsetHeuristic should initially be zero). Patch by Nick White, thanks! llvm-svn: 241981
* Move getStrideFromPointer and friends from LoopVectorize to VectorUtilsHal Finkel2015-07-112-137/+146
| | | | | | | | | | | | | | | | The following functions are moved from the LoopVectorizer to VectorUtils: - getGEPInductionOperand - stripGetElementPtr - getUniqueCastUse - getStrideFromPointer These used to be static functions in LoopVectorize, but will also be used by the upcoming loop versioning LICM transformation. Patch by Ashutosh Nema! llvm-svn: 241980
* Add argmemonly attribute.Igor Laevsky2015-07-118-33/+62
| | | | | | | | This change adds new attribute called "argmemonly". Function marked with this attribute can only access memory through it's argument pointers. This attribute directly corresponds to the "OnlyAccessesArgumentPointees" ModRef behaviour in alias analysis. Differential Revision: http://reviews.llvm.org/D10398 llvm-svn: 241979
* [PM/AA] Completely remove the AliasAnalysis::copyValue interface.Chandler Carruth2015-07-1110-36/+1
| | | | | | | | | | | | | | | | | | | | | No in-tree alias analysis used this facility, and it was not called in any particularly rigorous way, so it seems unlikely to be correct. Note that one of the only stateful AA implementations in-tree, GlobalsModRef is completely broken currently (and any AA passes like it are equally broken) because Module AA passes are not effectively invalidated when a function pass that fails to update the AA stack runs. Ultimately, it doesn't seem like we know how we want to build stateful AA, and until then trying to support and maintain correctness for an untested API is essentially impossible. To that end, I'm planning to rip out all of the update API. It can return if and when we need it and know how to build it on top of the new pass manager and as part of *tested* stateful AA implementations in the tree. Differential Revision: http://reviews.llvm.org/D10889 llvm-svn: 241975
* Renamed some uses of unroll to interleave in the vectorizer.Tyler Nowicki2015-07-111-91/+98
| | | | llvm-svn: 241971
* Cleanup a couple of comments in DIBuilder.cppAdrian Prantl2015-07-101-3/+3
| | | | llvm-svn: 241966
* MC: Only allow changing feature bits in MCSubtargetInfoDuncan P. N. Exon Smith2015-07-102-6/+13
| | | | | | | | | | | | | | | | | Disallow all mutation of `MCSubtargetInfo` expect the feature bits. Besides deleting the assignment operators -- which were dead "code" -- this restricts `InitMCProcessorInfo()` to subclass initialization sequences, and exposes a new more limited function called `setDefaultFeatures()` for use by the ARMAsmParser `.cpu` directive. There's a small functional change here: ARMAsmParser used to adjust `MCSubtargetInfo::CPUSchedModel` as a side effect of calling `InitMCProcessorInfo()`, but I've removed that suspicious behaviour. Since the AsmParser shouldn't be doing any scheduling, there shouldn't be any observable change... llvm-svn: 241961
* AMDGPU: Fix chains for memory ops dependent on argument loadsMatt Arsenault2015-07-101-4/+19
| | | | | | | | | | | | | | | Most loads and stores are derived from pointers derived from a kernel argument load inserted during argument lowering. This was just using the EntryToken chain for the argument loads, and any users of these loads were also on the EntryToken chain. Return the chain of the lowered argument load so that dependent loads end up on the correct chain. No test since I'm not aware of any case where this actually broke. llvm-svn: 241960
* MIR Serialization: Serialize the virtual register operands.Alex Lorenz2015-07-106-13/+47
| | | | | | | | Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D11005 llvm-svn: 241959
* [IR] Switch static const to an enum to silence MSVC linker warningsDavid Majnemer2015-07-101-2/+0
| | | | | | | Integral class statics are handled oddly in MSVC, we don't need them in this case, use an enum instead. llvm-svn: 241958
* MC: Remove MCSubtargetInfo() default constructorDuncan P. N. Exon Smith2015-07-1015-56/+26
| | | | | | | | | | | | | | | | | | | | | Force all creators of `MCSubtargetInfo` to immediately initialize it, merging the default constructor and the initializer into an initializing constructor. Besides cleaning up the code a little, this makes it clear that the initializer is never called again later. Out-of-tree backends need a trivial change: instead of calling: auto *X = new MCSubtargetInfo(); InitXYZMCSubtargetInfo(X, ...); return X; they should call: return createXYZMCSubtargetInfoImpl(...); There's no real functionality change here. llvm-svn: 241957
* MC: Remove MCSubtargetInfo::InitCPUSched()Duncan P. N. Exon Smith2015-07-103-10/+1
| | | | | | | | | | | | Remove all calls to `MCSubtargetInfo::InitCPUSched()` and merge its body into the only relevant caller, `MCSubtargetInfo::InitMCProcessorInfo()`. We were only calling the former after explicitly calling the latter with the same CPU; it's confusing to have both methods exposed. Besides a minor (surely unmeasurable) speedup in ARM and X86 from avoiding running the logic twice, no functionality change. llvm-svn: 241956
* [InstCombine] Actually combine AA metadata when replacing one load with anotherBjorn Steinbrink2015-07-101-2/+0
| | | | | | Fixes PR24083 llvm-svn: 241955
* AMDGPU: Use requested chain when lowering argumentsMatt Arsenault2015-07-101-1/+1
| | | | | | | No test since I'm not aware of any case where this will end up being a different chain. llvm-svn: 241954
* ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920Matthias Braun2015-07-101-3/+3
| | | | llvm-svn: 241951
* [SEH] Push reloads of the SEH code past phi nodesReid Kleckner2015-07-101-6/+28
| | | | | | | | | | | This in turn would sometimes introduce new cleanupblocks that didn't previously exist. The uses were being introduced by SSA value demotion. We actually want to *promote* uses of EH pointers and selectors, so I added some spcecial casing to avoid demoting such instructions. This is getting overly complicated, but hopefully we'll come along and delete it in the new representation. llvm-svn: 241950
* Add <type_traits> for is_pod, fixing r241947Duncan P. N. Exon Smith2015-07-101-0/+1
| | | | llvm-svn: 241949
* DAGCombiner: Assume invariant load cannot alias a storeMatt Arsenault2015-07-101-0/+9
| | | | | | | | | | The motivation is to allow GatherAllAliases / FindBetterChain to not give up on dependent loads of a pointer from constant memory. This is important for AMDGPU, because most loads are pointers derived from a load of a kernel argument from constant memory. llvm-svn: 241948
* MC: Remove the copy of MCSchedModel in MCSubtargetInfoDuncan P. N. Exon Smith2015-07-103-6/+39
| | | | | | | | | | | `MCSchedModel` is large. Make `MCSchedModel::GetDefaultSchedModel()` return by-reference instead of by-value, so we can store a pointer in `MCSubtargetInfo::CPUSchedModel` instead of a copy. Note: since `MCSchedModel` is POD, this doesn't create a static constructor. llvm-svn: 241947
* [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.Quentin Colombet2015-07-101-3/+8
| | | | | | | Although this is not incorrect to insert such code, it is useless and it hurts the binary size. llvm-svn: 241946
* [MC] Switch static const to an enum to silence MSVC linker warningsDavid Majnemer2015-07-101-3/+0
| | | | | | | Integral class statics are handled oddly in MSVC, we don't need them in this case, use an enum instead. llvm-svn: 241945
* Fix AArch64 prologue for empty frame with dynamic allocas.Evgeniy Stepanov2015-07-101-8/+4
| | | | | | | | Fixes PR23804: assertion failure in emitPrologue in the case of a function with an empty frame and a dynamic alloca that needs stack realignment. This is a typical case for AddressSanitizer. llvm-svn: 241943
* [TTI] BasicTTIImpl assumes no vector registersJingyue Wu2015-07-103-11/+8
| | | | | | | | | | | | | | | | | | | | | | | Summary: Following the discussion on r241884, it's more reasonable to assume that a target has no vector registers by default instead of letting every such target overrides getNumberOfRegisters. Therefore, this patch modifies BasicTTIImpl::getNumberOfRegisters to return 0 when Vector is true, and partially reverts r241884 which modifies NVPTXTTIImpl::getNumberOfRegisters. It also fixes a performance bug in LoopVectorizer. Even if a target has no vector registers, vectorization may still help ILP. So, we need both checks to be false before disabling loop vectorization all together. Reviewers: hfinkel Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11108 llvm-svn: 241942
* [LoopDist/LoopVer] Move LoopVersioning to a new module, NFCAdam Nemet2015-07-103-115/+108
| | | | | | | | | | | | | | | | | | | Summary: The class will obviously need improvement down the road. For one, there is no reason that addPHINodes would have to be exposed like that. I will make this and other improvements in follow-up patches. The main goal is to be able to share this functionality. The LoopLoadElimination pass I am working on needs it too. Later we can move other clients as well (LV and Ashutosh's LICMVer). Reviewers: hfinkel, ashutosh.nema Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10577 llvm-svn: 241932
* [LoopDist] Move loop-versioning helper functions to Cloning, NFCAdam Nemet2015-07-102-66/+70
| | | | | | | | | | | | | | Summary: This makes them available to the LoopVersioning class as that is moved to its own module in the next patch. Reviewers: ashutosh.nema, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10576 llvm-svn: 241931
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-101-166/+186
| | | | | | | | | | | | This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 241928
* ComputeKnownBits: be a bit smarter about ADDsFiona Glaser2015-07-101-5/+14
| | | | | | | | If our two inputs have known top-zero bit counts M and N, we trivially know that the output cannot have any bits set in the top (min(M, N)-1) bits, since nothing could carry past that point. llvm-svn: 241927
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-101-29/+96
| | | | | | Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926
* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-1016-19/+331
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* MIR Serialization: Initial serialization of stack objects.Alex Lorenz2015-07-102-3/+39
| | | | | | | | | | | | | | This commit implements the initial serialization of stack objects from the MachineFrameInfo class. It can only serialize the ordinary stack objects (including ordinary spill slots), but it doesn't serialize variable sized or fixed stack objects yet. The stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset and alignment. The stack objects are a part of machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 241922
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-108-61/+50
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun2015-07-101-551/+481
| | | | | | | | | | | | | | | | | | | | | This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920
* Actually support volatile memcpys in NVPTX loweringEli Bendersky2015-07-101-8/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D11091 llvm-svn: 241914
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