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* Begin adding static dependence information to passes, which will allow us toOwen Anderson2010-10-1260-63/+346
| | | | | | | | | perform initialization without static constructors AND without explicit initialization by the client. For the moment, passes are required to initialize both their (potential) dependencies and any passes they preserve. I hope to be able to relax the latter requirement in the future. llvm-svn: 116334
* Combine these together - should probably have some text associatedEric Christopher2010-10-121-4/+4
| | | | | | that says what why what we just asserted is wrong. llvm-svn: 116333
* Mark variable 'NoImplicitFloatOps' used only in an assert as used.Nick Lewycky2010-10-121-0/+1
| | | | llvm-svn: 116323
* Add MOVi ARM encoding.Jim Grosbach2010-10-122-14/+24
| | | | llvm-svn: 116321
* Initial va_arg support for x86-64. Patch by David Meyer!Dan Gohman2010-10-124-6/+351
| | | | llvm-svn: 116319
* Nuke unused wrapper function.Jim Grosbach2010-10-121-3/+0
| | | | llvm-svn: 116318
* Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.Jakob Stoklund Olesen2010-10-123-56/+12
| | | | | | | | | | | The reg-reg copies were no longer being generated since copyPhysReg copies physical registers only. The loads and stores are not necessary - The TC constraint is imposed by the TAILJMP and TCRETURN instructions, there should be no need for constrained loads and stores. llvm-svn: 116314
* Add encoding information for the remainder of the generic arithmeticJim Grosbach2010-10-122-22/+43
| | | | | | ARM instructions. llvm-svn: 116313
* PR8359: The ARM backend may end up allocating registers D16 to D31 whenBob Wilson2010-10-124-3/+11
| | | | | | | | "-mattr=+vfp3" is specified. However, this will not work for hardware that only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16". Patch by Jan Voung! llvm-svn: 116310
* Rework alloca handling so that we can load or store from castedEric Christopher2010-10-121-63/+29
| | | | | | | | address that we've looked through. Fixes compilation problems in tramp3d from earlier patch. llvm-svn: 116296
* Handle a wider arrangement of loads.Eric Christopher2010-10-121-0/+16
| | | | llvm-svn: 116284
* Delete a redundant check.Dan Gohman2010-10-121-1/+1
| | | | llvm-svn: 116280
* More SmallVectorImpls.Dan Gohman2010-10-122-10/+10
| | | | llvm-svn: 116279
* Shrink a SmallVector with a known maximum size.Dan Gohman2010-10-121-1/+1
| | | | llvm-svn: 116278
* Constify.Dan Gohman2010-10-121-3/+4
| | | | llvm-svn: 116277
* Use SmallVectorImpl in a bunch of places.Dan Gohman2010-10-121-9/+9
| | | | llvm-svn: 116276
* More ARM scheduling itinerary fixes.Evan Cheng2010-10-114-377/+460
| | | | llvm-svn: 116266
* Support AA chaining.Dan Gohman2010-10-111-6/+9
| | | | llvm-svn: 116264
* Fix the pass manager's search order for immutable passes, and make itDan Gohman2010-10-111-22/+21
| | | | | | stop searching when it has found a match. llvm-svn: 116262
* MC machine encoding for simple aritmetic instructions that use a shiftedJim Grosbach2010-10-114-1/+42
| | | | | | register operand. llvm-svn: 116259
* Second set of ARM/MC/ELF changes.Jason W Kim2010-10-114-6/+71
| | | | | | | | | Added ARM specific ELF section types. Added AttributesSection to ARMElfTargetObject First step in unifying .cpu assembly tag with ELF/.o llc now asserts on actual ELF emission on -filetype=obj :-) llvm-svn: 116257
* Proper VST scheduling itineraries.Evan Cheng2010-10-114-124/+396
| | | | llvm-svn: 116251
* Use a sane mechanism for that assert.Eric Christopher2010-10-111-2/+2
| | | | llvm-svn: 116249
* Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis.Jakob Stoklund Olesen2010-10-111-10/+8
| | | | | | This helps hiding the LiveRange class which really should be private. llvm-svn: 116244
* We're not going to handle dynamic allocas anywhere else.Eric Christopher2010-10-111-1/+3
| | | | llvm-svn: 116240
* Change explicit search Apple specific code to only reference __eprintf on x86.Daniel Dunbar2010-10-111-8/+5
| | | | llvm-svn: 116239
* Make sure that the call stack adjustments have default operands. AlsoEric Christopher2010-10-111-5/+8
| | | | | | | | leave custom lowerings for later. Fixes some nightly tests. llvm-svn: 116232
* PowerPC varargs functions store live-in registers on the stack. Make sure we useJakob Stoklund Olesen2010-10-111-33/+13
| | | | | | | | | virtual registers for those stores since RegAllocFast requires that each live physreg only be used once. This fixes PR8357. llvm-svn: 116222
* Found a bug turning this on by default. Disable again for now.Eric Christopher2010-10-111-3/+3
| | | | llvm-svn: 116220
* Fix help text.Eric Christopher2010-10-111-1/+1
| | | | llvm-svn: 116218
* Change flag from Enable to Disable since we're enabled by default.Eric Christopher2010-10-111-4/+8
| | | | | | Also don't use fast-isel on non-darwin since it's untested. llvm-svn: 116217
* Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperandAndrew Trick2010-10-111-1/+3
| | | | llvm-svn: 116214
* More binary encoding stuff, taking advantage of the new "by name" operandJim Grosbach2010-10-112-25/+24
| | | | | | matching in tblgen to do the predicate operand. llvm-svn: 116213
* Turn on arm fast isel by default.Eric Christopher2010-10-111-1/+1
| | | | llvm-svn: 116212
* Properly handle reloading and spilling around partial redefines inJakob Stoklund Olesen2010-10-111-0/+14
| | | | | | | | | | | | LocalRewriter. This is a bit of a hack that adds an implicit use operand to model the read-modify-write nature of a partial redef. Uses and defs are rewritten in separate passes, and a single operand would never be processed twice. <rdar://problem/8518892> llvm-svn: 116210
* MSVC hangs on compilation of ARMDisassembler.cpp. PR6866 applied to ARM target.Francois Pichet2010-10-111-1/+7
| | | | llvm-svn: 116201
* Copy and pasteo.Eric Christopher2010-10-111-1/+1
| | | | llvm-svn: 116198
* Whitespace cleanup in ARM fast isel.Eric Christopher2010-10-111-80/+80
| | | | llvm-svn: 116197
* Add srem libcall support to ARM fast isel.Eric Christopher2010-10-111-0/+25
| | | | llvm-svn: 116196
* Add i8 sdiv support for ARM fast isel.Eric Christopher2010-10-111-1/+3
| | | | llvm-svn: 116195
* Implement select handling for ARM fast-isel.Eric Christopher2010-10-111-0/+31
| | | | llvm-svn: 116194
* Per discussion with Sanjiv, remove the PIC16 target from mainline. When/ifChris Lattner2010-10-1146-7493/+1
| | | | | | | it comes back, it will be largely a rewrite, so keeping the old codebase in tree isn't helping anyone. llvm-svn: 116190
* X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.Michael J. Spencer2010-10-111-0/+4
| | | | llvm-svn: 116188
* X86: MinGW should always use libgcc on Windows.Michael J. Spencer2010-10-101-1/+1
| | | | llvm-svn: 116177
* X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).Michael J. Spencer2010-10-101-0/+6
| | | | llvm-svn: 116174
* Fix Whitespace.Michael J. Spencer2010-10-102-90/+90
| | | | llvm-svn: 116173
* fix the default va_arg expansion (in the realignment case) to not implicitlyChris Lattner2010-10-101-1/+1
| | | | | | truncate the stack pointer to 32-bits on a 64-bit machine. llvm-svn: 116169
* fix the expansion of va_arg instruction on PPC to know the arg Chris Lattner2010-10-101-0/+4
| | | | | | | | | alignment for PPC32/64, avoiding some masking operations. llvm-gcc expands vaarg inline instead of using the instruction so it has never hit this. llvm-svn: 116168
* Now using a variant of the existing inlining heuristics to decide whether to ↵Kenneth Uildriks2010-10-092-40/+120
| | | | | | create a given specialization of a function in PartialSpecialization. If the total performance bonus across all callsites passing the same constant exceeds the specialization cost, we create the specialization. llvm-svn: 116158
* Silence compiler warning.Benjamin Kramer2010-10-091-1/+1
| | | | llvm-svn: 116156
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