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* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-058-31/+256
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Improvements to tail call code. No functional effectDale Johannesen2010-06-051-20/+22
| | | | | | unless using -arm-tail-calls. llvm-svn: 105515
* getFoldedOffsetOf no longer does anything special with vector types.Dan Gohman2010-06-051-1/+1
| | | | llvm-svn: 105514
* Revert 105492 & 105493 due to a testcase regression. Radar 7424645.Stuart Hastings2010-06-052-36/+19
| | | | llvm-svn: 105511
* LSR needs to remember inserted instructions even in postinc mode, becauseDan Gohman2010-06-051-1/+3
| | | | | | | there could be multiple subexpressions within a single expansion which require insert point adjustment. This fixes PR7306. llvm-svn: 105510
* Fix some liveout handling related to tail calls, see comments.Dale Johannesen2010-06-052-12/+12
| | | | | | | I don't think this ever resulted in problems on x86, but it would on ARM. llvm-svn: 105509
* Re-apply 105308 with fix.Evan Cheng2010-06-041-7/+13
| | | | llvm-svn: 105502
* Don't track users of undef values; they aren't interesting forDan Gohman2010-06-041-1/+5
| | | | | | register pressure. llvm-svn: 105501
* Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940Jim Grosbach2010-06-041-4/+23
| | | | llvm-svn: 105498
* Support for nested functions/classes in debug output. Radar 7424645.Stuart Hastings2010-06-042-19/+36
| | | | llvm-svn: 105492
* Copy location info for current function argument from dbg.declare if ↵Devang Patel2010-06-041-4/+2
| | | | | | respective store instruction does not have any location info. llvm-svn: 105490
* Skip dbg_value instructions when scanning instructions in register scavenging.Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105481
* Fix normalization and de-normalization of non-affine SCEVs.Dan Gohman2010-06-041-6/+9
| | | | llvm-svn: 105480
* Keep track of the call instructions whose clobber lists were skipped during fastJakob Stoklund Olesen2010-06-041-0/+17
| | | | | | | | | | | register allocation. Process all of the clobber lists at the end of the function, marking the registers as used in MachineRegisterInfo. This is necessary in case the calls clobber callee-saved registers (sic). llvm-svn: 105473
* More thoroughly disable tails calls by default.Dale Johannesen2010-06-041-3/+3
| | | | | | 8060143, although this doesn't fix the real problem with tail call. llvm-svn: 105472
* Another fix to prevent debug info from affecting codegen. rdar://7797940Jim Grosbach2010-06-041-0/+4
| | | | llvm-svn: 105470
* more dbg_value adjustments so debug info doesn't affect codegenJim Grosbach2010-06-041-2/+4
| | | | llvm-svn: 105454
* Fixed a bug during widening where we would avoid legalizing a node. When weMon P Wang2010-06-041-31/+36
| | | | | | | | | replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE when recursively updating nodes. Since OpA has been processed, the new uses are not examined again. The patch checks if this occurred and it it did, updates the new uses of OpA to use OpB. llvm-svn: 105453
* fix typoJim Grosbach2010-06-041-1/+1
| | | | llvm-svn: 105441
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-043-31/+75
| | | | | | | | | | | VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR node corresponds closely to REG_SEQUENCE but I couldn't use it here because its operands do not get legalized. That is pretty awful, but I guess it makes sense for other targets. Instead, I have added an ARM-specific version of BUILD_VECTOR that will have its operands properly legalized. This fixes the rest of Radar 7872877. llvm-svn: 105439
* Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.Bob Wilson2010-06-031-4/+21
| | | | | | | | | | | Check that all the instructions are in the same basic block, that the EXTRACT_SUBREGs write to the same subregs that are being extracted, and that the source and destination registers are in the same regclass. Some of these constraints can be relaxed with a bit more work. Jakob suggested that the loop that checks for subregs when NewSubIdx != 0 should use the "nodbg" iterator, so I made that change here, too. llvm-svn: 105437
* Cleanup 80-column and trim trailing whitespaceJim Grosbach2010-06-031-33/+33
| | | | llvm-svn: 105435
* Teach the ARM load-store optimizer to deal with dbg_value instructions.Jim Grosbach2010-06-031-4/+16
| | | | llvm-svn: 105427
* Early implementation of tail call for ARM.Dale Johannesen2010-06-035-6/+371
| | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. llvm-svn: 105413
* Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. ItDan Gohman2010-06-031-4/+8
| | | | | | needs to demand the high bits because it's asserting that they're zero. llvm-svn: 105406
* Revert 105308.Bob Wilson2010-06-031-1/+4
| | | | llvm-svn: 105399
* Machine sink could potentially sink instructions into a block where the physicalBill Wendling2010-06-031-4/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers it defines then interfere with an existing preg live range. For instance, if we had something like these machine instructions: BB#0 ... = imul ... EFLAGS<imp-def,dead> test ..., EFLAGS<imp-def> jcc BB#2 EFLAGS<imp-use> BB#1 ... ; fallthrough to BB#2 BB#2 ... ; No code that defines EFLAGS jcc ... EFLAGS<imp-use> Machine sink will come along, see that imul implicitly defines EFLAGS, but because it's "dead", it assumes that it can move imul into BB#2. But when it does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and messes up the condition code for the jump (and pretty much anything else which relies upon it being correct). The solution is to know which pregs are live going into a basic block. However, that information isn't calculated at this point. Nor does the LiveVariables pass take into account non-allocatable physical registers. In lieu of this, we do a *very* conservative pass through the basic block to determine if a preg is live coming out of it. llvm-svn: 105387
* Add first pass at darwin tls compiler support.Eric Christopher2010-06-038-24/+168
| | | | llvm-svn: 105381
* One underscore, not two.Eric Christopher2010-06-031-1/+1
| | | | llvm-svn: 105379
* Implement expansion in type legalization for add/sub with overflow. TheEli Friedman2010-06-032-0/+73
| | | | | | | | | | expansion is the same as that used by LegalizeDAG. The resulting code sucks in terms of performance/codesize on x86-32 for a 64-bit operation; I haven't looked into whether different expansions might be better in general. llvm-svn: 105378
* Remove some already-fixed README entries.Eli Friedman2010-06-031-86/+1
| | | | llvm-svn: 105377
* Remove README entry which no longer compiles to something sane.Eli Friedman2010-06-031-56/+0
| | | | llvm-svn: 105376
* Remove a fixed item, update a couple partially-fixed items.Eli Friedman2010-06-031-81/+22
| | | | llvm-svn: 105375
* Use the fast register allocator by default for -O0 builds.Jakob Stoklund Olesen2010-06-031-1/+1
| | | | | | This affects both llvm-gcc and clang. llvm-svn: 105372
* Use readsWritesVirtualRegister instead of counting uses and defs when insertingJakob Stoklund Olesen2010-06-031-46/+8
| | | | | | | | | | | | | spills and reloads. This means that a partial define of a register causes a reload so the other parts of the register are preserved. The reload can be prevented by adding an <imp-def> operand for the full register. This is already done by the coalescer and live interval analysis where relevant. llvm-svn: 105369
* Add full register <imp-def> operands when the coalescer is creating partialJakob Stoklund Olesen2010-06-021-50/+50
| | | | | | | | | register updates. These operands tell the spiller that the other parts of the partially defined register are don't-care, and a reload is not necessary. llvm-svn: 105361
* Speedup bitcode writer. Do not walk all values for all functions to emit ↵Devang Patel2010-06-023-9/+16
| | | | | | function local metadata. In one testcase, probably worst case scenario, the 70x speed up is seen. llvm-svn: 105360
* Compulsive reformating. No functionalitical changes.Bill Wendling2010-06-021-11/+19
| | | | llvm-svn: 105359
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-0212-38/+38
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. llvm-svn: 105358
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-0219-50/+64
| | | | llvm-svn: 105350
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-029-55/+63
| | | | llvm-svn: 105344
* Fix comment so it doesn't include comments which are irrelevant to the x86Eli Friedman2010-06-021-9/+5
| | | | | | backend. Add a FIXME noting what can be fixed here. llvm-svn: 105342
* Use comments to document non-obvious code rather thanDan Gohman2010-06-021-0/+11
| | | | | | mailing list archives. llvm-svn: 105341
* Skip identical instruction while calculating DBG_VALUE range.Devang Patel2010-06-021-1/+4
| | | | llvm-svn: 105340
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-023-11/+12
| | | | | | and tidy up the comment describing it. llvm-svn: 105339
* Replace ARM's getCalleeSavedRegClasses with a simpler solutionRafael Espindola2010-06-022-94/+40
| | | | llvm-svn: 105335
* Use local small vector.Devang Patel2010-06-022-4/+3
| | | | llvm-svn: 105332
* Remove unused function.Rafael Espindola2010-06-022-56/+0
| | | | llvm-svn: 105325
* Not all entries in the range will have an SUnit. Check for that when lookingJim Grosbach2010-06-022-0/+2
| | | | | | for debug information. llvm-svn: 105324
* cleanupRafael Espindola2010-06-0222-352/+0
| | | | llvm-svn: 105322
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