summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" ↵Geoff Berry2017-08-183-577/+24
| | | | | | | | | | | round 2 This reverts commit r311135. sanitizer-x86_64-linux-android buildbot is timing out with just this patch applied. llvm-svn: 311142
* Increase tail dup threshold for -O3 from 3 to 4.Richard Smith2017-08-171-1/+1
| | | | | | | | We see a modest performance improvement from this slightly higher tail dup threshold. Differential Revision: https://reviews.llvm.org/D36775 llvm-svn: 311139
* [X86] Remove SSE/AVX patterns for AND/XOR/OR/ANDN that checked for the ↵Craig Topper2017-08-171-26/+9
| | | | | | | | | | inputs being bitcasted from floating point types. There's really no reason to do this we should just let isel pick the integer version and let the execution dependency fixing pass take care of moving to FP if necessary. It's not very reliable to look for bitcasts at the edges of patterns. If for some reason one input was bitcasted and the other wasn't, or if one was a v4f32 bitcast and one was a v2f64 bitcast, we would have fallen back to the integer pattern anyway. llvm-svn: 311138
* GlobalISel (AArch64): fix ABI at border between GPRs and SP.Tim Northover2017-08-171-1/+5
| | | | | | | | If a struct would end up half in GPRs and half on SP the ABI says it should actually go entirely on the stack. We were getting this wrong in GlobalISel before, causing compatibility issues. llvm-svn: 311137
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source ↵Geoff Berry2017-08-173-24/+577
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | forwarding" Two issues identified by buildbots were addressed: - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. Reviewers: qcolombet, javed.absar, MatzeB, jonpa Subscribers: jyknight, nemanjai, llvm-commits, nhaehnle, mcrosier, mgorny Differential Revision: https://reviews.llvm.org/D30751 llvm-svn: 311135
* AMDGPU: Add R600InstPrinter classTom Stellard2017-08-173-109/+252
| | | | | | | | | | | | | | | | | | Summary: This is step towards separating the GCN and R600 tablegen'd code. This is a little awkward for now, because the R600 functions won't have the MCSubtargetInfo parameter, so we need to have AMDMGPUInstPrinter delegate to R600InstPrinter, but once the tablegen'd code is split, we will be able to drop the delegation and use R600InstPrinter directly. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36444 llvm-svn: 311128
* [LoopRotate][Dominators] Use the incremental API to update DomTreeJakub Kuderski2017-08-171-66/+13
| | | | | | | | | | | | | | Summary: This patch teaches LoopRotate to use the new incremental API to update the DominatorTree. Reviewers: dberlin, davide, grosser, sanjoy Reviewed By: dberlin, davide Subscribers: hiraditya, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D35581 llvm-svn: 311125
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-08-1716-220/+360
| | | | | | other minor fixes (NFC). llvm-svn: 311124
* Remove unused variable.Zachary Turner2017-08-171-1/+0
| | | | llvm-svn: 311119
* [llvm-pdbutil] Fix some dumping issues.Zachary Turner2017-08-171-1/+3
| | | | | | | | | | | | | | | | | When dumping, we were treating the S_INLINESITESYM as referring to a type record, when it actually refers to an id record. We had this correct in TypeIndexDiscovery, so our merging algorithm should be fine, but we had it wrong in the dumper, which means it would appear to work most of the time, unless the index was out of bounds in the type stream, when it would fail. Fixed this, and audited a few other cases to make them match the behavior in TypeIndexDiscovery. Also, I've now observed a new symbol record with kind 0x1168 which I have no clue what it is, so to avoid crashing we have to just print "Unknown Symbol Kind". llvm-svn: 311117
* Revert "[Debug info] Transfer DI to fragment expressions for split integer ↵Jonas Devlieghere2017-08-173-62/+19
| | | | | | | | values." This reverts commit r311102. llvm-svn: 311111
* [Debug info] Transfer DI to fragment expressions for split integer values.Jonas Devlieghere2017-08-173-19/+62
| | | | | | | | | This patch teaches the SDag type legalizer how to split up debug info for integer values that are split into a hi and lo part. Differential Revision: https://reviews.llvm.org/D36805 llvm-svn: 311102
* Improve line debug info when translating a CaseBlock to SDNodes.Adrian Prantl2017-08-172-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SelectionDAGBuilder translates various conditional branches into CaseBlocks which are then translated into SDNodes. If a conditional branch results in multiple CaseBlocks only the first CaseBlock is translated into SDNodes immediately, the rest of the CaseBlocks are put in a queue and processed when all LLVM IR instructions in the basic block have been processed. When a CaseBlock is transformed into SDNodes the SelectionDAGBuilder is queried for the current LLVM IR instruction and the resulting SDNodes are annotated with the debug info of the current instruction (if it exists and has debug metadata). When the deferred CaseBlocks are processed, the SelectionDAGBuilder does not have a current LLVM IR instruction, and the resulting SDNodes will not have any debuginfo. As DwarfDebug::beginInstruction() outputs a .loc directive for the first instruction in a labeled block (typically the case for something coming from a CaseBlock) this tends to produce a line-0 directive. This patch changes the handling of CaseBlocks to store the current instruction's debug info into the CaseBlock when it is created (and the SelectionDAGBuilder knows the current instruction) and to always use the stored debug info when translating a CaseBlock to SDNodes. Patch by Frej Drejhammar! Differential Revision: https://reviews.llvm.org/D36671 llvm-svn: 311097
* [Dominators] Teach LoopUnswitch to use the incremental APIJakub Kuderski2017-08-172-64/+60
| | | | | | | | | | | | | | | | | | Summary: This patch makes LoopUnswitch use new incremental API for updating dominators. It also updates SplitCriticalEdge, as it is called in LoopUnswitch. There doesn't seem to be any noticeable performance difference when bootstrapping clang with this patch. Reviewers: dberlin, davide, sanjoy, grosser, chandlerc Reviewed By: davide, grosser Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D35528 llvm-svn: 311093
* [AVX512] Don't switch unmasked subvector insert/extract instructions when ↵Craig Topper2017-08-171-36/+91
| | | | | | | | | | | | | | AVX512DQI is enabled. There's no reason to switch instructions with and without DQI. It just creates extra isel patterns and test divergences. There is however value in enabling the masked version of the instructions with DQI. This required introducing some new multiclasses to enabling this splitting. Differential Revision: https://reviews.llvm.org/D36661 llvm-svn: 311091
* [X86] Remove memopmmx pattern fragmentCraig Topper2017-08-172-11/+2
| | | | | | | | | | | | | | Summary: Just like the FIXME says, there is no alignment requirement for MMX. Reviewers: RKSimon, zvi, igorb Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36815 llvm-svn: 311090
* [dfsan] Add explicit zero extensions for shadow parameters in function wrappers.Simon Dardis2017-08-171-0/+10
| | | | | | | | | | | | | | | | | In the case where dfsan provides a custom wrapper for a function, shadow parameters are added for each parameter of the function. These parameters are i16s. For targets which do not consider this a legal type, the lack of sign extension information would cause LLVM to generate anyexts around their usage with phi variables and calling convention logic. Address this by introducing zero exts for each shadow parameter. Reviewers: pcc, slthakur Differential Revision: https://reviews.llvm.org/D33349 llvm-svn: 311087
* [DAGCombiner] Add support for non-uniform constant vectors to (mul x, (1 << ↵Simon Pilgrim2017-08-171-5/+9
| | | | | | c)) -> x << c llvm-svn: 311083
* [X86] Refactoring of X86TargetLowering::EmitLoweredSelect. NFC.Amjad Aboud2017-08-172-163/+238
| | | | | | | Authored by aivchenk Differential Revision: https://reviews.llvm.org/D35685 llvm-svn: 311082
* [Verifier] Avoid visiting DIGlobalVariables twice.Davide Italiano2017-08-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | We currently visit them twice. Once, through `visitMDNode()` -> (the code generated by) `../include/llvm/IR/Metadata.def:109` -> `visitDIGlobalVariable()` Then, through `visitMDNode()` -> `visitDIGlobalVariableExpression()` -> `visitDIGlobalVariable()` This results in verification failures printed twice, e.g.: $ ./opt -verify ../../test/DebugInfo/pr34186.ll missing global variable type !4 = distinct !DIGlobalVariable(name: "pat", scope: !0, file: !1, line: 27, isLocal: true, isDefinition: true) missing global variable type !4 = distinct !DIGlobalVariable(name: "pat", scope: !0, file: !1, line: 27, isLocal: true, isDefinition: true) ./opt: ../../test/DebugInfo/pr34186.ll: error: input module is broken! The patch removes one call so we ensure each GV is visited exactly once. Differential Revision: https://reviews.llvm.org/D36797 llvm-svn: 311081
* [LV] Using VPlan to model the vectorized code and drive its transformationAyal Zaks2017-08-174-523/+2251
| | | | | | | | | | | | | | | | | | | | | | | | | | | | VPlan is an ongoing effort to refactor and extend the Loop Vectorizer. This patch introduces the VPlan model into LV and uses it to represent the vectorized code and drive the generation of vectorized IR. In this patch VPlan models the vectorized loop body: the vectorized control-flow is represented using VPlan's Hierarchical CFG, with predication refactored from being a post-vectorization-step into a vectorization planning step modeling if-then VPRegionBlocks, and generating code inline with non-predicated code. The vectorized code within each VPBasicBlock is represented as a sequence of Recipes, each responsible for modelling and generating a sequence of IR instructions. To keep the size of this commit manageable the Recipes in this patch are coarse-grained and capture large chunks of LV's code-generation logic. The constructed VPlans are dumped in dot format under -debug. This commit retains current vectorizer output, except for minor instruction reorderings; see associated modifications to lit tests. For further details on the VPlan model see docs/Proposals/VectorizationPlan.rst and its references. Authors: Gil Rapaport and Ayal Zaks Differential Revision: https://reviews.llvm.org/D32871 llvm-svn: 311077
* Re-commit: [globalisel][tablegen] Support zero-instruction emission.Daniel Sanders2017-08-171-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Support the case where an operand of a pattern is also the whole of the result pattern. In this case the original result and all its uses must be replaced by the operand. However, register class restrictions can require a COPY. This patch handles both cases by always emitting the copy and leaving it for the register allocator to optimize. The previous commit failed on Windows machines due to a flaw in the sort predicate which allowed both A < B < C and B == C to be satisfied simultaneously. The cause of this was some sloppiness in the priority order of G_CONSTANT instructions compared to other instructions. These had equal priority because it makes no difference, however there were operands had higher priority than G_CONSTANT but lower priority than any other instruction. As a result, a priority order between G_CONSTANT and other instructions must be enforced to ensure the predicate defines a strict weak order. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: javed.absar, kristof.beyls, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36084 llvm-svn: 311076
* [SystemZ] Also wrap TII with #ifndef NDEBUG in constructor initilizer list.Jonas Paulsson2017-08-171-2/+8
| | | | | | TII needs to be wrapped with #ifndef NDEBUG to silece compiler warnings. llvm-svn: 311075
* [SystemZ] Add a wrapping with #ifndef NDEBUG to silence warning.Jonas Paulsson2017-08-171-0/+2
| | | | | | | SystemZHazardRecognizer::TII is only used for debug output, so it needs also to be wrapped with #ifndef NDEBUG. llvm-svn: 311074
* [SystemZ, MachineScheduler] Improve post-RA scheduling.Jonas Paulsson2017-08-175-77/+348
| | | | | | | | | | | | | | | | | | | | | | The idea of this patch is to continue the scheduler state over an MBB boundary in the case where the successor block has only one predecessor. This means that the scheduler will continue in the successor block (after emitting any branch instructions) with e.g. maintained processor resource counters. Benchmarks have been confirmed to benefit from this. The algorithm in MachineScheduler.cpp that extracts scheduling regions of an MBB has been extended so that the strategy may optionally reverse the order of processing the regions themselves. This is controlled by a new method doMBBSchedRegionsTopDown(), which defaults to false. Handling the top-most region of an MBB first also means that a top-down scheduler can continue the scheduler state across any scheduling boundary between to regions inside MBB. Review: Ulrich Weigand, Matthias Braun, Andy Trick. https://reviews.llvm.org/D35053 llvm-svn: 311072
* [SelectionDAG] Teach the vector-types operand scalarizer about SETCCElad Cohen2017-08-172-0/+34
| | | | | | | | | | | | | | | | When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
* [llvm-dlltool] Improve an error message when unable to open files. NFC.Martin Storsjo2017-08-171-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D36818 llvm-svn: 311069
* [llvm-dlltool] Don't crash if no def file is provided or it can't be openedMartin Storsjo2017-08-171-7/+14
| | | | | | Differential Revision: https://reviews.llvm.org/D36780 llvm-svn: 311068
* [CGP] Fix the rematerialization of gc.relocatesSerguei Katkov2017-08-171-0/+15
| | | | | | | | | | | | | | | | | | | If we want to substitute the relocation of derived pointer with gep of base then we must ensure that relocation of base dominates the relocation of derived pointer. Currently only check for basic block is present. However it is possible that both relocation are in the same basic block but relocation of derived pointer is defined earlier. The patch moves the relocation of base pointer right before relocation of derived pointer in this case. Reviewers: sanjoy,artagnon,igor-laevsky,reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36462 llvm-svn: 311067
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-08-173-549/+24
| | | | | | | | | | This reverts commit r311038. Several buildbots are breaking, and at least one appears to be due to the forwarding of physical regs enabled by this change. Reverting while I investigate further. llvm-svn: 311062
* ARM: mark CPSR as clobbered for Windows VLAsSaleem Abdulrasool2017-08-171-0/+4
| | | | | | | | | | | | | When lowering a VLA, we emit a __chstk call. However, this call can internally clobber CPSR. We did not mark this register as an ImpDef, which could potentially allow a comparison to be hoisted above the call to `__chkstk`. In such a case, the CPSR could be clobbered, and the check invalidated. When the support was initially added, it seemed that the call would take care of preventing CPSR from being clobbered, but this is not the case. Mark the register as clobbered to fix a possible state corruption. llvm-svn: 311061
* [X86] Exchange the memory op predicate for PALIGNR/VPALIGNR. I accidentally ↵Craig Topper2017-08-171-2/+2
| | | | | | swapped them. llvm-svn: 311060
* [X86] Cleanup multiclasses for SSE/AVX2 PALIGNR. Add missing load patterns.Craig Topper2017-08-171-43/+21
| | | | | | | | We used to have a separate multiclass for AVX2 and SSE/AVX. Now we have one multiclass and pass the relevant differences. We were also missing load patterns, though we had them for the AVX-512 version. llvm-svn: 311059
* [X86] Remove patterns for PALIGNR with non-vXi8 types.Craig Topper2017-08-173-37/+5
| | | | llvm-svn: 311058
* Reapply: [ADCE][Dominators] Teach ADCE to preserve dominatorsJakub Kuderski2017-08-171-7/+46
| | | | | | | | | | | | | | | | | | | | | Summary: This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees. I didn't notice any performance impact when bootstrapping clang with this patch. The patch was originally committed in r311039 and reverted in r311049. This revision fixes the problem with not adding a dependency on the DominatorTreeWrapperPass for the LegacyPassManager. Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki Reviewed By: davide Subscribers: grandinj, zhendongsu, llvm-commits, david2050 Differential Revision: https://reviews.llvm.org/D35869 llvm-svn: 311057
* [X86] Put multiclass closer to its use and simplify slightly. NFCCraig Topper2017-08-161-10/+11
| | | | llvm-svn: 311055
* [X86] Use a static array instead of a SmallVector for a small fixed size ↵Craig Topper2017-08-161-2/+2
| | | | | | array. NFC llvm-svn: 311054
* [InstCombine] Teach canEvaluateTruncated to handle arithmetic shift ↵Amjad Aboud2017-08-161-0/+17
| | | | | | | | (including those with vector splat shift amount) Differential Revision: https://reviews.llvm.org/D36784 llvm-svn: 311050
* Revert "[ADCE][Dominators] Teach ADCE to preserve dominators"Jakub Kuderski2017-08-161-43/+7
| | | | | | | This reverts commit r311039. The patch caused the `test/Bindings/OCaml/Output/scalar_opts.ml` to fail. llvm-svn: 311049
* [Analysis] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-08-165-81/+166
| | | | | | other minor fixes (NFC). llvm-svn: 311048
* [InstCombine] Make folding (X >s -1) ? C1 : C2 --> ((X >>s 31) & (C2 - C1)) ↵Craig Topper2017-08-161-17/+22
| | | | | | | | | | + C1 support splat vectors This also uses decomposeBitTestICmp to decode the compare. Differential Revision: https://reviews.llvm.org/D36781 llvm-svn: 311044
* [ADCE][Dominators] Teach ADCE to preserve dominatorsJakub Kuderski2017-08-161-7/+43
| | | | | | | | | | | | | | | | | Summary: This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees. I didn't notice any performance impact when bootstrapping clang with this patch. Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki Reviewed By: davide Subscribers: grandinj, zhendongsu, llvm-commits, david2050 Differential Revision: https://reviews.llvm.org/D35869 llvm-svn: 311039
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2017-08-163-24/+549
| | | | | | | | | | | | | | | | | | This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. Reviewers: qcolombet, javed.absar, MatzeB, jonpa Subscribers: jyknight, nemanjai, llvm-commits, nhaehnle, mcrosier, mgorny Differential Revision: https://reviews.llvm.org/D30751 llvm-svn: 311038
* [LoopDataPrefetch][AArch64FalkorHWPFFix] Preserve ScalarEvolutionGeoff Berry2017-08-162-6/+2
| | | | | | | | | | | | | | | | | | | | | Summary: Mark LoopDataPrefetch and AArch64FalkorHWPFFix passes as preserving ScalarEvolution since they do not alter loop structure and should not alter any SCEV values (though LoopDataPrefetch may introduce new instructions that won't have cached SCEV values yet). This can result in slight code differences, mainly w.r.t. nsw/nuw flags on SCEVs, since these are computed somewhat lazily when a zext/sext instruction is encountered. As a result, passes after the modified passes may see SCEVs with more nsw/nuw flags present. Reviewers: sanjoy, anemet Subscribers: aemerson, rengolin, mzolotukhin, javed.absar, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D36716 llvm-svn: 311032
* Add a convenience overload of DWARFDie::dump() for debugging purposes.Adrian Prantl2017-08-161-0/+2
| | | | llvm-svn: 311026
* Add more commentXinliang David Li2017-08-161-1/+9
| | | | llvm-svn: 311025
* [PGO] Fix ThinLTO crash Xinliang David Li2017-08-161-0/+6
| | | | | | Differential Revsion: http://reviews.llvm.org/D36640 llvm-svn: 311023
* [AMDGPU] NFC: test commitEvgeny Mankov2017-08-161-10/+10
| | | | llvm-svn: 311019
* AMDGPU/NFC: Sort files in CMakeLists.txt alphabeticallyKonstantin Zhuravlyov2017-08-161-17/+17
| | | | llvm-svn: 311017
* [Dominators] Introduce batch updatesJakub Kuderski2017-08-161-0/+10
| | | | | | | | | | | | | | | | | Summary: This patch introduces a way of informing the (Post)DominatorTree about multiple CFG updates that happened since the last tree update. This makes performing tree updates much easier, as it internally takes care of applying the updates in lockstep with the (virtual) updates to the CFG, which is done by reverse-applying future CFG updates. The batch updater is able to remove redundant updates that cancel each other out. In the future, it should be also possible to reorder updates to reduce the amount of work needed to perform the updates. Reviewers: dberlin, sanjoy, grosser, davide, brzycki Reviewed By: brzycki Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D36167 llvm-svn: 311015
OpenPOWER on IntegriCloud