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* Change ARMGlobalMerge to keep BSS globals in separate pools.Bob Wilson2010-11-171-4/+10
| | | | | | This completes the fixes for Radar 8673120. llvm-svn: 119566
* Fix ARMGlobalMerge pass to check if globals are entirely within range.Bob Wilson2010-11-171-2/+5
| | | | | | | It is generally not sufficient to check if the starting offset is in range of the maximum offset that can be efficiently used for the target. llvm-svn: 119565
* Change the symbol for merged globals from "merged" to "_MergedGlobals".Bob Wilson2010-11-171-1/+1
| | | | | | | This makes it more clear that the symbol is an internal, compiler-generated name and gives a little more description about its contents. llvm-svn: 119564
* Fix the ARMGlobalMerge pass to look at variable sizes instead of pointer sizes.Bob Wilson2010-11-171-1/+1
| | | | | | | It was mistakenly looking at the pointer type when checking for the size of global variables. This is a partial fix for Radar 8673120. llvm-svn: 119563
* Move SCEV::isLoopInvariant and hasComputableLoopEvolution to be memberDan Gohman2010-11-175-99/+153
| | | | | | | functions of ScalarEvolution, in preparation for memoization and other optimizations. llvm-svn: 119562
* Make the ARM BR_JTadd instruction an explicit pseudo and lower it properlyJim Grosbach2010-11-172-12/+25
| | | | | | in the MC lowering process. llvm-svn: 119559
* Avoid isel movcc of large immediates when the large immediate is available ↵Evan Cheng2010-11-171-10/+14
| | | | | | in a register. These immediates aren't free. llvm-svn: 119558
* Reference ScalarEvolution by name rather than directly in LICM,Dan Gohman2010-11-171-2/+1
| | | | | | to avoid an unneeded dependence. llvm-svn: 119557
* Before replacing a phi node with a different value, itDuncan Sands2010-11-171-11/+15
| | | | | | | | | | needs to be checked that this won't break LCSSA form. Change the existing checking method to a more direct one: rather than seeing if all predecessors belong to the loop, check that the replacing value is either not in any loop or is in a loop that contains the phi node. llvm-svn: 119556
* Revert r119551, which broke buildbots.Owen Anderson2010-11-171-34/+13
| | | | llvm-svn: 119555
* Verify SCEVAddRecExpr's invariant in ScalarEvolution::getAddRecExprDan Gohman2010-11-171-0/+3
| | | | | | | instead of in SCEVAddRecExpr's constructor, in preparation for an upcoming change. llvm-svn: 119554
* Provide Thumb2 encodings for bitfield instructions.Owen Anderson2010-11-171-13/+34
| | | | llvm-svn: 119551
* Fix ScalarEvolution's range memoization to avoid using aDan Gohman2010-11-171-44/+43
| | | | | | default ctor with ConstantRange. llvm-svn: 119550
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-177-43/+200
| | | | | | | | | | | | | | | | | | | | | and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 llvm-svn: 119548
* make isVirtualSection a virtual method on MCSection. Chris' suggestion.Rafael Espindola2010-11-179-48/+21
| | | | llvm-svn: 119547
* More miscellaneous Thumb2 encodings.Owen Anderson2010-11-171-14/+41
| | | | llvm-svn: 119546
* Fix typo.Jim Grosbach2010-11-171-1/+1
| | | | llvm-svn: 119542
* Add missing opcodes now that this function's used in more than one place.Bill Wendling2010-11-171-0/+20
| | | | llvm-svn: 119539
* InstCombine: Add a missing irem identity (X % X -> 0).Benjamin Kramer2010-11-171-0/+4
| | | | llvm-svn: 119538
* Move some those Xor simplifications which don't require creating newDuncan Sands2010-11-172-61/+80
| | | | | | | | instructions out of InstCombine and into InstructionSimplify. While there, introduce an m_AllOnes pattern to simplify matching with integers and vectors with all bits equal to one. llvm-svn: 119536
* More ARM encoding bits. LDRH now encodes properly.Jim Grosbach2010-11-172-30/+47
| | | | llvm-svn: 119529
* Add support for .int.Rafael Espindola2010-11-171-0/+2
| | | | llvm-svn: 119512
* Add support for .2byte, .4byte and .8byte.Rafael Espindola2010-11-171-0/+6
| | | | | | Fixes PR8631. llvm-svn: 119511
* MC-JIT: Stub out "pure" streamer.Daniel Dunbar2010-11-172-0/+260
| | | | | | - No immediate use, but maybe someone feels like hacking on it. llvm-svn: 119510
* MCJIT: Stub out MCJIT implementation, still doesn't do anything useful.Daniel Dunbar2010-11-176-1/+269
| | | | llvm-svn: 119509
* lli: Add stub -use-mcjit option, which doesn't currently do anything.Daniel Dunbar2010-11-171-1/+17
| | | | llvm-svn: 119508
* Have InlineFunction use SimplifyInstruction rather thanDuncan Sands2010-11-171-9/+11
| | | | | | | | | hasConstantValue. I was leery of using SimplifyInstruction while the IR was still in a half-baked state, which is the reason for delaying the simplification until the IR is fully cooked. llvm-svn: 119494
* Now that hasConstantValue has been made simpler, it may return theDuncan Sands2010-11-172-5/+7
| | | | | | | phi node itself if it occurs in an unreachable basic block. Protect against this. Hopefully this will fix some more buildbots. llvm-svn: 119493
* Revert r119109 for now. It's breaking 176.gcc.Evan Cheng2010-11-171-17/+0
| | | | llvm-svn: 119492
* Previously SimplifyInstruction could report that an instructionDuncan Sands2010-11-172-17/+32
| | | | | | | | simplified to itself (this can only happen in unreachable blocks). Change it to return null instead. Hopefully this will fix some buildbot failures. llvm-svn: 119490
* With the newly simplified SourceMgr interfaces and the generalizedChris Lattner2010-11-171-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SrcMgrDiagHandler, we can improve clang diagnostics for inline asm: instead of reporting them on a source line of the original line, we can report it on the correct line wherever the string literal came from. For something like this: void foo() { asm("push %rax\n" ".code32\n"); } we used to get this: (note that the line in t.c isn't helpful) t.c:4:7: error: warning: ignoring directive for now asm("push %rax\n" ^ <inline asm>:2:1: note: instantiated into assembly here .code32 ^ now we get: t.c:5:8: error: warning: ignoring directive for now ".code32\n" ^ <inline asm>:2:1: note: instantiated into assembly here .code32 ^ Note that we're pointing to line 5 properly now. llvm-svn: 119488
* now that AsmPrinter::EmitInlineAsm is factored right, we can eliminate theChris Lattner2010-11-174-17/+14
| | | | | | | | cookie argument to the SourceMgr diagnostic stuff. This cleanly separates LLVMContext's inlineasm handler from the sourcemgr error handling definition, increasing type safety and cleaning things up. llvm-svn: 119486
* Add simple arithmetics and %type directive for PTXChe-Liang Chiou2010-11-172-9/+51
| | | | llvm-svn: 119485
* Simplify code that toggle optional operand to ARM::CPSR.Evan Cheng2010-11-171-3/+3
| | | | llvm-svn: 119484
* rearrange how the handler in SourceMgr is installed, eliminating the use of Chris Lattner2010-11-171-8/+35
| | | | | | the cookie argument to setDiagHandler llvm-svn: 119483
* refactor the interface to EmitInlineAsm a bit, no functionality change.Chris Lattner2010-11-172-11/+18
| | | | llvm-svn: 119482
* fix PR8613 - Copy constructor of SwitchInst does not call SwitchInst::initChris Lattner2010-11-171-8/+9
| | | | llvm-svn: 119463
* tidy upChris Lattner2010-11-172-26/+16
| | | | llvm-svn: 119462
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-173-6/+14
| | | | | | should get the submode from the load/store multiple instruction's opcode. llvm-svn: 119461
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-173-11/+57
| | | | | | | | | instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
* Fix a layering violation: hasConstantValue, which is part of the PHINodeDuncan Sands2010-11-173-61/+46
| | | | | | | | | | | | | | class, uses DominatorTree which is an analysis. This change moves all of the tricky hasConstantValue logic to SimplifyInstruction, and replaces it with a very simple literal implementation. I already taught users of hasConstantValue that need tricky stuff to use SimplifyInstruction instead. I didn't update InlineFunction because the IR looks like it might be in a funky state at the point it calls hasConstantValue, which makes calling SimplifyInstruction dangerous since it can in theory do a lot of tricky reasoning. This may be a pessimization, for example in the case where all phi node operands are either undef or a fixed constant. llvm-svn: 119459
* Have ScalarEvolution use SimplifyInstruction rather than hasConstantValue.Duncan Sands2010-11-171-1/+5
| | | | | | While there, add a note about an inefficiency I noticed. llvm-svn: 119458
* Have RemovePredecessorAndSimplify you SimplifyInstructionDuncan Sands2010-11-171-4/+4
| | | | | | rather than hasConstantValue. llvm-svn: 119457
* Remove dead code in GVN: now that SimplifyInstruction is calledDuncan Sands2010-11-171-43/+2
| | | | | | | | | | systematically, CollapsePhi will always return null here. Note that CollapsePhi did an extra check, isSafeReplacement, which the SimplifyInstruction logic does not do. I think that check was bogus - I guess we will soon find out! (It was originally added in commit 41998 without a testcase). llvm-svn: 119456
* Memoize results from ScalarEvolution's getUnsignedRange and getSignedRange.Dan Gohman2010-11-171-43/+80
| | | | | | This fixes some extreme compile times on unrolled sha512 code. llvm-svn: 119455
* Only avoid the check if we're the last operand before the variableEric Christopher2010-11-171-3/+3
| | | | | | operands in a variadic instruction. llvm-svn: 119446
* Add binary emission stuff for VLDM/VSTM. This reuses theBill Wendling2010-11-172-6/+49
| | | | | | | "getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. llvm-svn: 119435
* Fix typo: Exectuable -> ExecutablePeter Collingbourne2010-11-172-2/+2
| | | | llvm-svn: 119433
* Use the correct variable names so that the encodings will be correct.Bill Wendling2010-11-162-4/+4
| | | | llvm-svn: 119403
* Reapply r118917. With pseudo-instruction expansion moved toDan Gohman2010-11-161-5/+5
| | | | | | | a different pass, the complicated interaction between cmov expansion and fast isel is no longer a concern. llvm-svn: 119400
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