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* Add a statistic to PHIElimination tracking the number of critical edges split.Cameron Zwarich2011-02-141-2/+7
| | | | llvm-svn: 125476
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-135-72/+91
| | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
* Revisit my fix for PR9028: the issue is that DAGCombine was Chris Lattner2011-02-134-40/+46
| | | | | | | | | generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h llvm-svn: 125465
* remove a now-unneccesary cast.Chris Lattner2011-02-131-1/+1
| | | | llvm-svn: 125464
* Remove pointless blank line.Duncan Sands2011-02-131-1/+0
| | | | llvm-svn: 125463
* Teach instsimplify that X+Y>=X+Z is the same as Y>=Z if neither side overflows,Duncan Sands2011-02-131-2/+49
| | | | | | | | plus some variations of this. According to my auto-simplifier this occurs a lot but usually in combination with max/min idioms. Because max/min aren't handled yet this unfortunately doesn't have much effect in the testsuite. llvm-svn: 125462
* Fix a regression from r125393;Nadav Rotem2011-02-131-1/+2
| | | | | | | | | | | | | It caused a crash in MultiSource/Benchmarks/Bullet. Opt hit an assertion with "opt -std-compile-opts" because Constant::getAllOnesValue doesn't know how to handle floats. This patch added a test to reproduce the problem and a check that the destination vector is of integer type. Thank you Benjamin! llvm-svn: 125459
* when legalizing extremely wide shifts, make sure that Chris Lattner2011-02-132-3/+9
| | | | | | | | | the shift amounts are in a suitably wide type so that we don't generate out of range constant shift amounts. This fixes PR9028. llvm-svn: 125458
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-131-20/+19
| | | | | | | is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. llvm-svn: 125457
* implement instcombine folding for things like (x >> c) < 42.Chris Lattner2011-02-131-8/+50
| | | | | | We were previously simplifying divisions, but not right shifts! llvm-svn: 125454
* refactor some code out into a helper method.Chris Lattner2011-02-132-46/+56
| | | | llvm-svn: 125451
* teach SCEV that the scale and addition of an inbounds gep don't NSW.Chris Lattner2011-02-131-2/+5
| | | | | | | This fixes a FIXME in scev-aa.ll (allowing a new no-alias result) and generally makes things more precise. llvm-svn: 125449
* Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.Reid Kleckner2011-02-121-0/+4
| | | | | | | | These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. llvm-svn: 125446
* Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend.Venkatraman Govindaraju2011-02-121-0/+3
| | | | llvm-svn: 125444
* SimplifyLibCalls: Add missing legalize check on various printf to puts andDaniel Dunbar2011-02-121-5/+9
| | | | | | putchar transforms, their return values are not compatible. llvm-svn: 125442
* Add a note about SSE4.1 roundss/roundsd.Benjamin Kramer2011-02-121-0/+11
| | | | llvm-svn: 125438
* A fix for 9165.Nadav Rotem2011-02-121-4/+9
| | | | | | | | The DAGCombiner created illegal BUILD_VECTOR operations. The patch added a check that either illegal operations are allowed or that the created operation is legal. llvm-svn: 125435
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-123-23/+32
| | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. llvm-svn: 125426
* Also fold (A+B) == A -> B == 0 when the add is commuted.Benjamin Kramer2011-02-111-2/+4
| | | | llvm-svn: 125411
* Per discussion with Dan G, inbounds geps *certainly* can haveChris Lattner2011-02-111-3/+14
| | | | | | | | | | | unsigned overflow (e.g. "gep P, -1"), and while they can have signed wrap in theoretical situations, modelling an AddRec as not having signed wrap is going enough for any case we can think of today. In the future if this isn't enough, we can revisit this. Modeling them as having NUW isn't causing any known problems either FWIW. llvm-svn: 125410
* When lowering an inbounds gep, the intermediate adds can haveChris Lattner2011-02-111-6/+3
| | | | | | | | unsigned overflow (e.g. due to a negative array index), but the scales on array size multiplications are known to not sign wrap. llvm-svn: 125409
* Adds llvm::sys::path::is_separator() to test whether a char is a path separatorZhanyong Wan2011-02-111-12/+13
| | | | | | on the host OS. Reviewed by dgregor. llvm-svn: 125406
* Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.Nate Begeman2011-02-111-0/+182
| | | | | | This avoids moving each element to the integer register file and calling __divsi3 etc. on it. llvm-svn: 125402
* SimplifySelectOps can only handle selects with a scalar condition. Add a checkNadav Rotem2011-02-111-0/+3
| | | | | | that the condition is not a vector. llvm-svn: 125398
* Fix 9173.Nadav Rotem2011-02-111-0/+40
| | | | | | | Add more folding patterns to constant expressions of vector selects and vector bitcasts. llvm-svn: 125393
* Fix #9190Nadav Rotem2011-02-111-1/+1
| | | | | | | | | | | The bug happens when the DAGCombiner attempts to optimize one of the patterns of the SUB opcode. It tries to create a zero of type v2i64. This type is legal on 32bit machines, but the initializer of this vector (i64) is target dependent. Currently, the initializer attempts to create an i64 zero constant, which fails. Added a flag to tell the DAGCombiner to create a legal zero, if we require that the pass would generate legal types. llvm-svn: 125391
* More whitespace cleanup...Jim Grosbach2011-02-112-41/+41
| | | | llvm-svn: 125388
* Make LoopUnswitch preserve ScalarEvolution by just forgetting everything aboutCameron Zwarich2011-02-111-0/+5
| | | | | | | a loop when unswitching it. It only does this in the complex case, because everything should be fine already in the simple case. llvm-svn: 125369
* LoopInstSimplify preserves ScalarEvolution.Cameron Zwarich2011-02-111-0/+1
| | | | llvm-svn: 125368
* make ConstantExpr::replaceUsesOfWithOnConstant preserve the inboundsChris Lattner2011-02-111-1/+2
| | | | | | flag. Noticed by Jin Gu Kang! llvm-svn: 125366
* make the constantexpr interfaces for inbounds GEPs follow the same styleChris Lattner2011-02-111-63/+10
| | | | | | as other constantexpr flags, reducing redundancy. llvm-svn: 125365
* Remove std::string version of getNameWithPrefix.Rafael Espindola2011-02-111-10/+0
| | | | llvm-svn: 125363
* Fix buggy fcopysign lowering.Evan Cheng2011-02-111-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define float @foo(float %x, float %y) nounwind readnone { entry: %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 } Was compiled to: vmov s0, r1 bic r0, r0, #-2147483648 vmov s1, r0 vcmpe.f32 s0, #0 vmrs apsr_nzcv, fpscr it lt vneglt.f32 s1, s1 vmov r0, s1 bx lr This fails to copy the sign of -0.0f because it's lost during the float to int conversion. Also, it's sub-optimal when the inputs are in GPR registers. Now it uses integer and + or operations when it's profitable. And it's correct! lsrs r1, r1, #31 bfi r0, r1, #31, #1 bx lr rdar://8984306 llvm-svn: 125357
* Tolerate degenerate phi nodes that can occur in the middle of optimizationNick Lewycky2011-02-101-0/+4
| | | | | | passes. Fixes PR9112. Patch by Jakub Staszak! llvm-svn: 125319
* If we can't avoid running loop-simplify twice for now, at least avoid runningCameron Zwarich2011-02-101-0/+3
| | | | | | iv-users twice. llvm-svn: 125318
* Rename 'loopsimplify' to 'loop-simplify'.Cameron Zwarich2011-02-101-3/+3
| | | | llvm-svn: 125317
* [AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR. ThisDavid Greene2011-02-101-0/+18
| | | | | | | largely completes support for 128-bit fallback lowering for code that is not 256-bit ready. llvm-svn: 125315
* Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka ↵Bruno Cardoso Lopes2011-02-101-47/+71
| | | | | | with some small modifications by me. llvm-svn: 125292
* [AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.David Greene2011-02-101-1/+35
| | | | llvm-svn: 125284
* ptx: add passing parameter to kernel functionsChe-Liang Chiou2011-02-108-61/+96
| | | | llvm-svn: 125279
* implement the first part of PR8882: when lowering an inboundsChris Lattner2011-02-101-8/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | gep to explicit addressing, we know that none of the intermediate computation overflows. This could use review: it seems that the shifts certainly wouldn't overflow, but could the intermediate adds overflow if there is a negative index? Previously the testcase would instcombine to: define i1 @test(i64 %i) { %p1.idx.mask = and i64 %i, 4611686018427387903 %cmp = icmp eq i64 %p1.idx.mask, 1000 ret i1 %cmp } now we get: define i1 @test(i64 %i) { %cmp = icmp eq i64 %i, 1000 ret i1 %cmp } llvm-svn: 125271
* switch the constantexpr, target folder, and IRBuilder interfacesChris Lattner2011-02-101-67/+24
| | | | | | | for NSW/NUW binops to follow the pattern of exact binops. This allows someone to use Builder.CreateAdd(x, y, "tmp", MaybeNUW); llvm-svn: 125270
* Enhance a bunch of transformations in instcombine to start generatingChris Lattner2011-02-102-142/+145
| | | | | | | | | | | exact/nsw/nuw shifts and have instcombine infer them when it can prove that the relevant properties are true for a given shift without them. Also, a variety of refactoring to use the new patternmatch logic thrown in for good luck. I believe that this takes care of a bunch of related code quality issues attached to PR8862. llvm-svn: 125267
* Enhance the "compare with shift" and "compare with div" Chris Lattner2011-02-101-44/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations to be much more aggressive in the face of exact/nsw/nuw div and shifts. For example, these (which are the same except the first is 'exact' sdiv: define i1 @sdiv_icmp4_exact(i64 %X) nounwind { %A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0 %B = icmp eq i64 %A, 0 ret i1 %B } define i1 @sdiv_icmp4(i64 %X) nounwind { %A = sdiv i64 %X, -5 ; X/-5 == 0 --> x == 0 %B = icmp eq i64 %A, 0 ret i1 %B } compile down to: define i1 @sdiv_icmp4_exact(i64 %X) nounwind { %1 = icmp eq i64 %X, 0 ret i1 %1 } define i1 @sdiv_icmp4(i64 %X) nounwind { %X.off = add i64 %X, 4 %1 = icmp ult i64 %X.off, 9 ret i1 %1 } This happens when you do something like: (ptr1-ptr2) == 42 where the pointers are pointers to non-unit types. llvm-svn: 125266
* more cleanups, notably bitcast isn't used for "signed to unsigned type Chris Lattner2011-02-101-45/+27
| | | | | | conversions". :) llvm-svn: 125265
* A bunch of cleanups and simplifications using the new PatternMatch predicatesChris Lattner2011-02-101-176/+132
| | | | | | | | | | and generally tidying things up. Only very trivial functionality changes like now doing (-1 - A) -> (~A) for vectors too. InstCombineAddSub.cpp | 296 +++++++++++++++++++++----------------------------- 1 file changed, 126 insertions(+), 170 deletions(-) llvm-svn: 125264
* teach SimplifyDemandedBits that exact shifts demand the bits they Chris Lattner2011-02-101-3/+23
| | | | | | | are shifting out since they do require them to be zeros. Similarly for NUW/NSW bits of shl llvm-svn: 125263
* After 3-addressifying a two-address instruction, update the register maps; ↵Evan Cheng2011-02-101-4/+9
| | | | | | add a missing check when considering whether it's profitable to commute. rdar://8977508. llvm-svn: 125259
* Revert this in an attempt to bring the builders back.Eric Christopher2011-02-101-4/+4
| | | | llvm-svn: 125257
* Turn this pass ordering:Cameron Zwarich2011-02-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Natural Loop Information Loop Pass Manager Canonicalize natural loops Scalar Evolution Analysis Loop Pass Manager Induction Variable Users Canonicalize natural loops Induction Variable Users Loop Strength Reduction into this: Scalar Evolution Analysis Loop Pass Manager Canonicalize natural loops Induction Variable Users Loop Strength Reduction This fixes <rdar://problem/8869639>. I also filed PR9184 on doing this sort of thing automatically, but it seems easier to just change the ordering of the passes if this is the only case. llvm-svn: 125254
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