| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 53237
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soft float.
llvm-svn: 53231
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parameter attributes.
llvm-svn: 53228
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llvm-svn: 53227
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call attributes.
llvm-svn: 53223
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1) evaluate [v]fcmp true/false with undefs to true or false instead
of undef.
2) fix vector comparisons with undef to return a vector result instead
of i1
3) fix vector comparisons with evaluatable results to return vector
true/false instead of i1 true/false (PR2529)
llvm-svn: 53220
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llvm-svn: 53217
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llvm-svn: 53215
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MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
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and reused across SelectionDAGs.
This drastically reduces the number of calls to malloc/free made during
instruction selection, and improves memory locality.
llvm-svn: 53211
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for handling bookkeeping for deleted objects, as well as the alist class
template, for keeping lists of objects allocated from Recyclers, and some
related utilities.
llvm-svn: 53210
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llvm-svn: 53209
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each charater of Name. This speeds it up by 10%.
llvm-svn: 53208
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There is no need for targets to specify register names in addition to their AsmName's.
llvm-svn: 53207
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llvm-svn: 53206
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llvm-svn: 53202
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properly track dead nodes that are on the original SDNode's operand
list but not the new one, and have no other uses.
llvm-svn: 53201
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#include dependency on Support/MathExtras.h in the header file.
llvm-svn: 53200
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pool-allocating MachineInstrs.
llvm-svn: 53198
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llvm-svn: 53197
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llvm-svn: 53196
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their cleanup code.
llvm-svn: 53194
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1. LSR runOnLoop is always returning false regardless if any transformation is made.
2. AddUsersIfInteresting can create new instructions that are added to DeadInsts. But there is a later early exit which prevents them from being freed.
llvm-svn: 53193
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llvm-svn: 53192
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simple const SDOperand*, which is what's usually needed.
For AddNodeIDOperands, which is small, just duplicate the function to
accept an SDUse*.
For SelectionDAG::getNode - Add an overload that accepts SDUse* that
copies the operands into a temporary SDOperand array, but also has
special-case checks for 0 through 3 operands to avoid the copy in
the common cases.
llvm-svn: 53183
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llvm-svn: 53179
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llvm-svn: 53178
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llvm-svn: 53177
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Richard Osborne.
llvm-svn: 53169
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Comment the xor %x, -1 case.
llvm-svn: 53167
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llvm-svn: 53166
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float value.
llvm-svn: 53165
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having weak or linkonce or common or extweak LLVM linkage.
llvm-svn: 53158
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llvm-svn: 53156
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llvm-svn: 53154
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llvm-svn: 53151
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that fixed problems in EmitStackConvert where the source and target type
have different alignment by creating a stack slot with the max
alignment of source and target type.
llvm-svn: 53150
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important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
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hook for each way in which a result type can be
legalized (promotion, expansion, softening etc),
just use one: ReplaceNodeResults, which returns
a node with exactly the same result types as the
node passed to it, but presumably with a bunch of
custom code behind the scenes. No change if the
new LegalizeTypes infrastructure is not turned on.
llvm-svn: 53137
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moves in order to get correct debug info. Since
I can't imagine how any target could possibly
be any different, I've just stripped out the
option: now all the world's like Darwin!
llvm-svn: 53134
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llvm-svn: 53123
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slow the compiler down at -O0 some 30% or more. Ooops.
llvm-svn: 53120
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llvm-svn: 53110
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llvm-svn: 53109
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there won't be a value number match. This speeds up GVN on a case where there are very few redundancies by ~25%.
llvm-svn: 53108
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not handle all cases and keeps invalid dom info around some cases, which misleads other passes down stream.
Right now, dom info is recaluclated in the end if the loop is switched.
llvm-svn: 53106
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because, as Eli pointed out, SimplifyCFG already does this.
llvm-svn: 53104
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propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc.
- Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list.
llvm-svn: 53097
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llvm-svn: 53092
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processed separately. Honour such situation and emit PIC relocations properly
in such case.
llvm-svn: 53091
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