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* [X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX ↵Ayman Musa2017-03-073-1193/+8
| | | | | | | | | | | | compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
* [X86][AVX512] Add missing entries to EVEX2VEX tablesAyman Musa2017-03-071-28/+61
| | | | | | | | evex2vex pass defines 2 tables which maps EVEX instructions to their VEX identical when possible. Adding all missing entries. Differential Revision: https://reviews.llvm.org/D30501 llvm-svn: 297126
* Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce ↵Tim Shen2017-03-071-43/+5
| | | | | | | | | | | stack frame size" This reverts commit r296771. We found some wide spread test failures internally. I'm working on a testcase. Politely revert the patch in the mean time. :) llvm-svn: 297124
* [LoopUnrolling] Fix loop size check for peelingSanjoy Das2017-03-071-1/+3
| | | | | | | | | | | | | | | | | | Summary: We should check if loop size allows us to peel at least one iteration before we do so. Patch by Max Kazantsev! Reviewers: sanjoy, mkuper, efriedma Reviewed By: mkuper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30632 llvm-svn: 297122
* [APInt] Add rvalue reference support to and, or, xor operations to allow ↵Craig Topper2017-03-071-25/+0
| | | | | | | | | | | | | | | | their memory allocation to be reused when possible This extends an earlier change that did similar for add and sub operations. With this first patch we lose the fastpath for the single word case as operator&= and friends don't support it. This can be added there if we think that's important. I had to change some functions in the APInt class since the operator overloads were moved out of the class and can't be used inside the class now. The getBitsSet change collides with another outstanding patch to implement it with setBits. But I didn't want to make this patch dependent on that series. I've also removed the Or, And, Xor functions which were rarely or never used. I already commited two changes to remove the only uses of Or that existed. Differential Revision: https://reviews.llvm.org/D30612 llvm-svn: 297121
* Revert "AMDGPU: Set MCAsmInfo::PointerSize"Konstantin Zhuravlyov2017-03-071-1/+0
| | | | | | | | It breaks line tables because the patch is not complete, working on a complete one at the moment This reverts commit r294031. llvm-svn: 297118
* Use LLVM for all stat-related functionality.Zachary Turner2017-03-071-0/+7
| | | | | | | | | | This deletes LLDB's FileType enumeration and replaces all users, and all calls to functions that check whether a file exists etc with corresponding calls to LLVM. Differential Revision: https://reviews.llvm.org/D30624 llvm-svn: 297116
* [APInt] Add setLowBits/setHighBits methods to APInt.Craig Topper2017-03-071-29/+23
| | | | | | | | | | | | | | | | | | | | | Summary: There are quite a few places in the code base that do something like the following to set the high or low bits in an APInt. KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1); For BitWidths larger than 64 this creates a short lived APInt with malloced storage. I think it might even call malloc twice. Its better to just provide methods that can set the necessary bits without the temporary APInt. I'll update usages that benefit in a separate patch. Reviewers: majnemer, MatzeB, davide, RKSimon, hans Reviewed By: hans Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30525 llvm-svn: 297111
* Un-XFAIL Fuzzer/test/dump_coverage.test. This now passes on Darwin (after ↵Kuba Mracek2017-03-071-2/+0
| | | | | | r297094). llvm-svn: 297110
* [SLP] Revert r296863 due to miscompiles.Michael Kuperstein2017-03-062-103/+80
| | | | | | Details and reproducer are on the email thread for r296863. llvm-svn: 297103
* GlobalISel: restrict G_EXTRACT instruction to just one operand.Tim Northover2017-03-0610-76/+73
| | | | | | | A bit more painful than G_INSERT because it was more widely used, but this should simplify the handling of extract operations in most locations. llvm-svn: 297100
* [libfuzzer] do not use xargs for shell expansionMike Aizatsky2017-03-061-1/+1
| | | | | | | | | Summary: After https://reviews.llvm.org/rL296904 xargs shouldn't be necesssary. Differential Revision: https://reviews.llvm.org/D30371 llvm-svn: 297094
* [InstCombine] use dyn_cast instead of isa+cast; NFCISanjay Patel2017-03-061-15/+12
| | | | llvm-svn: 297092
* [ObjectYAML] Support for DW_FORM_implicit_const DWARF5 formChris Bieneman2017-03-062-0/+4
| | | | | | | | This patch adds support to the DWARF YAML reader and writer for the new DWARF5 abbreviation form, DW_FORM_implicit_const. The attribute was added in r291599. llvm-svn: 297091
* [DAG] refactor related div/rem folds; NFCISanjay Patel2017-03-061-28/+32
| | | | | | | | | | | This is known incomplete and not called in the right order relative to other folds, but that's the current behavior. I'm just trying to clean this up before making actual functional changes to make the patch smaller. The logic here should mimic the IR equivalents that are in InstSimplify's simplifyDivRem(). llvm-svn: 297086
* [DWARFv5] Update definitions to match published spec.Paul Robinson2017-03-064-9/+50
| | | | | | | | | | | | | Some late additions to DWARF v5 were not in Dwarf.def; also one form was redefined. Add the new cases to relevant switches in different parts of LLVM. Replace DW_FORM_ref_sup with DW_FORM_ref_sup[4,8]. I did not add support for DW_FORM_strx3/addrx3 other that defining the constants. We don't have any infrastructure to support these. Differential Revision: http://reviews.llvm.org/D30664 llvm-svn: 297085
* [Outliner] Fixed Asan bot failure in r296418Jessica Paquette2017-03-066-0/+1506
| | | | | | | | Fixed the asan bot failure which led to the last commit of the outliner being reverted. The change is in lib/CodeGen/MachineOutliner.cpp in the SuffixTree's constructor. LeafVector is no longer initialized using reserve but just a standard constructor. llvm-svn: 297081
* [AArch64][Redundant Copy Elim] Add support for CMN and shifted imm.Chad Rosier2017-03-061-6/+13
| | | | | | | | | | This patch extends the current functionality of the AArch64 redundant copy elimination pass to handle CMN instructions as well as a shifted immediates. Differential Revision: https://reviews.llvm.org/D30576. llvm-svn: 297078
* Disable gvn-hoist (PR32153)Hans Wennborg2017-03-061-2/+2
| | | | llvm-svn: 297075
* Verifier: Change Assert to AssertDI.Adrian Prantl2017-03-061-3/+3
| | | | | | | This error can be recovered from by stripping debug info. This is NFC for +asserts builds. llvm-svn: 297072
* [ObjectYAML] NFC. Refactor DWARFYAML CompileUnit dump codeChris Bieneman2017-03-064-122/+324
| | | | | | | | | | | | Summary: This patch refactors the DWARFYAML code for dumping compile units to use a visitor pattern. Using this design will, in the future, enable the DWARF YAML code to perform analysis and mutations of the DWARF DIEs. An example of such mutations would be calculating the length of a compile unit and updating the CU's Length field before writing the DIE. This support will make it easier to craft or modify DWARF tests by hand. Reviewers: lhames Subscribers: mgorny, fhahn, jgosnell, aprantl, llvm-commits Differential Revision: https://reviews.llvm.org/D30357 llvm-svn: 297067
* AMDGPU/R600: Fix ALU clause markers use detectionJan Vesely2017-03-061-2/+5
| | | | | | | | also exit early on kill instead of redefinition. Differential Revision: https://reviews.llvm.org/D30230 llvm-svn: 297060
* [IfConversion] Only renormalize probabilities if branches are analyzableKrzysztof Parzyszek2017-03-061-2/+4
| | | | | | | | | | | If a block has non-analyzable branches, the listed successors don't need to add up to one. For example, if a block has a conditional tail call, that tail call will not have a corresponding successor in the successor list, but will still be a possible branch. Differential Revision: https://reviews.llvm.org/D30556 llvm-svn: 297054
* [InstSimplify] refactor related div/rem folds; NFCISanjay Patel2017-03-061-47/+37
| | | | llvm-svn: 297052
* GlobalISel: don't emit degenerate G_INSERT instructions.Tim Northover2017-03-061-0/+25
| | | | | | | | | | | Before, we were producing G_INSERT instructions that were actually closer to a cast or even a COPY when both input and output sizes are the same. This doesn't really make sense and means that everything interpreting a G_INSERT also has to handle all these kinds of casts. So now we detect these degenerate cases and emit real casts instead. llvm-svn: 297051
* NewGVN: Remove DebugUnknownExprs, just mark the instructions as unusedDaniel Berlin2017-03-061-7/+3
| | | | llvm-svn: 297047
* NewGVN: Only call isInstructionTrivially dead once per instruction.Daniel Berlin2017-03-061-9/+10
| | | | llvm-svn: 297046
* [X86] Fix arg copy elision for illegal typesReid Kleckner2017-03-061-37/+33
| | | | | | | | | | | Use the store size of the argument type, which will be a byte-sized quantity, rather than dividing the size in bits by 8. Fixes PR32136 and re-enables copy elision from i64 arguments. Reverts the workaround in from r296950. llvm-svn: 297045
* GlobalISel: add buildUndef method to MachineIRBuilder. NFC.Tim Northover2017-03-062-1/+5
| | | | llvm-svn: 297044
* GlobalISel: refactor legalization of G_INSERT.Tim Northover2017-03-061-37/+23
| | | | | | | | Now that G_INSERT instructions can only insert one register, this code was overly general. In another direction it didn't handle registers that crossed split boundaries properly, which needed to be fixed. llvm-svn: 297042
* Remove the sample pgo annotation heuristic that uses call count to annotate ↵Dehao Chen2017-03-061-5/+3
| | | | | | | | | | | | | | | | basic block count. Summary: We do not need that special handling because the debug info is more accurate now. Performance testing shows no regression on google internal benchmarks. Reviewers: davidxl, aprantl Reviewed By: aprantl Subscribers: llvm-commits, aprantl Differential Revision: https://reviews.llvm.org/D30658 llvm-svn: 297038
* [Hexagon] Early-if-convert branches that may exit the loopKrzysztof Parzyszek2017-03-061-63/+106
| | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033
* [Hexagon] Mark dead defs as <dead> in expand-condsetsKrzysztof Parzyszek2017-03-061-12/+28
| | | | | | | | | The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-063-4/+25
| | | | llvm-svn: 297031
* [InstSimplify] remove misleading comments; NFCSanjay Patel2017-03-061-2/+2
| | | | | | Div/rem-of-0 does not cause faults/undef (not the same as div/rem-by-0). llvm-svn: 297029
* [DAGCombiner] simplify div/rem-by-0Sanjay Patel2017-03-061-1/+10
| | | | | | | | | | | | | | | | | Refactoring of duplicated code and more fixes to follow. This is motivated by the post-commit comments for r296699: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html Ie, we can crash if we're missing obvious simplifications like this that exist in the IR simplifier or if these occur later than expected. The x86 change for non-splat division shows a potential opportunity to improve vector codegen: we assumed that since only one lane had meaningful results, we should do the math in scalar. But that means moving back and forth from vector registers. llvm-svn: 297026
* Silence a warning "hiding virtual function".Vassil Vassilev2017-03-061-0/+1
| | | | llvm-svn: 297018
* [BasicBlockUtils] Check for nullptr before updating LoopInfo.Michael Kruse2017-03-061-3/+4
| | | | | | | | | | | | | | | | LoopInfo::getLoopFor returns nullptr if a BB is not in a loop and only then can the loop be updated to contain the newly created BBs. Add the missing nullptr check to SplitBlockAndInsertIfThen. Within LLVM, the only user of this function that also passes a LoopInfo to be updated is InnerLoopVectorizer::predicateInstructions(). As the method's name implies, the BB operataten on will always be within a loop, but out-of-tree users may also use it differently (here: Polly). All other uses of LoopInfo::getLoopFor in the file properly check its return value for nullptr. llvm-svn: 297016
* [DAG] fix formatting; NFCSanjay Patel2017-03-061-2/+1
| | | | llvm-svn: 297015
* [DAG] fix typo in comment; NFCSanjay Patel2017-03-061-1/+1
| | | | llvm-svn: 297011
* [PowerPC] Fix failure with STBRX when store is narrower than the bswapNemanja Ivanovic2017-03-061-2/+5
| | | | | | | | | | | Fixes a crash caused by r296811 by truncating the input of the STBRX node when the bswap is wider than i32. Fixes https://bugs.llvm.org/show_bug.cgi?id=32140 Differential Revision: https://reviews.llvm.org/D30615 llvm-svn: 297001
* [XRay] Allow logging the first argument of a function call.Dean Michael Berris2017-03-061-0/+3
| | | | | | | | | | | | | | | | | | | Summary: Functions with the "xray-log-args" attribute will have a special XRay sled kind emitted, for compiler-rt to copy any call arguments to your logging handler. For practical and performance reasons, only the first argument is supported, and only up to 64 bits. Reviewers: dberris Reviewed By: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29702 llvm-svn: 296998
* [SCEV] Decrease the recursion threshold for CompareValueComplexitySanjoy Das2017-03-051-6/+11
| | | | | | | | | | Fixes PR32142. r287232 accidentally increased the recursion threshold for CompareValueComplexity from 2 to 32. This change reverses that change by introducing a separate flag for CompareValueComplexity's threshold. llvm-svn: 296992
* [SelectionDAG] Fix vector splitting for *_EXTEND_VECTOR_INREG instructionsSimon Pilgrim2017-03-051-1/+6
| | | | | | Found by fuzz testing after rL296985 landed llvm-svn: 296989
* [X86] Silence GCC enum compare warning.Benjamin Kramer2017-03-051-2/+2
| | | | | | | | X86ISelLowering.cpp:26506:36: error: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' [-Werror=enum-compare] llvm-svn: 296986
* [X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG opsSimon Pilgrim2017-03-054-93/+136
| | | | | | | | | | | | As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT. We're missing a couple of shuffle combines that will be added in a future patch for review. Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases. Differential Revision: https://reviews.llvm.org/D30549 llvm-svn: 296985
* [SimplifyCFG] Use APInt::operator| instead of APInt::Or. NFCCraig Topper2017-03-051-1/+1
| | | | | | I'm looking to improve operator| to support rvalue references and may remove APInt::Or. llvm-svn: 296982
* [DAGCombine] Use APInt::operator|(uint64_t) instead of creating a temporary ↵Craig Topper2017-03-051-6/+6
| | | | | | | | APInt and calling APInt::Or. NFC This is more efficient by itself. But this is prep for a future patch that may remove APInt::Or while making operator| support rvalue references similar to add/sub. llvm-svn: 296981
* [x86] don't require a zext when forming ADC/SBBSanjay Patel2017-03-041-24/+29
| | | | | | | | | | | | | The larger goal is to move the ADC/SBB transforms currently in combineX86SetCC() to combineAddOrSubToADCOrSBB() because we're creating ADC/SBB in lots of places where we shouldn't. This was intended to be an NFC change, but avx-512 has something strange going on. It doesn't seem like any of the affected tests should really be using SET+TEST or ADC; a simple ADD could replace several instructions. But that's another bug... llvm-svn: 296978
* [DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)Sanjay Patel2017-03-043-2/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | select Cond, C +/- 1, C --> add(ext Cond), C -- with a target hook. This is part of the ongoing process to obsolete D24480. The motivation is to canonicalize to select IR in InstCombine whenever possible, so we need to have a way to undo that easily in codegen. PowerPC is an obvious winner for this kind of transform because it has fast and complete bit-twiddling abilities but generally lousy conditional execution perf (although this might have changed in recent implementations). x86 also sees some wins, but the effect is limited because these transforms already mostly exist in its target-specific combineSelectOfTwoConstants(). The fact that we see any x86 changes just shows that that code is a mess of special-case holes. We may be able to remove some of that logic now. My guess is that other targets will want to enable this hook for most cases. The likely follow-ups would be to add value type and/or the constants themselves as parameters for the hook. As the tests in select_const.ll show, we can transform any select-of-constants to math/logic, but the general transform for any 2 constants needs one more instruction (multiply or 'and'). ARM is one target that I think may not want this for most cases. I see infinite loops there because it wants to use selects to enable conditionally executed instructions. Differential Revision: https://reviews.llvm.org/D30537 llvm-svn: 296977
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