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* Fix incorrect alignment for NEON VST2b32_UPD.Johnny Chen2011-04-041-7/+132
| | | | | | rdar://problem/9225433 llvm-svn: 128841
* Insert code in the right location when lowering PowerPC atomics.Jakob Stoklund Olesen2011-04-041-2/+4
| | | | | | | This causes defs to dominate uses, no instructions after terminators, and other goodness. llvm-svn: 128836
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-047-32/+240
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Move transformation of JmpLink and related nodes done during instruction ↵Akira Hatanaka2011-04-042-59/+27
| | | | | | selection to Legalize phase. llvm-svn: 128830
* PowerPC atomic pseudos clobber CR0, they don't read it.Jakob Stoklund Olesen2011-04-042-2/+2
| | | | llvm-svn: 128829
* Use X0 instead of R0 for the zero register on ppc64.Jakob Stoklund Olesen2011-04-041-10/+13
| | | | | | The 32-bit R0 cannot be used where a 64-bit register is expected. llvm-svn: 128828
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-047-4/+81
| | | | llvm-svn: 128826
* Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger2011-04-043-50/+51
| | | | | | | | Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. llvm-svn: 128822
* Stop caching basic block index ranges now that SlotIndexes can keep up.Jakob Stoklund Olesen2011-04-043-30/+33
| | | | llvm-svn: 128821
* Delete leftover data members.Jakob Stoklund Olesen2011-04-041-4/+0
| | | | llvm-svn: 128820
* Remove some support for ReturnInsts with multiple operands, and forJay Foad2011-04-043-43/+5
| | | | | | | returning a scalar value in a function whose return type is a single- element structure or array. llvm-svn: 128810
* Region: Allow user control the printing style of the print function.Tobias Grosser2011-04-041-16/+16
| | | | | | Contributed by: etherzhhb@gmail.com llvm-svn: 128808
* Attempt to fix breakage from r128782 reported by Francois Pichet onEli Friedman2011-04-041-0/+3
| | | | | | | llvm-commits. (Not sure why it only breaks on Windows; maybe it has something to do with the iterator representation...) llvm-svn: 128802
* Start migrating mach-o dumping facilities to the object file out of aEric Christopher2011-04-031-0/+28
| | | | | | separate executable. llvm-svn: 128801
* Move Object.cpp out of VMCore and into Object.Eric Christopher2011-04-033-1/+1
| | | | llvm-svn: 128800
* Assorted bugfixes in object file handling:Eric Christopher2011-04-033-2/+34
| | | | | | | | | | | | | | | | | | | | | | | - Adds support for sniffing PE/COFF files on win32 (.exe and .dll) which are COFF files that have an MS-DOS compatibility stub on the front of them. - Fixes a bug in the COFFObjectFile's support for the Microsoft COFF extension for long symbol names, wherein it was attempting to parse the leading '/' in an extended symbol name reference as part of the integer offset. - Fixes bugs in COFFObjectFile and ELFObjectFile wherein section and symbol iterators were being returned with uninitialized bytes; the type DataRefImpl is a union between 2 32-bit words (d.a and d.b) and a single intptr_t word (p). Only p was being initialized, so in 32-bit builds the result would be iterators with random upper 32-bit words in their DataRefImpls. This caused random failures when seeking around in object files. Patch by Graydon Hoare! llvm-svn: 128799
* Add a set of C bindings for the Object interface.Eric Christopher2011-04-032-0/+60
| | | | | | Patch by Patrick Walton! llvm-svn: 128798
* PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman2011-04-021-1/+4
| | | | | | | | | | | after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. llvm-svn: 128782
* Don't assume something which might be a constant expression is an instruction.Eli Friedman2011-04-021-3/+3
| | | | | | | Based on PR9429, but no testcase because I can't figure out how to trigger it anymore given other changes to the relevant code. llvm-svn: 128781
* While SimplifyDemandedBits constant folds this, we can't rely on it here.Benjamin Kramer2011-04-021-2/+7
| | | | | | | | | | It's possible to craft an input that hits the recursion limits in a way that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits can infer which bits are zero. No test case as it depends on too many other things. Fixes PR9609. llvm-svn: 128777
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-022-35/+86
| | | | llvm-svn: 128767
* Use InterferenceCache in RegAllocGreedy.Jakob Stoklund Olesen2011-04-021-94/+46
| | | | llvm-svn: 128765
* Add an InterferenceCache class for caching per-block interference ranges.Jakob Stoklund Olesen2011-04-024-1/+300
| | | | | | | | When the greedy register allocator is splitting multiple global live ranges, it tends to look at the same interference data many times. The InterferenceCache class caches queries for unaltered LiveIntervalUnions. llvm-svn: 128764
* Use basic block numbers as indexes when mapping slot index ranges.Jakob Stoklund Olesen2011-04-021-11/+9
| | | | | | This is more compact and faster than using DenseMap. llvm-svn: 128763
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+31
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. llvm-svn: 128759
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-5/+13
| | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 llvm-svn: 128757
* Undo changes mistakenly made in revision 128750.Akira Hatanaka2011-04-022-27/+59
| | | | llvm-svn: 128751
* Insert space before ';' to prevent warnings.Akira Hatanaka2011-04-023-60/+28
| | | | llvm-svn: 128750
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+1
| | | | | | rdar://problem/9224276 llvm-svn: 128749
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+1
| | | | | | | | UNPREDICTABLE. rdar://problem/9224120 llvm-svn: 128748
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 llvm-svn: 128746
* Fix comment.Benjamin Kramer2011-04-011-2/+2
| | | | llvm-svn: 128745
* Tweaks to the icmp+sext-to-shifts optimization to address Frits' comments:Benjamin Kramer2011-04-011-6/+6
| | | | | | | | | | - Localize the check if an icmp has one use to a place where we know we're introducing something that's likely more expensive than a sext from i1. - Add an assert to make sure a case that would lead to a miscompilation is folded away earlier. - Fix a typo. llvm-svn: 128744
* Avoid de-referencing pass beginning of a basic block. No small test case ↵Evan Cheng2011-04-011-18/+21
| | | | | | possible. rdar://9216009 llvm-svn: 128743
* Remove redundant code. There are assignments to variables Base and Offset ↵Akira Hatanaka2011-04-011-5/+0
| | | | | | right after the code that is removed. llvm-svn: 128742
* Simplifies logic for printing target flags.Akira Hatanaka2011-04-013-34/+29
| | | | llvm-svn: 128741
* When the architecture is explicitly armv6 or thumbv6, we need to mark the ↵Owen Anderson2011-04-011-9/+15
| | | | | | object file appropriately. llvm-svn: 128739
* LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach2011-04-011-10/+5
| | | | llvm-svn: 128736
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-011-0/+8
| | | | | | | | should reject the instruction as invalid. llvm-svn: 128734
* Fix build.Benjamin Kramer2011-04-011-1/+2
| | | | llvm-svn: 128733
* InstCombine: Turn icmp + sext into bitwise/integer ops when the input has ↵Benjamin Kramer2011-04-011-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | only one unknown bit. int test1(unsigned x) { return (x&8) ? 0 : -1; } int test3(unsigned x) { return (x&8) ? -1 : 0; } before (x86_64): _test1: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax ret _test3: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax notl %eax ret after: _test1: shrl $3, %edi andl $1, %edi leal -1(%rdi), %eax ret _test3: shll $28, %edi movl %edi, %eax sarl $31, %eax ret llvm-svn: 128732
* InstCombine: Move (sext icmp) transforms into their own method. No intended ↵Benjamin Kramer2011-04-012-37/+43
| | | | | | functionality change. llvm-svn: 128731
* Add comments.Evan Cheng2011-04-011-2/+4
| | | | llvm-svn: 128730
* Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng2011-04-011-4/+8
| | | | | | should improve src line debug info when sdisel is used. rdar://9199118 llvm-svn: 128728
* Modifies MipsAsmPrinter::isBlockOnlyReachableByFallthrough so that it ↵Akira Hatanaka2011-04-011-1/+26
| | | | | | handles delay slots correctly. llvm-svn: 128724
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-3/+4
| | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 llvm-svn: 128722
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-012-223/+138
| | | | llvm-svn: 128718
* Initialize HasVMLxForwarding.Benjamin Kramer2011-04-011-0/+1
| | | | llvm-svn: 128709
* Various Instructions' resizeOperands() methods are only used to grow theJay Foad2011-04-011-54/+16
| | | | | | list of operands. Simplify and rename them accordingly. llvm-svn: 128708
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