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* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-173-3/+160
| | | | | | | | | | | | | | any scheduling heuristics nor does it build up any scheduling data structure that other heuristics use. It essentially linearize by doing a DFA walk but it does handle glues correctly. IMPORTANT: it probably can't handle all the physical register dependencies so it's not suitable for x86. It also doesn't deal with dbg_value nodes right now so it's definitely is still WIP. rdar://12474515 llvm-svn: 166122
* Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen2012-10-173-4/+4
| | | | | | | | | | | All callers of these functions really want the isPhysRegOrOverlapUsed() functionality which also checks aliases. For historical reasons, targets without register aliases were calling isPhysRegUsed() instead. Change isPhysRegUsed() to also check aliases, and switch all isPhysRegOrOverlapUsed() callers to isPhysRegUsed(). llvm-svn: 166117
* Add a loop vectorizer.Nadav Rotem2012-10-174-2/+814
| | | | llvm-svn: 166112
* Check for empty YMM use-def lists in X86VZeroUpper.Jakob Stoklund Olesen2012-10-171-1/+1
| | | | | | | | | | | The previous MRI.isPhysRegUsed(YMM0) would also return true when the function contains a call to a function that may clobber YMM0. That's most of them. Checking the use-def chains allows us to skip functions that don't explicitly mention YMM registers. llvm-svn: 166110
* Fix fallout from RegInfo => FrameLowering refactoring on MSP430.Anton Korobeynikov2012-10-174-16/+15
| | | | | | Patch by Job Noorman! llvm-svn: 166108
* misched: Better handling of invalid latencies in the machine modelAndrew Trick2012-10-171-2/+10
| | | | llvm-svn: 166107
* Support: Don't remove special files on signals.Daniel Dunbar2012-10-171-9/+21
| | | | | | | - Similar to Path::eraseFromDisk(), we don't want LLVM to remove things like /dev/null, even if it has the permission. llvm-svn: 166105
* [asan] better debug diagnostics in asan compiler moduleKostya Serebryany2012-10-171-4/+4
| | | | llvm-svn: 166102
* This just in, it is a *bad idea* to use 'udiv' on an offset ofChandler Carruth2012-10-171-3/+3
| | | | | | | | | | | a pointer. A very bad idea. Let's not do that. Fixes PR14105. Note that this wasn't *that* glaring of an oversight. Originally, these routines were only called on offsets within an alloca, which are intrinsically positive. But over the evolution of the pass, they ended up being called for arbitrary offsets, and things went downhill... llvm-svn: 166095
* Fix a really annoying "bug" introduced in r165941. The change from thatChandler Carruth2012-10-171-3/+3
| | | | | | | | | | | revision makes no sense. We cannot use the address space of the *post indexed* type to conclude anything about a *pre indexed* pointer type's size. More importantly, this index can never be over a pointer. We are indexing over arrays and vectors here. Of course, I have no test case here. Neither did the original patch. =/ llvm-svn: 166091
* Check SSSE3 instead of SSE4.1Michael Liao2012-10-171-2/+2
| | | | | | - All shuffle insns required, especially PSHUB, are added in SSSE3. llvm-svn: 166086
* Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao2012-10-172-22/+50
| | | | | | | | | | - MBB address is only valid as an immediate value in Small & Static code/relocation models. On other models, LEA is needed to load IP address of the restore MBB. - A minor fix of MBB in MC lowering is added as well to enable target relocation flag being propagated into MC. llvm-svn: 166084
* Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.Jakob Stoklund Olesen2012-10-171-23/+30
| | | | | | | | This is just as fast, and it makes it possible to avoid leaking the UsedPhysRegs BitVector implementation through MachineRegisterInfo::addPhysRegsUsed(). llvm-svn: 166083
* Use a typedef to reduce some typing and reformat code accordingly.Eric Christopher2012-10-161-12/+17
| | | | llvm-svn: 166077
* Variable name cleanup.Eric Christopher2012-10-161-4/+4
| | | | llvm-svn: 166076
* Avoid rematerializing a redef immediately after the old def.Jakob Stoklund Olesen2012-10-161-0/+7
| | | | | | | | | | | | | | | | | PR14098 contains an example where we would rematerialize a MOV8ri immediately after the original instruction: %vreg7:sub_8bit<def> = MOV8ri 9; GR32_ABCD:%vreg7 %vreg22:sub_8bit<def> = MOV8ri 9; GR32_ABCD:%vreg7 Besides being pointless, it is also wrong since the original instruction only redefines part of the register, and the value read by the new instruction is wrong. The problem was the LiveRangeEdit::allUsesAvailableAt() didn't special-case OrigIdx == UseIdx and found the wrong SSA value. llvm-svn: 166068
* Revert r166046 "Switch back to the old coalescer for now to fix the 32 bit bit"Jakob Stoklund Olesen2012-10-161-344/+1
| | | | | | A fix for PR14098, including the test case is in the next commit. llvm-svn: 166067
* [InstCombine] Teach InstCombine how to handle an obfuscated splat.Michael Gottesman2012-10-161-2/+5
| | | | | | | | | | | | An obfuscated splat is where the frontend poorly generates code for a splat using several different shuffles to create the splat, i.e., %A = load <4 x float>* %in_ptr, align 16 %B = shufflevector <4 x float> %A, <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef> %C = shufflevector <4 x float> %B, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 4, i32 undef> %D = shufflevector <4 x float> %C, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 4> llvm-svn: 166061
* [ms-inline asm] Add the helper function, isParseringInlineAsm(). To be used ↵Chad Rosier2012-10-161-0/+1
| | | | | | in a future commit. llvm-svn: 166054
* Simplify code. No functionality change.Jakub Staszak2012-10-161-7/+3
| | | | llvm-svn: 166053
* Check .rela instead of ELF64 for the compensation vaue resettingMichael Liao2012-10-161-2/+1
| | | | llvm-svn: 166051
* 80-col fixup.Jakub Staszak2012-10-161-1/+2
| | | | llvm-svn: 166050
* Teach DAG combine to fold (trunc (fptoXi x)) to (fptoXi x)Michael Liao2012-10-161-0/+46
| | | | llvm-svn: 166049
* Switch back to the old coalescer for now to fix the 32 bit bitRafael Espindola2012-10-161-1/+344
| | | | | | llvm+clang+compiler-rt bootstrap. llvm-svn: 166046
* Simplify potentially quadratic behavior while erasing elements from std::vector.Jakub Staszak2012-10-161-7/+1
| | | | llvm-svn: 166045
* Support v8f32 to v8i8/vi816 conversion through custom loweringMichael Liao2012-10-162-17/+39
| | | | | | | | - Add custom FP_TO_SINT on v8i16 (and v8i8 which is legalized as v8i16 due to vector element-wise widening) to reduce DAG combiner and its overhead added in X86 backend. llvm-svn: 166036
* This patch addresses PR13949.Bill Schmidt2012-10-161-6/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the PowerPC 64-bit ELF Linux ABI, aggregates of size less than 8 bytes are to be passed in the low-order bits ("right-adjusted") of the doubleword register or memory slot assigned to them. A previous patch addressed this for aggregates passed in registers. However, small aggregates passed in the overflow portion of the parameter save area are still being passed left-adjusted. The fix is made in PPCTargetLowering::LowerCall_Darwin_Or_64SVR4 on the caller side, and in PPCTargetLowering::LowerFormalArguments_64SVR4 on the callee side. The main fix on the callee side simply extends existing logic for 1- and 2-byte objects to 1- through 7-byte objects, and correcting a constant left over from 32-bit code. There is also a fix to a bogus calculation of the offset to the following argument in the parameter save area. On the caller side, again a constant left over from 32-bit code is fixed. Additionally, some code for 1, 2, and 4-byte objects is duplicated to handle the 3, 5, 6, and 7-byte objects for SVR4 only. The LowerCall_Darwin_Or_64SVR4 logic is getting fairly convoluted trying to handle both ABIs, and I propose to separate this into two functions in a future patch, at which time the duplication can be removed. The patch adds a new test (structsinmem.ll) to demonstrate correct passing of structures of all seven sizes. Eight dummy parameters are used to force these structures to be in the overflow portion of the parameter save area. As a side effect, this corrects the case when aggregates passed in registers are saved into the first eight doublewords of the parameter save area: Previously they were stored left-justified, and now are properly stored right-justified. This requires changing the expected output of existing test case structsinregs.ll. llvm-svn: 166022
* Issue:Stepan Dyatkovskiy2012-10-163-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack is formed improperly for long structures passed as byval arguments for EABI mode. If we took AAPCS reference, we can found the next statements: A: "If the argument requires double-word alignment (8-byte), the NCRN (Next Core Register Number) is rounded up to the next even register number." (5.5 Parameter Passing, Stage C, C.3). B: "The alignment of an aggregate shall be the alignment of its most-aligned component." (4.3 Composite Types, 4.3.1 Aggregates). So if we have structure with doubles (9 double fields) and 3 Core unused registers (r1, r2, r3): caller should use r2 and r3 registers only. Currently r1,r2,r3 set is used, but it is invalid. Callee VA routine should also use r2 and r3 regs only. All is ok here. This behaviour is guessed by rounding up SP address with ADD+BFC operations. Fix: Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and 8 byte alignment, we waste odd registers then. P.S.: I also improved LDRB_POST_IMM regression test. Since ldrb instruction will not generated by current regression test after this patch. llvm-svn: 166018
* Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.NAKAMURA Takumi2012-10-161-0/+41
| | | | | | | | | | | | | | | | | | | | | | | Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". Original message since r165661: My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code. llvm-svn: 166017
* Cleanup whitespace.Bill Wendling2012-10-161-1/+2
| | | | llvm-svn: 166016
* Move X86MCInstLower class definition into implementation file. It's not ↵Craig Topper2012-10-163-54/+25
| | | | | | needed outside. llvm-svn: 166014
* Cleanup whitespace.Bill Wendling2012-10-161-37/+35
| | | | llvm-svn: 166013
* Have AttributesImpl defriend the Attributes class.Bill Wendling2012-10-162-3/+3
| | | | llvm-svn: 166012
* Have AttrBuilder defriend the Attributes class.Bill Wendling2012-10-161-3/+3
| | | | llvm-svn: 166011
* Use the Attributes::get method which takes an AttrVal value directly to ↵Bill Wendling2012-10-163-34/+13
| | | | | | simplify the code a bit. No functionality change. llvm-svn: 166009
* Put simple c'tors inline.Bill Wendling2012-10-161-6/+1
| | | | llvm-svn: 166008
* Pass in the context to the Attributes::get method.Bill Wendling2012-10-161-1/+1
| | | | llvm-svn: 166007
* Fix filename in file header.Craig Topper2012-10-161-1/+1
| | | | llvm-svn: 166004
* misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick2012-10-162-8/+21
| | | | | | | | | allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. llvm-svn: 166001
* Remove unused BitVectors from getAllocatableSet().Jakob Stoklund Olesen2012-10-163-9/+1
| | | | llvm-svn: 165999
* Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen2012-10-156-17/+18
| | | | | | Clients can use the equivalent functions in MRI. llvm-svn: 165990
* Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao2012-10-157-1/+260
| | | | | | | | | | | - Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also used as a light-weight replacement of setjmp/longjmp which are used to implementation continuation, user-level threading, and etc. The support added in this patch ONLY addresses this usage and is NOT intended to support SjLj exception handling as zero-cost DWARF exception handling is used by default in X86. llvm-svn: 165989
* Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen2012-10-154-7/+5
| | | | | | All callers can simply use the corresponding MRI functions. llvm-svn: 165985
* Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen2012-10-1510-40/+25
| | | | | | | Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. llvm-svn: 165983
* Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen2012-10-152-9/+10
| | | | | | | | | | | | | Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. llvm-svn: 165982
* ARM: v1i64 and v2i64 VBSL intrinsic support.Jim Grosbach2012-10-151-0/+17
| | | | | | rdar://12502028 llvm-svn: 165981
* Move the Attributes::Builder outside of the Attributes class and into its ↵Bill Wendling2012-10-1516-71/+109
| | | | | | own class named AttrBuilder. No functionality change. llvm-svn: 165960
* [ms-inline asm] If we parsed a statement and the opcode is valid, then it's ↵Chad Rosier2012-10-152-5/+5
| | | | | | an instruction. llvm-svn: 165955
* Make sure we iterate over newly created instructions. Fixes pr13625. Testcase toRafael Espindola2012-10-151-0/+5
| | | | | | follow in one sec. llvm-svn: 165951
* misched: ILP scheduler for experimental heuristics.Andrew Trick2012-10-152-20/+197
| | | | llvm-svn: 165950
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