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* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-111-13/+38
| | | | | | of function parameters llvm-svn: 194410
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-1/+1
| | | | llvm-svn: 194409
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-10/+21
| | | | | | source operands, a vector, an element to insert, and a shift amount. llvm-svn: 194406
* CalcSpillWeights: give a better describing name to calculateSpillWeightsArnaud A. de Grandmaison2013-11-115-9/+10
| | | | | | | | Besides, this relates it more obviously to the VirtRegAuxInfo::calculateSpillWeightAndHint. No functionnal change. llvm-svn: 194404
* Unify the adding of enumerators with the construction of the enumeration.Eric Christopher2013-11-112-23/+25
| | | | llvm-svn: 194401
* Formatting.Eric Christopher2013-11-111-9/+8
| | | | llvm-svn: 194400
* 80-col.Eric Christopher2013-11-111-5/+7
| | | | llvm-svn: 194399
* Just pass the DIComposite type by value instead of by pointer.Eric Christopher2013-11-112-6/+6
| | | | llvm-svn: 194398
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-111-3/+25
| | | | | | instructions. llvm-svn: 194394
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-111-0/+18
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 llvm-svn: 194393
* Move debug message in vectorizerRenato Golin2013-11-111-4/+1
| | | | | | No functional change, just better reporting. llvm-svn: 194388
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+10
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. llvm-svn: 194384
* Simplify code. No functionality change.Benjamin Kramer2013-11-111-5/+1
| | | | llvm-svn: 194383
* [msan] Propagate origin for insertvalue, extractvalue.Evgeniy Stepanov2013-11-111-2/+2
| | | | llvm-svn: 194374
* [NVPTX] Blacklist TailDuplicate passJustin Holewinski2013-11-111-0/+1
| | | | | | | | This causes issues with virtual registers. We will likely need to fix TailDuplicate in the future, or introduce a new version that plays nicely with vregs. llvm-svn: 194373
* AArch64: refactor vector list creation to be more uniformTim Northover2013-11-111-101/+55
| | | | | | | | | | | Instructions taking a vector list (e.g. "ld2 {v0.2d, v1.d2}, [x0]") need a special register-class to deal with the constraints, and C++ code to support selection. However, that C++ code can be made reasonably uniform to simplify the selection process. Hence this patch. No functionality change, so no tests. llvm-svn: 194361
* CalculateSpillWeights does not need to be a passArnaud A. de Grandmaison2013-11-105-29/+14
| | | | | | | | | | Based on discussions with Lang Hames and Jakob Stoklund Olesen at the hacker's lab, and in the light of upcoming work on the PBQP register allocator, it was though that CalcSpillWeights does not need to be a pass. This change will enable to customize / tune the spill weight computation depending on the allocator. Update the documentation style while there. No functionnal change. llvm-svn: 194356
* Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus ↵Bill Wendling2013-11-101-168/+6
| | | | | | | | | | | | | a fix to PR17307 & 17308." This causes PR17852. This reverts commit d93e8a06b2ca09ab18f390cd514b7443e2e571f7. Conflicts: test/Transforms/GVN/cond_br2.ll llvm-svn: 194348
* Use type form of getIntPtrType.Matt Arsenault2013-11-103-4/+5
| | | | | | | | This should be inconsequential and is work towards removing the default address space arguments. llvm-svn: 194347
* SimplifyCFG has a heuristics for out-of-order processors that decides when ↵Nadav Rotem2013-11-101-1/+1
| | | | | | | | it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite. llvm-svn: 194346
* Use size function instead of manually calculating it.Matt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194345
* Teach MergeFunctions about address spacesMatt Arsenault2013-11-101-11/+19
| | | | llvm-svn: 194342
* IR: Refactor GEP range checks, reuse them for other parts of foldingDavid Majnemer2013-11-101-28/+51
| | | | llvm-svn: 194341
* Make method staticMatt Arsenault2013-11-102-2/+2
| | | | llvm-svn: 194340
* Fix missing C++ mode commentMatt Arsenault2013-11-101-1/+1
| | | | llvm-svn: 194339
* Mostly finish up constant islands port for Mips for load constants.Reed Kotler2013-11-101-3/+20
| | | | | | | Still need to finish the branch part. Still lots more review of the code, clean up and testing. llvm-svn: 194337
* Remove some unnecessary temporary strings.Benjamin Kramer2013-11-092-6/+5
| | | | llvm-svn: 194335
* [arm] Refine ARMBuildAttrs.h.Logan Chien2013-11-091-6/+8
| | | | | | | | This commit cleans up some comments in ARMBuildAttrs.h. Besides, this commit fixes an error related to AllowWMMXv1 and AllowWMMXv2 (although they are not used currently.) llvm-svn: 194327
* Move the old pass manager infrastructure into a legacy namespace andChandler Carruth2013-11-093-14/+22
| | | | | | | | | | | | | | | | | | | give the files a legacy prefix in the right directory. Use forwarding headers in the old locations to paper over the name change for most clients during the transitional period. No functionality changed here! This is just clearing some space to reduce renaming churn later on with a new system. Even when the new stuff starts to go in, it is going to be hidden behind a flag and off-by-default as it is still WIP and under development. This patch is specifically designed so that very little out-of-tree code has to change. I'm going to work as hard as I can to keep that the case. Only direct forward declarations of the PassManager class are impacted by this change. llvm-svn: 194324
* Re-apply r194300 with fixes for warnings.Lang Hames2013-11-091-14/+14
| | | | llvm-svn: 194311
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-091-3/+5
| | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. llvm-svn: 194309
* Revert r194300 which broke the build.Nick Lewycky2013-11-091-14/+14
| | | | llvm-svn: 194308
* [Stackmap] Materialize the jump address within the patchpoint noop slide.Juergen Ributzka2013-11-095-7/+44
| | | | | | | | | | | | | | | This patch moves the jump address materialization inside the noop slide. This enables patching of the materialization itself or its complete removal. This patch also adds the ability to define scratch registers that can be used safely by the code called from the patchpoint intrinsic. At least one scratch register is required, because that one is used for the materialization of the jump address. This patch depends on D2009. Differential Revision: http://llvm-reviews.chandlerc.com/D2074 Reviewed by Andy llvm-svn: 194306
* Revert "Move copying of global initializers below the cloning of functions."Adrian Prantl2013-11-091-4/+4
| | | | | | | | This would cause internal symbols that are only referenced by global initializers to be removed. This reverts commit 194219. llvm-svn: 194304
* Rewrite the PBQP graph data structure.Lang Hames2013-11-091-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The new graph structure replaces the node and edge linked lists with vectors. Free lists (well, free vectors) are used for fast insertion/deletion. The ultimate aim is to make PBQP graphs cheap to clone. The motivation is that the PBQP solver destructively consumes input graphs while computing a solution, forcing the graph to be fully reconstructed for each round of PBQP. This imposes a high cost on large functions, which often require several rounds of solving/spilling to find a final register allocation. If we can cheaply clone the PBQP graph and incrementally update it between rounds then hopefully we can reduce this cost. Further, once we begin pooling matrix/vector values (future work), we can cache some PBQP solver metadata and share it between cloned graphs, allowing the PBQP solver to re-use some of the computation done in earlier rounds. For now this is just a data structure update. The allocator and solver still use the graph the same way as before, fully reconstructing it between each round. I expect no material change from this update, although it may change the iteration order of the nodes, causing ties in the solver to break in different directions, and this could perturb the generated allocations (hopefully in a completely benign way). Thanks very much to Arnaud Allard de Grandmaison for encouraging me to get back to work on this, and for a lot of discussion and many useful PBQP test cases. llvm-svn: 194300
* [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.Juergen Ributzka2013-11-0814-47/+205
| | | | | | | | | | | | | | The idea of the AnyReg Calling Convention is to provide the call arguments in registers, but not to force them to be placed in a paticular order into a specified set of registers. Instead it is up tp the register allocator to assign any register as it sees fit. The same applies to the return value (if applicable). Differential Revision: http://llvm-reviews.chandlerc.com/D2009 Reviewed by Andy llvm-svn: 194293
* increase the accuracy of register pressure computation in the presence of ↵Pedro Artigas2013-11-082-16/+36
| | | | | | dead definitions by using live intervals, if available, to identify dead definitions and proceed accordingly. llvm-svn: 194286
* X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()Jim Grosbach2013-11-081-1/+3
| | | | | | | | | | On darwin, when trying to create compact unwind info, a .cfi_cfa_def directive would case an llvm_unreachable() to be hit. Back off when we see this directive and generate the regular DWARF style eh_frame. rdar://15406518 llvm-svn: 194285
* Fix some minor issues with r194282 to get the tree healthy again.Lang Hames2013-11-081-1/+2
| | | | llvm-svn: 194284
* Add a method to get the object-file appropriate stack map section.Lang Hames2013-11-082-2/+4
| | | | | | Thanks to Eric Christopher for the tips on the appropriate way to do this. llvm-svn: 194282
* Remove dead code from LoopUnswitchHal Finkel2013-11-081-127/+0
| | | | | | | | | | | | LoopUnswitch's code simplification routine has logic to convert conditional branches into unconditional branches, after unswitching makes the condition constant, and then remove any blocks that renders dead. Unfortunately, this code is dead, currently broken, and furthermore, has never been alive (at least as far back at 2006). No functionality change intended. llvm-svn: 194277
* Revert "CalculateSpillWeights does not need to be a pass"Arnaud A. de Grandmaison2013-11-085-9/+29
| | | | | | Temporarily revert my previous commit until I understand why it breaks 3 target tests. llvm-svn: 194272
* [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when settingQuentin Colombet2013-11-081-1/+5
| | | | | | | isPhysRegUsed if the unwind information is required. Indeed, the runtime may need a correct stack to be able to unwind the call. llvm-svn: 194271
* Make PrintAsmOperand call to the superclass to handle 'n' and 'c' operand ↵Richard Barton2013-11-081-6/+2
| | | | | | modifiers. llvm-svn: 194270
* CalculateSpillWeights does not need to be a passArnaud A. de Grandmaison2013-11-085-29/+9
| | | | | | | | | | Based on discussions with Lang Hames and Jakob Stoklund Olesen at the hacker's lab, and in the light of upcoming work on the PBQP register allocator, it was though that CalcSpillWeights does not need to be a pass. This change will enable to customize / tune the spill weight computation depending on the allocator. Update the documentation style while there. No functionnal change. llvm-svn: 194269
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-084-32/+166
| | | | | | | | | | | | | | | | | | ARM prologues usually look like: push {r7, lr} sub sp, sp, #4 If code size is extremely important, this can be optimised to the single instruction: push {r6, r7, lr} where we don't actually care about the contents of r6, but pushing it subtracts 4 from sp as a side effect. This should implement such a conversion, predicated on the "minsize" function attribute (-Oz) since I've yet to find any code it actually makes faster. llvm-svn: 194264
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-8/+21
| | | | | | ARMv8 (Thumb encodings) llvm-svn: 194263
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-082-9/+24
| | | | | | ARMv8 (ARM encodings) llvm-svn: 194261
* CalculateSpillWeights cleanup: remove unneeded includesArnaud A. de Grandmaison2013-11-081-2/+0
| | | | llvm-svn: 194259
* [mips][msa] Update encoding of LDI instruction.Matheus Almeida2013-11-081-4/+4
| | | | | | The encoding was updated in MSA r1.07. llvm-svn: 194255
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