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* Add MSP430 InstPrinter stubAnton Korobeynikov2009-10-213-0/+84
| | | | llvm-svn: 84701
* Use proper target dataAnton Korobeynikov2009-10-211-1/+1
| | | | llvm-svn: 84700
* Respect src register allocation requirements when breaking ↵David Goodwin2009-10-201-17/+20
| | | | | | anti-dependencies. Remove some dead code. llvm-svn: 84691
* Cosmetic changes.Devang Patel2009-10-202-10/+10
| | | | | | | | s/validName/isValidName/g s/with an Instruction/to an Instruction/g s/RegisterMDKind/registerMDKind/g llvm-svn: 84689
* Fix -Asserts warning.Daniel Dunbar2009-10-201-2/+3
| | | | llvm-svn: 84687
* Fix invalid for vector types fneg(bitconvert(x)) => bitconvert(x ^ sign)Anton Korobeynikov2009-10-201-4/+6
| | | | | | transform. llvm-svn: 84683
* Oops. Backing out 84681 - needs to wait for the indexing patch.Lang Hames2009-10-201-54/+35
| | | | llvm-svn: 84682
* Added some debugging output to pre-alloc splitting.Lang Hames2009-10-201-35/+54
| | | | llvm-svn: 84681
* Fix another place that calls Loop::contains a lot to construct a sortedDan Gohman2009-10-201-1/+4
| | | | | | | | container of the blocks and do efficient lookups. This makes isLoopSimplifyForm much faster on large loops, fixing a significant compile-time issue in builds with assertions enabled. llvm-svn: 84673
* Disable by default while debuggingJim Grosbach2009-10-201-1/+1
| | | | llvm-svn: 84669
* alternate fix for PR5258 which avoids worklist problems, with reduced testcase.Chris Lattner2009-10-201-11/+6
| | | | llvm-svn: 84667
* add cmd line opt to disable frame index reuse for ARM and T2. debug aid.Jim Grosbach2009-10-201-0/+7
| | | | llvm-svn: 84664
* Restore LoopUnswitch's block-oriented threshold. LoopUnswitch now checks bothDan Gohman2009-10-201-36/+27
| | | | | | | | | the estimated code size and the number of blocks when deciding whether to do a non-trivial unswitch. This protects it from some very undesirable worst-case behavior on large numbers of loop-unswitchable conditions, such as in the testcase in PR5259. llvm-svn: 84661
* Checkpoint more aggressive anti-dependency breaking for post-ra scheduler.David Goodwin2009-10-201-310/+477
| | | | llvm-svn: 84658
* Better handle instructions that re-def a scratch registerJim Grosbach2009-10-201-9/+18
| | | | llvm-svn: 84657
* Following r84485, add Defs = [EFLAGS] to the 32-bit lock instructions too.Dan Gohman2009-10-201-0/+2
| | | | llvm-svn: 84652
* Move the Function*->allocated blocks map from the JITMemoryManager to theJeffrey Yasskin2009-10-202-34/+30
| | | | | | | | | | | | | | | JITEmitter. I'm gradually making Functions auto-remove themselves from the JIT when they're destroyed. In this case, the Function needs to be removed from the JITEmitter, but the map recording which Functions need to be removed lived behind the JITMemoryManager interface, which made things difficult. This patch replaces the deallocateMemForFunction(Function*) method with a pair of methods deallocateFunctionBody(void *) and deallocateExceptionTable(void *) corresponding to the two startFoo/endFoo pairs. llvm-svn: 84651
* Register re-use for scavenged frame indices must check for re-deginitionJim Grosbach2009-10-201-0/+4
| | | | | | of the register in the instruction which kills the scavenged value. llvm-svn: 84641
* Make TranslateX86CC return COND_INVALID instead of aborting when itDan Gohman2009-10-201-4/+15
| | | | | | | | | | encounters an OEQ or UNE comparison, and update its callers to check for this return status and recover. This fixes a problem resulting from the LowerOperation hooks being called from LegalizeVectorOps, because LegalizeVectorOps only lowers vectors, so OEQ and UNE comparisons may still be at large. This fixes PR5092. llvm-svn: 84640
* Fix PR5258, jump-threading creating invalid PHIs.Torok Edwin2009-10-201-2/+10
| | | | | | | When an incoming value for a PHI is updated, we must also updated all other incoming values for the same BB to match, otherwise we create invalid PHIs. llvm-svn: 84638
* Fix PR4313: IPSCCP was not setting the lattice value for the invoke instructionTorok Edwin2009-10-201-2/+4
| | | | | | | | | | when the invoke had multiple return values: it set the lattice value only on the extractvalue. This caused the invoke's lattice value to remain the default (undefined), and later propagated to extractvalue's operand, which incorrectly introduces undefined behavior. llvm-svn: 84637
* Random #include pruning.Benjamin Kramer2009-10-201-1/+2
| | | | llvm-svn: 84632
* This file is replaeced by PIC16Section.h.Sanjiv Gupta2009-10-201-88/+0
| | | | llvm-svn: 84628
* implement some more easy hooks.Chris Lattner2009-10-202-3/+34
| | | | llvm-svn: 84614
* Implement some hooks, make printOperand abort if unknown modifiers areChris Lattner2009-10-202-9/+129
| | | | | | present. llvm-svn: 84613
* t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.Chris Lattner2009-10-201-2/+2
| | | | llvm-svn: 84611
* Wire up the ARM MCInst printer, for llvm-mc.Daniel Dunbar2009-10-202-8/+33
| | | | llvm-svn: 84600
* Re-apply r84295, with fixes to how the loop "top" and "bottom" blocks areDan Gohman2009-10-201-182/+343
| | | | | | | | | tracked. Instead of trying to manually keep track of these locations while doing complex modifications, just recompute them when they're needed. This fixes a bug in which the TopMBB and BotMBB were not correctly updated, leading to invalid transformations. llvm-svn: 84598
* Trim unnecessary includes.Evan Cheng2009-10-202-2/+0
| | | | llvm-svn: 84597
* Add getTopBlock and getBottomBlock member functions to MachineLoopInfo.Dan Gohman2009-10-201-0/+28
| | | | llvm-svn: 84596
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-202-15/+0
| | | | | | functions are not needed. llvm-svn: 84587
* If the physical register being spilled does not have an interval, spill its ↵Evan Cheng2009-10-201-5/+21
| | | | | | sub-registers instead. llvm-svn: 84586
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-203-25/+10
| | | | llvm-svn: 84585
* lower ARM::MOVi32imm properly.Chris Lattner2009-10-201-2/+36
| | | | llvm-svn: 84583
* add support for external symbols. The mc instprinter can now handleChris Lattner2009-10-202-3/+17
| | | | | | | reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing identical output except for superior formatting of constant pool entries. llvm-svn: 84582
* get fancy: support basic block operands. Yay for jumps.Chris Lattner2009-10-203-15/+12
| | | | llvm-svn: 84579
* add supprort for the 'sbit' operand, MOVi apparently has one.Chris Lattner2009-10-203-1/+11
| | | | llvm-svn: 84577
* add support for instruction predicates.Chris Lattner2009-10-202-3/+8
| | | | llvm-svn: 84575
* implement printSORegOperand, add lowering for the nasty and despicable ↵Chris Lattner2009-10-204-5/+75
| | | | | | MOVi2pieces :) llvm-svn: 84573
* Refs: A8-598.Jim Grosbach2009-10-202-10/+24
| | | | | | | | | Leave Inst{11-8}, which represents the starting byte index of the extracted result in the concatenation of the operands and is left unspecified. Patch by Johnny Chen. llvm-svn: 84572
* Add missing encoding bits to NLdSt class of instructions.Jim Grosbach2009-10-201-0/+4
| | | | | | Patch by Johnny Chen. llvm-svn: 84570
* X86 should ignore implicit regs when lowering to MCInst also,Chris Lattner2009-10-191-0/+2
| | | | | | no functionality change. llvm-svn: 84567
* handle addmode4 modifiers, fix a fixme in printRegisterListChris Lattner2009-10-192-10/+4
| | | | | | by ignoring all implicit regs when lowering. llvm-svn: 84566
* simplify by using the twine form of GetOrCreateSymbolChris Lattner2009-10-191-8/+5
| | | | llvm-svn: 84565
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-194-17/+3
| | | | llvm-svn: 84563
* use EmitLabel instead of text emissionChris Lattner2009-10-191-4/+6
| | | | llvm-svn: 84562
* add a twine version of MCContext::GetOrCreateSymbol.Chris Lattner2009-10-193-7/+16
| | | | llvm-svn: 84561
* lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entriesChris Lattner2009-10-193-6/+32
| | | | | | | | | | | | | like: @ BB#1: .align 2 LCPI1_0: .long L_.str-(LPC0+8) Note that proper indentation of the label :) llvm-svn: 84558
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-193-22/+35
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.Chris Lattner2009-10-193-5/+34
| | | | llvm-svn: 84553
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