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* Support: chunk writing on LinuxSaleem Abdulrasool2017-06-202-1/+16
| | | | | | | | This is a workaround for large file writes. It has been witnessed that write(2) failing with EINVAL (22) due to a large value (>2G). Thanks to James Knight for the help with coming up with a sane test case. llvm-svn: 305846
* AMDGPU: Allow vectorization of packed typesMatt Arsenault2017-06-202-8/+20
| | | | llvm-svn: 305844
* [codeview] Fully initialize DataSym when mapping from YAMLReid Kleckner2017-06-201-0/+2
| | | | | | | | | | In the object file, the section index and relative offset are typically zero, so make these YAML fields optional with a default. It looks like there may be more partially initialized symbol records, but this should fix the msan bot. llvm-svn: 305842
* [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32Stanislav Mekhanoshin2017-06-201-0/+2
| | | | | | | | | If there is an immediate operand we shall not shrink V_SUBB_U32 and V_ADDC_U32, it does not fit e32 encoding. Differential Revison: https://reviews.llvm.org/D34291 llvm-svn: 305840
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-206-6/+106
| | | | llvm-svn: 305838
* [GISel]: Add G_FMA opcode for fused multiply addsAditya Nandakumar2017-06-201-0/+7
| | | | | | | | https://reviews.llvm.org/D34372 Reviewed by dsanders llvm-svn: 305824
* AMDGPU: Do operand folding in program orderMatt Arsenault2017-06-201-5/+3
| | | | | | | | | Before it was possible to partially fold use instructions before the defs. After the xor is folded into a copy, the same mov can end up in the fold list twice, so on the second attempt it will fail expecting to see a register to fold. llvm-svn: 305821
* [PDB] Don't write uninitialized bytes to a PDB file.Zachary Turner2017-06-202-0/+3
| | | | | | | | | | There were certain fields that we didn't know how to write, as well as various padding bytes that we would ignore. This leads to garbage data in the PDB. While not strictly necessary, we should initialize these bytes to something meaningful, as it makes for easier binary comparison between PDBs. llvm-svn: 305819
* RegisterScavenging: Followup to r305625Matthias Braun2017-06-201-41/+38
| | | | | | | | | | | | | This does some improvements/cleanup to the recently introduced scavengeRegisterBackwards() functionality: - Rewrite findSurvivorBackwards algorithm to use the existing LiveRegUnit::accumulateBackward() code. This also avoids the Available and Candidates bitset and just need 1 LiveRegUnit instance (= 1 bitset). - Pick registers in allocation order instead of register number order. llvm-svn: 305817
* AMDGPU: Preserve undef when folding register operandsMatt Arsenault2017-06-201-0/+2
| | | | | | | | If the source was a copy of an undef register, this would produce a read of an undefined register which is a verifier error. llvm-svn: 305816
* [AMDGPU] Eliminate SGPR to VGPR copy when possibleStanislav Mekhanoshin2017-06-201-0/+30
| | | | | | | | SGPRs are generally cheaper, so try to use them over VGPRs. Differential Revision: https://reviews.llvm.org/D34130 llvm-svn: 305815
* AMDGPU: Fix crash with undef vreg input operandMatt Arsenault2017-06-201-1/+1
| | | | llvm-svn: 305814
* [PowerPC] fix trivial typos in comment, NFCHiroshi Inoue2017-06-201-1/+1
| | | | llvm-svn: 305813
* [GSoC] Flag value completion for clangYuka Takahashi2017-06-203-6/+39
| | | | | | | | | | | | This is patch for GSoC project, bash-completion for clang. To use this on bash, please run `source clang/utils/bash-autocomplete.sh`. bash-autocomplete.sh is code for bash-completion. In this patch, Options.td was mainly changed in order to add value class in Options.inc. llvm-svn: 305805
* [x86] enable CGP memcmp() expansion for 2/4/8 byte sizesSanjay Patel2017-06-203-1/+13
| | | | | | | | | There are a couple of potential improvements as seen in the IR and asm: 1. We're unnecessarily extending to a larger type to compare values. 2. The codegen for (select cond, 1, -1) could avoid a cmov. (or we could change the order of the compares, so we have a select with 0 operand) llvm-svn: 305802
* [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with ↵Simon Pilgrim2017-06-201-1/+2
| | | | | | | | >=16bit elements Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this llvm-svn: 305801
* DAG: correctly legalize UMULO.Tim Northover2017-06-201-11/+18
| | | | | | | | | We were incorrectly sign extending into the high word (as you would for SMULO) when legalizing UMULO in terms of a wider full multiplication. Patch by James Duley. llvm-svn: 305800
* [InstCombine] fix code/test comments for r305792; NFCSanjay Patel2017-06-201-1/+1
| | | | | | | These diffs were in the last version of the patch in D33342, but I accidentally committed the previous rev. llvm-svn: 305793
* [InstCombine] try to canonicalize xor-of-icmps to and-of-icmpsSanjay Patel2017-06-201-0/+24
| | | | | | | | | | | | | | | | We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine, but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds, we can use the truth table definition of xor: X ^ Y --> (X | Y) & !(X & Y) ...to see if we can convert the xor to and/or and then use the existing folds. http://rise4fun.com/Alive/J9v Differential Revision: https://reviews.llvm.org/D33342 llvm-svn: 305792
* [globalisel][tablegen] Add support for COPY_TO_REGCLASS.Daniel Sanders2017-06-202-10/+30
| | | | | | | | | | | | | | | | | | | | | | Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
* [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODOSimon Pilgrim2017-06-201-2/+0
| | | | | | Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks. llvm-svn: 305788
* [GlobalISel][X86] fix compilation error ( -Werror=unused-function )Igor Breger2017-06-201-2/+2
| | | | llvm-svn: 305786
* [SelectionDAG] Fix an use-after-free issue introduced in r305775.Haojian Wu2017-06-201-2/+2
| | | | | | vector.back() will be invalidated when memory reallocation happens. llvm-svn: 305785
* [GlobalISel][X86] Get correct RegClass for given RegBank.Igor Breger2017-06-201-17/+26
| | | | | | | | | | | | | | | | | | | Summary: In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: t.p.northover, guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33952 Conflicts: test/CodeGen/X86/GlobalISel/select-memop-scalar.mir llvm-svn: 305784
* [GlobalISel] combine not symmetric merge/unmerge nodes.Igor Breger2017-06-201-13/+58
| | | | | | | | | | | | | | | | Summary: In some cases legalization ends up with not symmetric merge/unmerge nodes. Transform it to merge/unmerge nodes. Reviewers: t.p.northover, qcolombet, zvi Reviewed By: t.p.northover Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33626 llvm-svn: 305783
* [SCEV][NFC] Fix a misleading description of AddOpsInlineThresholdMax Kazantsev2017-06-201-1/+1
| | | | | | | | | The description of this option was copy-pasted from another one and does not correspond to reality. Differential Revision: https://reviews.llvm.org/D34390 llvm-svn: 305782
* WasmObjectWriter.cpp: Tweak a comment line. [-Wdocumentation]NAKAMURA Takumi2017-06-201-1/+1
| | | | llvm-svn: 305777
* [ARM] Support constant pools in data when generating execute-only code.Alexandros Lamprineas2017-06-203-15/+44
| | | | | | | | | | | | | | | | | | Resubmission of r305387, which was reverted at r305390. The Address Sanitizer caught a stack-use-after-scope of a Twine variable. This is now fixed by passing the Twine directly as a function parameter. The ARM backend asserts against constant pool lowering when it generates execute-only code in order to prevent the generation of constant pools in the text section. It appears that target independent optimizations might generate DAG nodes that represent constant pools. By lowering such nodes as global addresses we don't violate the semantics of execute-only code and also it is guaranteed that execute-only behaves correct with the position-independent addressing modes that support execute-only code. Differential Revision: https://reviews.llvm.org/D33773 llvm-svn: 305776
* [SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumberMax Kazantsev2017-06-201-19/+59
| | | | | | | | | | The recursive implementation of CalcNodeSethiUllmanNumber may overflow stack on extremely long pred chains. This patch replaces it with an equivalent iterative implementation. Differential Revision: https://reviews.llvm.org/D33769 llvm-svn: 305775
* Fix unused function build error in lldSam Clegg2017-06-201-0/+2
| | | | | | | | | | | | The lld-x86_64-darwin13 is failing with: error: unused function 'operator<<' Wrap the declation in ifndef NDEBUG, which matches what is done in MipsELFObjectWriter.cpp. Differential Revision: https://reviews.llvm.org/D34384 llvm-svn: 305771
* [WebAssembly] Fix build failures introduced in r305769Sam Clegg2017-06-202-2/+2
| | | | | | | | | | | This fixes two build failures that only occur in certain configurations: - error: unused function 'operator<<' - error: control reaches end of non-void function Differential Revision: https://reviews.llvm.org/D34382 llvm-svn: 305770
* [WebAssembly] Add support for weak symbols in the binary formatSam Clegg2017-06-204-60/+259
| | | | | | | | | | | This also introduces the updated format for the "linking" section which can represent extra symbol information. See: https://github.com/WebAssembly/tool-conventions/pull/10 Differential Revision: https://reviews.llvm.org/D34019 llvm-svn: 305769
* [DAG] Simplify BaseIndexOffset. NFCI.Nirav Dave2017-06-201-59/+57
| | | | | | Remove tail calls and cleanup codeflow. llvm-svn: 305768
* [Coverage] PR33517: Check for failure to load func recordsVedant Kumar2017-06-201-0/+3
| | | | | | | | | | | | With PR33517, it became apparent that symbol table creation can fail when presented with malformed inputs. This patch makes that sort of error detectable, so llvm-cov etc. can fail more gracefully. Specifically, we now check that function records loaded from corrupted coverage mapping data are rejected, e.g when the recorded function name is garbage. Testing: check-{llvm,clang,profile}, some unit test updates. llvm-svn: 305767
* [ProfileData] PR33517: Check for failure of symtab creationVedant Kumar2017-06-205-10/+27
| | | | | | | | | | | | With PR33517, it became apparent that symbol table creation can fail when presented with malformed inputs. This patch makes that sort of error detectable, so llvm-cov etc. can fail more gracefully. Specifically, we now check that function names within the symbol table aren't empty. Testing: check-{llvm,clang,profile}, some unit test updates. llvm-svn: 305765
* AMDGPU: Fix scratch wave offset relative FI expansionMatt Arsenault2017-06-191-9/+20
| | | | | | | | The offset may not be an inline immediate, so this needs to be materialized into a register. The post-RA run of SIShrinkInstructions is able to fold it later if it can. llvm-svn: 305761
* [ExecutionEngine] Fix some Clang-tidy modernize-use-using and Include What ↵Eugene Zelenko2017-06-192-30/+53
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 305760
* [AMDGPU] Add infer address spaces pass before SROAStanislav Mekhanoshin2017-06-191-0/+8
| | | | | | | | | It adds it for the target after inlining but before SROA where we can get most out of it. Differential Revision: https://reviews.llvm.org/D34366 llvm-svn: 305759
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-194-28/+60
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 305757
* [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).Eugene Zelenko2017-06-196-125/+232
| | | | llvm-svn: 305755
* Mark LLVMTestingSupport as not installed in LLVMBuild.Zachary Turner2017-06-191-0/+1
| | | | | | This is causing downstream issues with llvm-config. llvm-svn: 305754
* [AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands ↵Geoff Berry2017-06-191-1/+2
| | | | | | (e.g. blockaddress). llvm-svn: 305752
* [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.Geoff Berry2017-06-191-2/+4
| | | | | | Fixes PR33491 and PR33512. llvm-svn: 305751
* [AArch64][Falkor] Refine load/store increment latencies.Geoff Berry2017-06-191-164/+242
| | | | | | Also fix LDXP & LDAXP write latency to avoid similar assert as PR33491 and PR33512. llvm-svn: 305750
* Fix typosMatt Arsenault2017-06-191-2/+2
| | | | llvm-svn: 305749
* AMDGPU: Cleanup CreateLiveInRegisterMatt Arsenault2017-06-195-34/+45
| | | | llvm-svn: 305748
* [BDCE] Add comments. NFCXin Tong2017-06-191-0/+2
| | | | llvm-svn: 305739
* [PATCH] [PGO] Fixed cast operation in ↵Ana Pazos2017-06-191-1/+1
| | | | | | | | | | | | | | emIntrinsicVisitor::instrumentOneMemIntrinsic. Reviewers: xur, efriedma, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34293 llvm-svn: 305737
* Revert r305382, it caused PR33513.Nico Weber2017-06-191-6/+6
| | | | llvm-svn: 305735
* [CGP, PowerPC] try to constant fold before creating loads for memcmp expansionSanjay Patel2017-06-191-3/+13
| | | | | | | | | | | | | | | This is the last step needed to avoid regressions for x86 before we flip the switch to allow expansion of the smallest set of memcpy() via CGP. The DAG version checks for constant strings, so we need to do that here too. FWIW, the 2 constant test is not handled by LibCallSimplifier::optimizeMemCmp() because that code is limited to 8-bit constant arrays. LibCallSimplifier will also fail to optimize some 1 constant tests because its alignment requirements are too strict (shouldn't require alignment for a constant operand). Differential Revision: https://reviews.llvm.org/D34071 llvm-svn: 305734
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