summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* llvm-dwarfdump: Add support for -debug-info=<offset>.Adrian Prantl2017-09-151-45/+53
| | | | | | | | | This is the first of many commits that enable selectively dumping just one record from the debug info. This reapplies r313412 with some extra qualification to appease GCC and MSVC. llvm-svn: 313419
* Revert "llvm-dwarfdump: Add support for -debug-info=<offset>."Adrian Prantl2017-09-151-53/+45
| | | | | | This reverts commit r313412 because of a g++ incompatibility. llvm-svn: 313413
* llvm-dwarfdump: Add support for -debug-info=<offset>.Adrian Prantl2017-09-151-45/+53
| | | | | | | This is the first of many commits that enable selectively dumping just one record from the debug info. llvm-svn: 313412
* [SLP] Revert r312791 and other necessary commits, except for TTI andChandler Carruth2017-09-151-245/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | CostModel. The original patch added support for horizontal min/max reductions to the SLP vectorizer. This patch causes LLVM to miscompile fairly simple signed min reductions. I have attached a test progrom to http://llvm.org/PR34635 that shows the behavior change after this patch. We found this in a test for the open source Eigen library, but also in other code. Unfortunately, the revert is moderately challenging. It required reverting: r313042: [SLP] Test with multiple uses of conditional op and wrong parent. r312853: [SLP] Fix buildbots, NFC. r312793: [SLP] Fix the warning about paths not returning the value, NFC. r312791: [SLP] Support for horizontal min/max reduction. And even then, I had to completely skip reverting the changes to TTI and CostModel because r312832 rewrote so much of this code. Plus, the cost modeling changes aren implicated in the miscompile, so they should be fine and will just not be used until this gets re-introduced. llvm-svn: 313409
* Name the sentinel value used for the location number of the undefined ↵Reid Kleckner2017-09-151-7/+9
| | | | | | register NFC llvm-svn: 313405
* [DebugInfo] Insert DW_OP_deref when spilling indirect DBG_VALUEsReid Kleckner2017-09-151-35/+53
| | | | | | | | | | | | | | | | | | | | | Summary: This comes up in optimized debug info for C++ programs that pass and return objects indirectly by address. In these programs, llvm.dbg.declare survives optimization, which causes us to emit indirect DBG_VALUE instructions. The fast register allocator knows to insert DW_OP_deref when spilling indirect DBG_VALUE instructions, but the LiveDebugVariables did not until this change. This fixes part of PR34513. I need to look into why this doesn't work at -O0 and I'll send follow up patches to handle that. Reviewers: aprantl, dblaikie, probinson Subscribers: qcolombet, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37911 llvm-svn: 313400
* [DebugInfo] Add missing DW_OP_deref when an NRVO pointer is spilledReid Kleckner2017-09-152-62/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Fixes PR34513. Indirect DBG_VALUEs typically come from dbg.declares of non-trivially copyable C++ objects that must be passed by address. We were already handling the case where the virtual register gets allocated to a physical register and is later spilled. That's what usually happens for normal parameters that aren't NRVO variables: they usually appear in physical register parameters, and are spilled later in the function, which would correctly add deref. NRVO variables are different because the dbg.declare can come much later after earlier instructions cause the incoming virtual register to be spilled. Also, clean up this code. We only need to look at the first operand of a DBG_VALUE, which eliminates the operand loop. Reviewers: aprantl, dblaikie, probinson Subscribers: MatzeB, qcolombet, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37929 llvm-svn: 313399
* [AutoUpgrade] Fix a compatibility issue with module flagSteven Wu2017-09-151-0/+18
| | | | | | | | | | | | | | | | | | | | | | Summary: After r304661, module flag to record objective-c image info section is encoded without whitespaces after comma. The new name is equivalent to the old one, except that when LTO a module built by old compiler and a module built by a new compiler, it will fail with conflicting values. Fix the issue by removing whitespaces in bitcode upgrade path. rdar://problem/34416934 Reviewers: compnerd Reviewed By: compnerd Subscribers: mehdi_amini, hans, llvm-commits Differential Revision: https://reviews.llvm.org/D37909 llvm-svn: 313398
* [WebAssembly] MC: Create wasm data segments based on MCSectionsSam Clegg2017-09-154-68/+76
| | | | | | | | | | | This means that we can honor -fdata-sections rather than always creating a segment for each symbol. It also allows for a followup change to add .init_array and friends. Differential Revision: https://reviews.llvm.org/D37876 llvm-svn: 313395
* [ConstantFold] Return the correct type when folding a GEP with vector indices.Davide Italiano2017-09-151-1/+12
| | | | | | | | | | | | | | | | As Eli pointed out (and I got wrong in the first place), langref says: "The getelementptr returns a vector of pointers, instead of a single address, when one or more of its arguments is a vector. In such cases, all vector arguments should have the same number of elements, and every scalar argument will be effectively broadcast into a vector during address calculation." Costantfold for gep doesn't really take in account this paragraph, returning a pointer instead of a vector of pointer which triggers an assertion in RAUW, as we're trying to replace values with mistmatching types. Differential Revision: https://reviews.llvm.org/D37928 llvm-svn: 313394
* Change encodeU/SLEB128 to pad to certain number of bytesSam Clegg2017-09-155-31/+31
| | | | | | | | | | | | | | | Previously the 'Padding' argument was the number of padding bytes to add. However most callers that use 'Padding' know how many overall bytes they need to write. With the previous code this would mean encoding the LEB once to find out how many bytes it would occupy and then using this to calulate the 'Padding' value. See: https://reviews.llvm.org/D36595 Differential Revision: https://reviews.llvm.org/D37494 llvm-svn: 313393
* This patch fixes https://bugs.llvm.org/show_bug.cgi?id=32352 Vivek Pandya2017-09-1510-101/+162
| | | | | | | | | | | It enables OptimizationRemarkEmitter::allowExtraAnalysis and MachineOptimizationRemarkEmitter::allowExtraAnalysis to return true not only for -fsave-optimization-record but when specific remarks are requested with command line options. The diagnostic handler used to be callback now this patch adds a class DiagnosticHandler. It has virtual method to provide custom diagnostic handler and methods to control which particular remarks are enabled. However LLVM-C API users can still provide callback function for diagnostic handler. llvm-svn: 313390
* [llvm] Fix some typos. NFC.Mandeep Singh Grang2017-09-154-5/+5
| | | | | | | | | | | | Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37922 llvm-svn: 313388
* This reverts r313381Vivek Pandya2017-09-1510-162/+101
| | | | llvm-svn: 313387
* [WebAssembly] Pass ArrayRef rather than SmallVectorSam Clegg2017-09-151-26/+20
| | | | | | | | This is more flexible and less verbose. Differential Revision: https://reviews.llvm.org/D37875 llvm-svn: 313384
* This patch fixes https://bugs.llvm.org/show_bug.cgi?id=32352 Vivek Pandya2017-09-1510-101/+162
| | | | | | | | | | | It enables OptimizationRemarkEmitter::allowExtraAnalysis and MachineOptimizationRemarkEmitter::allowExtraAnalysis to return true not only for -fsave-optimization-record but when specific remarks are requested with command line options. The diagnostic handler used to be callback now this patch adds a class DiagnosticHandler. It has virtual method to provide custom diagnostic handler and methods to control which particular remarks are enabled. However LLVM-C API users can still provide callback function for diagnostic handler. llvm-svn: 313382
* [WebAssembly] MC: Fix crash in getProvitionalValue on weak referencesSam Clegg2017-09-151-15/+15
| | | | | | | | | - Create helper function for resolving weak references. - Add test that preproduces the crash. Differential Revision: https://reviews.llvm.org/D37916 llvm-svn: 313381
* Revert r313343 "[X86] PR32755 : Improvement in CodeGen instruction selection ↵Hans Wennborg2017-09-153-490/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for LEAs." This caused PR34629: asserts firing when building Chromium. It also broke some buildbots building test-suite as reported on the commit thread. > Summary: > 1/ Operand folding during complex pattern matching for LEAs has been > extended, such that it promotes Scale to accommodate similar operand > appearing in the DAG. > e.g. > T1 = A + B > T2 = T1 + 10 > T3 = T2 + A > For above DAG rooted at T3, X86AddressMode will no look like > Base = B , Index = A , Scale = 2 , Disp = 10 > > 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs > so that if there is an opportunity then complex LEAs (having 3 operands) > could be factored out. > e.g. > leal 1(%rax,%rcx,1), %rdx > leal 1(%rax,%rcx,2), %rcx > will be factored as following > leal 1(%rax,%rcx,1), %rdx > leal (%rdx,%rcx) , %edx > > 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops, > thus avoiding creation of any complex LEAs within a loop. > > Reviewers: lsaba, RKSimon, craig.topper, qcolombet > > Reviewed By: lsaba > > Subscribers: spatel, igorb, llvm-commits > > Differential Revision: https://reviews.llvm.org/D35014 llvm-svn: 313376
* Fix Bug 30978 by emitting cv file checksums.Eric Beckmann2017-09-157-49/+165
| | | | | | | | | | | | Summary: The checksums had already been placed in the IR, this patch allows MCCodeView to actually write it out to an MCStreamer. Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37157 llvm-svn: 313374
* [X86] Prefer VPERMQ over VPERM2F128 for any unary shuffle, not just the ones ↵Craig Topper2017-09-151-3/+4
| | | | | | | | | | | | that can be done with a insertf128 The early out for AVX2 in lowerV2X128VectorShuffle is positioned in a weird spot below some shuffle mask equivalency checks. But I think we want to allow VPERMQ for any unary shuffle. Differential Revision: https://reviews.llvm.org/D37893 llvm-svn: 313373
* llvm-dwarfdump: Factor out the printing of the section header (NFC)Adrian Prantl2017-09-152-65/+68
| | | | llvm-svn: 313370
* [X86] Use SDNode::ops() instead of makeArrayRef and op_begin(). NFCICraig Topper2017-09-151-5/+5
| | | | llvm-svn: 313367
* [X86] Don't create i64 constants on 32-bit targets when lowering v64i1 ↵Craig Topper2017-09-151-0/+12
| | | | | | | | | | | | | | constant build vectors When handling a v64i1 build vector of constants on 32-bit targets we were creating an illegal i64 constant that we then bitcasted back to v64i1. We need to instead create two 32-bit constants, bitcast them to v32i1 and concat the result. We should also take care to handle the halves being all zeros/ones after the split. This patch splits the build vector and then recursively lowers the two pieces. This allows us to handle the all ones and all zeros cases with minimal effort. Ideally we'd just do the split and concat, and let lowering get called again on the new nodes, but getNode has special handling for CONCAT_VECTORS that reassembles the pieces back into a single BUILD_VECTOR. Hopefully the two temporary BUILD_VECTORS we had to create to do this that don't get returned don't cause any issues. Fixes PR34605. Differential Revision: https://reviews.llvm.org/D37858 llvm-svn: 313366
* [X86] Add isel pattern infrastructure to begin recognizing when we're ↵Craig Topper2017-09-151-0/+59
| | | | | | | | | | | | | | | | | | inserting 0s into the upper portions of a vector register and the producing instruction as already produced the zeros. Currently if we're inserting 0s into the upper elements of a vector register we insert an explicit move of the smaller register to implicitly zero the upper bits. But if we can prove that they are already zero we can skip that. This is based on a similar idea of what we do to avoid emitting explicit zero extends for GR32->GR64. Unfortunately, this is harder for vector registers because there are several opcodes that don't have VEX equivalent instructions, but can write to XMM registers. Among these are SHA instructions and a MMX->XMM move. Bitcasts can also get in the way. So for now I'm starting with explicitly allowing only VPMADDWD because we emit zeros in combineLoopMAddPattern. So that is placing extra instruction into the reduction loop. I'd like to allow PSADBW as well after D37453, but that's currently blocked by a bitcast. We either need to peek through bitcasts or canonicalize insert_subvectors with zeros to remove bitcasts on the value being inserted. Longer term we should probably have a cleanup pass that removes superfluous zeroing moves even when the producer is in another basic block which is something these isel tricks can't do. See PR32544. Differential Revision: https://reviews.llvm.org/D37653 llvm-svn: 313365
* [RuntimeUnroll] Add heuristic for unrolling multi-exit loopAnna Thomas2017-09-151-2/+34
| | | | | | | | | | | | | | | | | | | | | Add a profitability heuristic to enable runtime unrolling of multi-exit loop: There can be atmost two unique exit blocks for the loop and the second exit block should be a deoptimizing block. Also, there can be one other exiting block other than the latch exiting block. The reason for the latter is so that we limit the number of branches in the unrolled code to being at most the unroll factor. Deoptimizing blocks are rarely taken so these additional number of branches created due to the unrolling are predictable, since one of their target is the deopt block. Reviewers: apilipenko, reames, evstupac, mkuper Subscribers: llvm-commits Reviewed by: reames Differential Revision: https://reviews.llvm.org/D35380 llvm-svn: 313363
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-1529-13785/+2407
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [RuntimeUnrolling] Populate the VMap entry correctly when default generated ↵Anna Thomas2017-09-151-3/+7
| | | | | | | | | | | | | | | | | through lookup During runtime unrolling on loops with multiple exits, we update the exit blocks with the correct phi values from both original and remainder loop. In this process, we lookup the VMap for the mapped incoming phi values, but did not update the VMap if a default entry was generated in the VMap during the lookup. This default value is generated when constants or values outside the current loop are looked up. This patch fixes the assertion failure when null entries are present in the VMap because of this lookup. Added a testcase that showcases the problem. llvm-svn: 313358
* Revert "[SLPVectorizer] Failure to beneficially vectorize 'copyable' ↵Ilya Biryukov2017-09-151-317/+142
| | | | | | | | | elements in integer binary ops." This reverts commit r313348. Reason: it caused buildbot failures. llvm-svn: 313352
* [AArch64] allow v8f16 types when FullFP16 is supportedSjoerd Meijer2017-09-151-33/+31
| | | | | | | | | | | This adds support for allowing v8f16 vector types, thus avoiding conversions from/to single precision for these types. This is a follow up patch of commits r311154 and r312104, which added support for scalars and v4f16 types, respectively. Differential Revision: https://reviews.llvm.org/D37802 llvm-svn: 313351
* Recommit "[RegAlloc] Make sure live-ranges reflect the state of the IR whenJonas Paulsson2017-09-152-2/+8
| | | | | | | | | | | | | removing them" This was temporarily reverted, but now that the fix has been commited (r313197) it should be put back in place. https://bugs.llvm.org/show_bug.cgi?id=34502 This reverts commit 9ef93d9dc4c51568e858cf8203cd2c5ce8dca796. llvm-svn: 313349
* [SLPVectorizer] Failure to beneficially vectorize 'copyable' elements in ↵Dinar Temirbulatov2017-09-151-142/+317
| | | | | | | | | | | | | | | | | | | | | | integer binary ops. Patch tries to improve vectorization of the following code: void add1(int * __restrict dst, const int * __restrict src) { *dst++ = *src++; *dst++ = *src++ + 1; *dst++ = *src++ + 2; *dst++ = *src++ + 3; } Allows to vectorize even if the very first operation is not a binary add, but just a load. Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev, davide Subscribers: llvm-commits, RKSimon Differential Revision: https://reviews.llvm.org/D28907 llvm-svn: 313348
* [ORC] Fix a typo.Lang Hames2017-09-151-1/+1
| | | | llvm-svn: 313346
* [X86] PR32755 : Improvement in CodeGen instruction selection for LEAs.Jatin Bhateja2017-09-153-10/+490
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: 1/ Operand folding during complex pattern matching for LEAs has been extended, such that it promotes Scale to accommodate similar operand appearing in the DAG. e.g. T1 = A + B T2 = T1 + 10 T3 = T2 + A For above DAG rooted at T3, X86AddressMode will no look like Base = B , Index = A , Scale = 2 , Disp = 10 2/ During OptimizeLEAPass down the pipeline factorization is now performed over LEAs so that if there is an opportunity then complex LEAs (having 3 operands) could be factored out. e.g. leal 1(%rax,%rcx,1), %rdx leal 1(%rax,%rcx,2), %rcx will be factored as following leal 1(%rax,%rcx,1), %rdx leal (%rdx,%rcx) , %edx 3/ Aggressive operand folding for AM based selection for LEAs is sensitive to loops, thus avoiding creation of any complex LEAs within a loop. Reviewers: lsaba, RKSimon, craig.topper, qcolombet Reviewed By: lsaba Subscribers: spatel, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D35014 llvm-svn: 313343
* [SLPVectorizer] Remove duplicated functionality code in initScheduleData ↵Dinar Temirbulatov2017-09-151-6/+0
| | | | | | function, NFCI. llvm-svn: 313341
* [XRay] fix and clarify comments in the log file decoderMartin Pelikan2017-09-151-30/+24
| | | | | | | | | | | | | | | | | | | Summary: For readers unfamiliar with the XRay code base, reference the compiler-rt implementation even though we're not allowed to share any code and explain our little-endian views more clearly. For code clarity either get rid of obvious comments or explain their intentions, fix typos, correct coding style according to LLVM's standards and manually CSE long expressions to point out it is the same expression. Reviewers: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34339 llvm-svn: 313340
* [codeview] Use a type index of zero for static method "this" typesReid Kleckner2017-09-151-1/+1
| | | | | | | Otherwise VS won't show anything in the autos or watch window of static methods. llvm-svn: 313329
* Refactor collectChildrenInLoop to LoopUtils [NFC]Alina Sbirlea2017-09-152-23/+21
| | | | | | | | | | | | Summary: Move to LoopUtils method that collects all children of a node inside a loop. Reviewers: majnemer, sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37870 llvm-svn: 313322
* [WebAssembly] Use a separate wasm data segment for each global symbolSam Clegg2017-09-141-70/+88
| | | | | | | | | | This is stepping stone towards honoring -fdata-sections and letting the assembler decide how many wasm data segments to create. Differential Revision: https://reviews.llvm.org/D37834 llvm-svn: 313313
* Fix bug 34608 by moving private header out of public header.Eric Beckmann2017-09-141-0/+1
| | | | | | | | | | | | | | | | | | WindowsManifestMerger.h should not include llvm/Config/config.h, since it is private. The include has been moved to the source instead. Summary: The checksums had already been placed in the IR, this patch allows MCCodeView to actually write it out to an MCStreamer. Move private config.h header dependency out of public header file. Addresses Bug 34608 Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37863 llvm-svn: 313312
* [X86] Remove an unnecessary SmallVector from LowerBUILD_VECTOR.Craig Topper2017-09-141-4/+2
| | | | | | I think this may have existed to convert from SDUse to SDValue, but it doesn't look like its needed now. llvm-svn: 313311
* Fix warnings in r313297.Jan Sjodin2017-09-142-5/+3
| | | | llvm-svn: 313302
* AMDGPU: Fix violating constant bus restrictionMatt Arsenault2017-09-141-4/+5
| | | | | | You can't use madmk/madmk if it already uses an SGPR input. llvm-svn: 313298
* Add AddresSpace to PseudoSourceValue.Jan Sjodin2017-09-147-23/+65
| | | | | | Differential Revision: https://reviews.llvm.org/D35089 llvm-svn: 313297
* Subtarget support for parameterized register class informationKrzysztof Parzyszek2017-09-141-0/+12
| | | | | | | | Implement "checkFeatures" and emitting HW mode check code. Differential Revision: https://reviews.llvm.org/D31959 llvm-svn: 313295
* Remove usages of deprecated std::unary_function and std::binary_function.Benjamin Kramer2017-09-141-1/+1
| | | | | | | | | | These are removed in C++17. We still have some users of unary_function::argument_type, so just spell that typedef out. No functionality change intended. Note that many of the argument types are actually wrong :) llvm-svn: 313287
* AMDGPU: Fix assert on alloca of array of structMatt Arsenault2017-09-141-6/+5
| | | | llvm-svn: 313282
* [test] Fix TestDWARFDieRangeInfoIntersectsJonas Devlieghere2017-09-141-0/+2
| | | | | | Fixes heap buffer overflow triggered in DWARF verifier, detected by ASAN. llvm-svn: 313280
* AMDGPU: Stop modifying SP in call sequencesMatt Arsenault2017-09-141-3/+3
| | | | | | | | | | | | | | | Because the stack growth direction and addressing is done in the same direction, modifying SP at the beginning of the call sequence was incorrect. If we had a stack passed argument, we would end up skipping that number of bytes before pushing arguments, leaving unused/inconsistent space. The callee creates fixed stack objects in its frame, so the space necessary for these is already logically allocated in the callee, so we just let the callee increment SP if it really requires it. llvm-svn: 313279
* Invoke GetInlineCost for legality check before inline functions in ↵Dehao Chen2017-09-141-6/+37
| | | | | | | | | | | | | | | | SampleProfileLoader. Summary: SampleProfileLoader inlines hot functions if it is inlined in the profiled binary. However, the inline needs to be guarded by legality check, otherwise it could lead to correctness issues. Reviewers: eraman, davidxl Reviewed By: eraman Subscribers: vitalybuka, sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D37779 llvm-svn: 313277
* [mips] Implement the 'dext' aliases and it's disassembly alias.Simon Dardis2017-09-145-43/+162
| | | | | | | | | | | | | | | | The other members of the dext family of instructions (dextm, dextu) are traditionally handled by the assembler selecting the right variant of 'dext' depending on the values of the position and size operands. When these instructions are disassembled, rather than reporting the actual instruction, an equivalent aliased form of 'dext' is generated and is reported. This is to mimic the behaviour of binutils. Reviewers: slthakur, nitesh.jain, atanasyan Differential Revision: https://reviews.llvm.org/D34887 llvm-svn: 313276
OpenPOWER on IntegriCloud