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* [ARM] When a bitcast is about to be turned into a VMOVDRR, try to combine itQuentin Colombet2015-12-041-0/+55
| | | | | | | | | | | with its source instead of forcing the values on GPRs. This improves the lowering of vector code when such bitcasts happen in the middle of vector computations. rdar://problem/23691584 llvm-svn: 254684
* ScheduleDAGInstrs: Rework schedule graph builder.Matthias Braun2015-12-041-66/+161
| | | | | | | | | | | | | | | | | | Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
* raw_ostream: << operator for callables with raw_ostream argumentMatthias Braun2015-12-043-76/+64
| | | | | | | | | This is a revised version of r254655 which uses a Printable wrapper class to avoid ambiguous overload problems. Differential Revision: http://reviews.llvm.org/D14348 llvm-svn: 254681
* X86InstrInfo::copyPhysReg: workaround reg livenessJF Bastien2015-12-041-3/+13
| | | | | | | | | | | | | | | | | | | | | | Summary: computeRegisterLiveness and analyzePhysReg are currently getting confused about liveness in some cases, breaking copyPhysReg's calculation of whether AX is dead in some cases. Work around this issue temporarily by assuming that AX is always live. See detail in: https://llvm.org/bugs/show_bug.cgi?id=25033#c7 And associated bugs PR24535 PR25033 PR24991 PR24992 PR25201. This workaround makes the code correct but slightly inefficient, but it seems to confuse the machine instr verifier which now things EAX was undefined in some cases where it's being conservatively saved / restored. Reviewers: majnemer, sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15198 llvm-svn: 254680
* IR: Update a comment and a bool that've been out of date since 2012Justin Bogner2015-12-041-3/+2
| | | | | | | It became impossible to get here with a half in r157393, over 3 years ago. llvm-svn: 254679
* [PGO] Unify VP data format between raw and indexed profile (Reader)Xinliang David Li2015-12-041-38/+11
| | | | | | | | | | | With the latest refactoring and code sharing patches landed, it is possible to unify the value profile implementation between raw and indexed profile. This is the patch in raw profile reader that uses the common interface. Differential Revision: http://reviews.llvm.org/D15056 llvm-svn: 254677
* Emit function alias to data as a function symbol.Evgeniy Stepanov2015-12-041-0/+5
| | | | | | | | | | CFI emits jump slots for indirect functions as a byte array constant, and declares function-typed aliases to these constants. This change fixes AsmPrinter to emit these aliases as function symbols and not data symbols. llvm-svn: 254674
* [llvm-profdata] Add support for weighted merge of profile dataNathan Slingerland2015-12-041-2/+12
| | | | | | | | | | | | | | | | | | This change adds support for an optional weight when merging profile data with the llvm-profdata tool. Weights are specified by adding an option ':<weight>' suffix to the input file names. Adding support for arbitrary weighting of input profile data allows for relative importance to be placed on the input data from multiple training runs. Both sampled and instrumented profiles are supported. Reviewers: dnovillo, bogner, davidxl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14547 llvm-svn: 254669
* Simplify since this function never fails.Rafael Espindola2015-12-031-10/+2
| | | | llvm-svn: 254667
* CodeGen peephole: fold redundant phys reg copiesJF Bastien2015-12-031-12/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Code generation often exposes redundant physical register copies through virtual registers such as: %vreg = COPY %PHYSREG ... %PHYSREG = COPY %vreg There are cases where no intervening clobber of %PHYSREG occurs, and the later copy could therefore be removed. In some cases this further allows us to remove the initial copy. This patch contains a motivating example which comes from the x86 build of Chrome, specifically cc::ResourceProvider::UnlockForRead uses libstdc++'s implementation of hash_map. That example has two tests live at the same time, and after machine sinking LLVM has confused itself enough and things spilling EFLAGS is a great idea even though it's never restored and the comparison results are both live. Before this patch we have: DEC32m %RIP, 1, %noreg, <ga:@L>, %noreg, %EFLAGS<imp-def> %vreg1<def> = COPY %EFLAGS; GR64:%vreg1 %EFLAGS<def> = COPY %vreg1; GR64:%vreg1 JNE_1 <BB#1>, %EFLAGS<imp-use> Both copies are useless. This patch tries to eliminate the later copy in a generic manner. dec is especially confusing to LLVM when compared with sub. I wrote this patch to treat all physical registers generically, but only remove redundant copies of non-allocatable physical registers because the allocatable ones caused issues (e.g. when calling conventions weren't properly modeled) and should be handled later by the register allocator anyways. The following tests used to failed when the patch also replaced allocatable registers: CodeGen/X86/StackColoring.ll CodeGen/X86/avx512-calling-conv.ll CodeGen/X86/copy-propagation.ll CodeGen/X86/inline-asm-fpstack.ll CodeGen/X86/musttail-varargs.ll CodeGen/X86/pop-stack-cleanup.ll CodeGen/X86/preserve_mostcc64.ll CodeGen/X86/tailcallstack64.ll CodeGen/X86/this-return-64.ll This happens because COPY has other special meaning for e.g. dependency breakage and x87 FP stack. Note that all other backends' tests pass. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D15157 llvm-svn: 254665
* AsmPrinter: Simplify emitting FP elements in sequential data. NFCJustin Bogner2015-12-031-26/+15
| | | | | | | Use APFloat APIs here Rather than manually type-punning through unions. llvm-svn: 254664
* [WebAssembly] Fix dominance check for PHIs in the StoreResult passDan Gohman2015-12-032-16/+26
| | | | | | | | | | | | | | When a block has no terminator instructions, getFirstTerminator() returns end(), which can't be used in dominance checks. Check dominance for phi operands separately. Also, remove some bits from WebAssemblyRegStackify.cpp that were causing trouble on the same testcase; they were left behind from an earlier experiment. Differential Revision: http://reviews.llvm.org/D15210 llvm-svn: 254662
* Revert "raw_ostream: << operator for callables with raw_stream argument"Matthias Braun2015-12-034-66/+76
| | | | | | | | This commit provoked "error C2593: 'operator <<' is ambiguous" on MSVC. This reverts commit r254655. llvm-svn: 254661
* [Analysis] Become aware of MSVC's new/delete functionsDavid Majnemer2015-12-031-2/+22
| | | | | | | | The compiler can take advantage of the allocation/deallocation function's properties. We knew how to do this for Itanium but had no support for MSVC-style functions. llvm-svn: 254656
* raw_ostream: << operator for callables with raw_stream argumentMatthias Braun2015-12-034-76/+66
| | | | | | | | | | | | | | | | | This allows easier construction of print helpers. Example: Printable PrintLaneMask(unsigned LaneMask) { return Printable([LaneMask](raw_ostream &OS) { OS << format("%08X", LaneMask); }); } // Usage: OS << PrintLaneMask(Mask); Differential Revision: http://reviews.llvm.org/D14348 llvm-svn: 254655
* [X86] Part 1 to fix x86-64 fp128 calling convention.Chih-Hung Hsieh2015-12-0313-75/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all these changes are conditioned and only apply to the new x86-64 f128 type configuration, which will be enabled in a follow up patch. They are required together to make new f128 work. If there is any error, we should fix or revert them as a whole. These changes should have no impact to current configurations. * Relax type legalization checks to accept new f128 type configuration, whose TypeAction is TypeSoftenFloat, not TypeLegal, but also has TLI.isTypeLegal true. * Relax GetSoftenedFloat to return in some cases f128 type SDValue, which is TLI.isTypeLegal but not "softened" to i128 node. * Allow customized FABS, FNEG, FCOPYSIGN on new f128 type configuration, to generate optimized bitwise operators for libm functions. * Enhance related Lower* functions to handle f128 type. * Enhance DAGTypeLegalizer::run, SoftenFloatResult, and related functions to keep new f128 type in register, and convert f128 operators to library calls. * Fix Combiner, Emitter, Legalizer routines that did not handle f128 type. * Add ExpandConstant to handle i128 constants, ExpandNode to handle ISD::Constant node. * Add one more parameter to getCommonSubClass and firstCommonClass, to guarantee that returned common sub class will contain the specified simple value type. This extra parameter is used by EmitCopyFromReg in InstrEmitter.cpp. * Fix infinite loop in getTypeLegalizationCost when f128 is the value type. * Fix printOperand to handle null operand. * Enhance ISD::BITCAST node to handle f128 constant. * Expand new f128 type for BR_CC, SELECT_CC, SELECT, SETCC nodes. * Enhance X86AsmPrinter to emit f128 values in comments. Differential Revision: http://reviews.llvm.org/D15134 llvm-svn: 254653
* [Hexagon] Adding shuffling resources for HVX instructions and tests for ↵Colin LeMahieu2015-12-032-7/+131
| | | | | | instruction encodings. llvm-svn: 254652
* [RuntimeDyld] DenseMap -> std::unordered_mapKeno Fischer2015-12-032-3/+4
| | | | | | | | | | | DenseMap is most applicable when both keys and values are small. In this case, the value violates that assumption, causing quite significant memory overhead. A std::unordered_map is more appropriate in this case (or at least fixed the memory problems I was seeing). Differential Revision: http://reviews.llvm.org/D14910 llvm-svn: 254651
* Interface to attach maximum function count from PGO to module as module flags.Easwaran Raman2015-12-031-0/+12
| | | | | | | | | | This provides interface to get and set maximum function counts to Module. This would allow things like determination of function hotness. The actual setting of this max function count will have to be done in the frontend. Differential Revision: http://reviews.llvm.org/D15003 llvm-svn: 254647
* [X86] Put no-op ADJCALLSTACK markers around all dynamic loweringsReid Kleckner2015-12-031-40/+29
| | | | | | | | | | | | | | | | | Summary: These ADJCALLSTACK markers don't generate code, but they keep dynamic alloca code that calls chkstk out of the prologue. This slightly pessimizes inalloca calls by preventing some register copy coalescing, but I can live with that. Reviewers: qcolombet Subscribers: hans, llvm-commits Differential Revision: http://reviews.llvm.org/D15200 llvm-svn: 254645
* Test commit.Easwaran Raman2015-12-031-2/+2
| | | | | | Remove blank spaces at the end of comments llvm-svn: 254630
* [WinEH] Avoid infinite loop in BranchFolding for multiple single block funcletsAndrew Kaylor2015-12-031-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D14996 llvm-svn: 254629
* dwarfdump: Correctly indentify the indicies for DWP recordsDavid Blaikie2015-12-031-1/+1
| | | | | | The indicies are one-based, not zero-based, per the spec. llvm-svn: 254626
* [ThinLTO] Appending linkage fixesTeresa Johnson2015-12-031-5/+9
| | | | | | | | | | | | | | | | | | | | Summary: Fix import from module with appending var, which cannot be imported. The first fix is to remove an overly-aggressive error check. The second fix is to deal with restructuring introduced to the module linker yesterday in r254418 (actually, this fix was included already in r254559, just added some additional cleanup). Test by Mehdi Amini. Reviewers: joker.eph, rafael Subscribers: joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D15156 llvm-svn: 254624
* [Hexagon] Remove variable unused in NDEBUG buildKrzysztof Parzyszek2015-12-031-3/+2
| | | | llvm-svn: 254623
* AArch64FastISel: Use cbz/cbnz to branch on i1Matthias Braun2015-12-031-61/+25
| | | | | | | | | In the case of a conditional branch without a preceding cmp we used to emit a "and; cmp; b.eq/b.ne" sequence, use tbz/tbnz instead. Differential Revision: http://reviews.llvm.org/D15122 llvm-svn: 254621
* [Hexagon] Implement CONCAT_VECTORS for HVX using V6_vcombineKrzysztof Parzyszek2015-12-033-1/+26
| | | | llvm-svn: 254617
* [Hexagon] NFC Using canonicalizePacket to compound/duplex/pad packets rather ↵Colin LeMahieu2015-12-031-17/+11
| | | | | | than doing it separately. This also ensures the integrated assembler path matches the assembly parser path. llvm-svn: 254616
* Simplify ValueMap handling.Rafael Espindola2015-12-031-42/+49
| | | | | | We now just return values and let ValueMap handle the map. llvm-svn: 254615
* [Hexagon] Fix instruction descriptor flags for memory access sizeKrzysztof Parzyszek2015-12-031-2/+6
| | | | llvm-svn: 254613
* Don't pass member variables to member functions. NFC.Rafael Espindola2015-12-031-17/+12
| | | | llvm-svn: 254610
* [X86] MS inline asm: produce error when encountering "<type> ptr <reg name>"Marina Yatsina2015-12-031-2/+11
| | | | | | | | | | | | | Currently "<type> ptr <reg name>" treated as <reg name> in MS inline asm, ignoring the "<type> ptr" completely and possibly ignoring the intention of the user. Fixed llvm to produce an error when encountering "<type> ptr <reg name>" operands. For example: andpd xmm1,xmmword ptr xmm1 --> andpd xmm1, xmm1 though andpd has 2 possible matching formats - andpd xmm, xmm/m128 Patch by: ziv.izhar@intel.com Differential Revision: http://reviews.llvm.org/D14607 llvm-svn: 254607
* [X86] Add support for fcomip, fucomip for Intel syntaxMarina Yatsina2015-12-031-2/+2
| | | | | | | | According to x86 spec, fcomip and fucomip should be supported for Intel syntax. Differential Revision: http://reviews.llvm.org/D15104 llvm-svn: 254595
* Fix class SCEVPredicate has virtual functions and accessible non-virtual ↵Andy Gibbs2015-12-031-0/+2
| | | | | | | | | | destructor. It is not enough to simply make the destructor virtual since there is a g++ 4.7 issue (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53613) that throws the error "looser throw specifier for ... overridding ~SCEVPredicate() noexcept". llvm-svn: 254592
* AMDGPU/SI: Emit constant arrays in the .hsrodata_readonly_agent sectionTom Stellard2015-12-037-1/+25
| | | | | | | | | | | | Summary: This is done only when targeting HSA. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13807 llvm-svn: 254587
* Revert "ScheduleDAGInstrs: Rework schedule graph builder."Matthias Braun2015-12-031-159/+66
| | | | | | | | | | This works mostly fine but breaks some stage 1 builders when compiling compiler-rt on i386. Revert for further investigation as I can't see an obvious cause/fix. This reverts commit r254577. llvm-svn: 254586
* clang-format FunctionImport after refactoring (NFC)Mehdi Amini2015-12-031-9/+10
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 254585
* Refactor FunctionImporter::importFunctions with a helper function to process ↵Mehdi Amini2015-12-031-29/+45
| | | | | | | | | the Worklist (NFC) This precludes some more functional changes to perform bulk imports. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 254583
* Adapt comment and rename variable in ModuleLinker to describe more ↵Mehdi Amini2015-12-031-4/+4
| | | | | | | | | accurately the actual use. Thanks Sean Silva for the suggestion. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 254582
* Remove "ExportingModule" from ThinLTO Index (NFC)Mehdi Amini2015-12-033-10/+7
| | | | | | | | | | | | | | | | | | | | | There is no real reason the index has to have the concept of an exporting Module. We should be able to have one single unique instance of the Index, and it should be read-only after creation for the whole ThinLTO processing. The linker plugin should be able to process multiple modules (in parallel or in sequence) with the same index. The only reason the ExportingModule was present seems to be to implement hasExportedFunctions() that is used by the Module linker to decide what to do with the current Module. For now I replaced it with a query to the map of Modules path to see if this module was declared in the Index and consider that if it is the case then it is probably exporting function. On the long term the Linker interface needs to evolve and this call should not be needed anymore. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 254581
* Add a TODO item that the nop handling before FP conditional branches isJoerg Sonnenberger2015-12-031-0/+2
| | | | | | not enough for SPARCv7. llvm-svn: 254580
* ScheduleDAGInstrs: Rework schedule graph builder.Matthias Braun2015-12-031-66/+159
| | | | | | | | | | | | | | | The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254577
* RegisterPressure: Use range based for, fix else style; NFCMatthias Braun2015-12-031-41/+28
| | | | llvm-svn: 254575
* MC: Make sure to clear *all* of MCMachOStreamer's stateJustin Bogner2015-12-031-0/+1
| | | | | | | The CreatedADWARFSection flag was added in r232842, but isn't cleared properly when resetting the streamer's state. Fix that. llvm-svn: 254571
* [WebAssembly] Add a test for wasm-store-results passDerek Schuff2015-12-031-1/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D15167 llvm-svn: 254570
* [WebAssembly] Assert that byval and nest are not used for return types.Dan Gohman2015-12-021-4/+2
| | | | llvm-svn: 254567
* Forgot to add this file with r254562.David Majnemer2015-12-021-0/+41
| | | | llvm-svn: 254565
* [Hexagon] Improve lowering of instructions to the MC layerKrzysztof Parzyszek2015-12-023-24/+55
| | | | | | | | | - Add extenders when necessary. - Handle some basic relocations. This should fix the failure in tools/clang/test/CodeGenCXX/crash.cpp llvm-svn: 254564
* Move EH-specific helper functions to a more appropriate placeDavid Majnemer2015-12-0216-62/+15
| | | | | | No functionality change is intended. llvm-svn: 254562
* Fixup for r254547: use format_hex() to simplify code.Alexey Samsonov2015-12-021-2/+1
| | | | llvm-svn: 254560
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