summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Minor code cleanup. NFC.Junmo Park2016-02-181-1/+1
| | | | llvm-svn: 261200
* Test commit access.Nikolay Haustov2016-02-181-1/+0
| | | | llvm-svn: 261199
* [AVX512][PRORQ][PRORD] Change imm8 to intMichael Zuckerman2016-02-181-6/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D17024 llvm-svn: 261198
* [PM/AA] Teach the new pass manager to use pass-by-lambda for registeringChandler Carruth2016-02-182-4/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | analysis passes, support pre-registering analyses, and use that to implement parsing and pre-registering a custom alias analysis pipeline. With this its possible to configure the particular alias analysis pipeline used by the AAManager from the commandline of opt. I've updated the test to show this effectively in use to build a pipeline including basic-aa as part of it. My big question for reviewers are around the APIs that are used to expose this functionality. Are folks happy with pass-by-lambda to do pass registration? Are folks happy with pre-registering analyses as a way to inject customized instances of an analysis while still using the registry for the general case? Other thoughts of course welcome. The next round of patches will be to add the rest of the alias analyses into the new pass manager and wire them up here so that they can be used from opt. This will require extending the (somewhate limited) functionality of AAManager w.r.t. module passes. Differential Revision: http://reviews.llvm.org/D17259 llvm-svn: 261197
* [WebAssembly] Don't use setRequiresStructuredCFG(true).Dan Gohman2016-02-181-3/+4
| | | | | | | | | | | | While we still do want reducible control flow, the RequiresStructuredCFG flag imposes more strict structure constraints than WebAssembly wants. Unsetting this flag enables critical edge splitting and tail merging. Also, disable TailDuplication explicitly, as it doesn't support virtual registers, and was previously only disabled by the RequiresStructuredCFG flag. llvm-svn: 261190
* Revert "LiveIntervalAnalysis: Remove LiveVariables requirement" and ↵Matthias Braun2016-02-183-3/+7
| | | | | | | | | | | | | | | | | | | LiveIntervalTest The commit breaks stage2 compilation on PowerPC. Reverting for now while this is analyzed. I also have to revert the LiveIntervalTest for now as that depends on this commit. Revert "LiveIntervalAnalysis: Remove LiveVariables requirement" This reverts commit r260806. Revert "Remove an unnecessary std::move to fix -Wpessimizing-move warning." This reverts commit r260931. Revert "Fix typo in LiveIntervalTest" This reverts commit r260907. Revert "Add unittest for LiveIntervalAnalysis::handleMove()" This reverts commit r260905. llvm-svn: 261189
* [AMDGPU] Disassembler: Added basic disassembler for AMDGPU targetTom Stellard2016-02-1812-49/+551
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes: - Added disassembler project - Fixed all decoding conflicts in .td files - Added DecoderMethod=“NONE” option to Target.td that allows to disable decoder generation for an instruction. - Created decoding functions for VS_32 and VReg_32 register classes. - Added stubs for decoding all register classes. - Added several tests for disassembler Disassembler only supports: - VI subtarget - VOP1 instruction encoding - 32-bit register operands and inline constants [Valery] One of the point that requires to pay attention to is how decoder conflicts were resolved: - Groups of target instructions were separated by using different DecoderNamespace (SICI, VI, CI) using similar to AssemblerPredicate approach. - There were conflicts in IMAGE_<> instructions caused by two different reasons: 1. dmask wasn’t specified for the output (fixed) 2. There are image instructions that differ only by the number of the address components but have the same encoding by the HW spec. The actual number of address components is determined by the HW at runtime using image resource descriptor starting from the VGPR encoded in an IMAGE instruction. This means that we should choose only one instruction from conflicting group to be the rule for decoder. I didn’t find the way to disable decoder generation for an arbitrary instruction and therefore made a onelinear fix to tablegen generator that would suppress decoder generation when DecoderMethod is set to “NONE”. This is a change that should be reviewed and submitted first. Otherwise I would need to specify different DecoderNamespace for every instruction in the conflicting group. I haven’t checked yet if DecoderMethod=“NONE” is not used in other targets. 3. IMAGE_GATHER decoder generation is for now disabled and to be done later. [/Valery] Patch By: Sam Kolton Differential Revision: http://reviews.llvm.org/D16723 llvm-svn: 261185
* [libFuzzer] fix the libFuzzer bot Kostya Serebryany2016-02-182-2/+2
| | | | llvm-svn: 261184
* [WebAssembly] Disable register stackification and coloring when not optimizingDerek Schuff2016-02-173-11/+23
| | | | | | | | | | | | | | These passes are optimizations, and should be disabled when not optimizing. Also create an MCCodeGenInfo so the opt level is correctly plumbed to the backend pass manager. Also remove the command line flag for disabling register coloring; running llc with -O0 should now be useful for debugging, so it's not necessary. Differential Revision: http://reviews.llvm.org/D17327 llvm-svn: 261176
* AArch64: always clear kill flags up to last eliminated copyTim Northover2016-02-171-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | After r261154, we were only clearing flags if the known-zero register was originally live-in to the basic block, but we have to do it even if not when more than one COPY has been eliminated, otherwise the user of the first COPY may still have <kill> marked. E.g. BB#N: %X0 = COPY %XZR STRXui %X0<kill>, <fi#0> %X0 = COPY %XZR STRXui %X0<kill>, <fi#1> We can eliminate both copies, X0 is not live-in, but we must clear the kill on the first store. Unfortunately, I've been unable to come up with a non-fragile test for this. I've only seen it in the wild with regalloc-created spills, and attempts to reproduce that in a reasonable way run afoul of COPY coalescing. Even volatile asm clobbers were moved around. Should fix the aarch64 bot though. llvm-svn: 261175
* Add support for memory operations (load/store/gep) in C API echo testAmaury Sechet2016-02-171-0/+12
| | | | | | | | | | | | Summary: As per title. Reviewers: bogner, chandlerc, echristo, dblaikie, joker.eph, Wallbraker Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17245 llvm-svn: 261174
* [DebugInfoPDB] A few cleanups on PDB Variant class.Zachary Turner2016-02-171-2/+4
| | | | | | | | Also implements the PDBSymbolCompilandEnv::getValue() method, which until now had been unimplemented specifically because variant did not support string values. llvm-svn: 261173
* Move LLVMCreateTargetData and LLVMDisposeTargetData together. NFCAmaury Sechet2016-02-171-4/+4
| | | | llvm-svn: 261172
* DwarfDebug: Don't drop the DIExpression just because a variable isAdrian Prantl2016-02-171-3/+14
| | | | | | | | | | | described by an immediate. Found via http://reviews.llvm.org/D16867 Thanks to Paul Robinson for pointing this out. <rdar://problem/24456528> llvm-svn: 261168
* DbgVariable: Add an accessor for the common case of a single expressionAdrian Prantl2016-02-172-2/+5
| | | | | | | | belonging to a single DBG_VALUE instruction. NFC llvm-svn: 261167
* [sanitizer-coverage] implement -fsanitize-coverage=trace-pc. This is similar ↵Kostya Serebryany2016-02-171-6/+24
| | | | | | to trace-bb, but has a different API. We already use the equivalent flag in GCC for Linux kernel fuzzing. We may be able to use this flag with AFL too llvm-svn: 261159
* NFC: Fix formatingAmaury Sechet2016-02-171-4/+4
| | | | llvm-svn: 261156
* Fix warning on build without assertsTim Northover2016-02-171-4/+5
| | | | llvm-svn: 261155
* AArch64: improve redundant copy elimination.Tim Northover2016-02-171-40/+46
| | | | | | | | | | | | | | | Mostly, this fixes the bug that if the CBZ guaranteed Xn but Wn was used, we didn't sort out the use-def chain properly. I've also made it check more than just the last instruction for a compatible CBZ (so it can cope without fallthroughs). I'd have liked to do that separately, but it's helps writing the test. Finally, I removed some custom loops in favour of MachineInstr helpers and refactored the control flow to flatten it and avoid possibly quadratic iterations in blocks with many copies. NFC for these, just a general tidy-up. llvm-svn: 261154
* [DebugInfoPDB] Raise getSymIndexId() up to PDBSymbolZachary Turner2016-02-171-0/+1
| | | | | | | | | | | | | Every symbol, no matter what it's tag is, supports the method getSymIndexId(). However, this was being forwarded on every concrete symbol type, so if someone had a PDBSymbol that they didn't know what type it was (or simply didn't have an instance of the concrete symbol type), they would not be able to get its index id. This patch moves the method up to PDBSymbol, so that no matter what type of object you have, you can always get its id. llvm-svn: 261153
* [DebugInfoPDB] Teach Variant to support string types.Zachary Turner2016-02-172-22/+36
| | | | | | | | | | The IDiaSymbol::getValue() method returns a variant. Until now, I had never encountered a string value, so the Variant wrapper did not support VT_BSTR. Now we have need to support string values, so this patch just adds support for one extra type to Variant. llvm-svn: 261152
* [LIR] Avoid turning non-temporal stores into memsetHaicheng Wu2016-02-171-0/+4
| | | | | | This is to fix PR26645. llvm-svn: 261149
* Debug Info: Teach LdStHasDebugValue() (Local.cpp) about DIExpressions.Adrian Prantl2016-02-171-17/+16
| | | | | | | | | | | This function is used to check whether a dbg.value intrinsic has already been inserted, but without comparing the DIExpression, it would erroneously fire on split aggregates and only the first scalar would survive. Found via http://reviews.llvm.org/D16867. <rdar://problem/24456528> llvm-svn: 261145
* [libFuzzer] don't timeout when loading the corpus. Be a bit more verbose ↵Kostya Serebryany2016-02-172-1/+7
| | | | | | when loading large corpus. llvm-svn: 261143
* Create masked gather and scatter intrinsics in Loop Vectorizer.Elena Demikhovsky2016-02-172-111/+254
| | | | | | | | | Loop vectorizer now knows to vectorize GEP and create masked gather and scatter intrinsics for random memory access. The feature is enabled on AVX-512 target. Differential Revision: http://reviews.llvm.org/D15690 llvm-svn: 261140
* Fix load alignement when unpacking aggregates structsAmaury Sechet2016-02-171-12/+26
| | | | | | | | | | | | Summary: Store and loads unpacked by instcombine do not always have the right alignement. This explicitely compute the alignement and set it. Reviewers: dblaikie, majnemer, reames, hfinkel, joker.eph Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17326 llvm-svn: 261139
* Revert "Reapply commit r258404 with fix."David Majnemer2016-02-171-231/+11
| | | | | | This reverts commit r259357, it caused PR26629. llvm-svn: 261137
* [ObjCARC] Handle ARCInstKind::ClaimRV in OptimizeIndividualCalls.Frederic Riss2016-02-171-0/+1
| | | | | | | | | When support for objc_unsafeClaimAutoreleasedReturnValue has been added to the ARC optimizer in r258970, one case was missed which would lead the optimizer to execute an llvm_unreachable. In this case, just handle ClaimRV in the same way we handle RetainRV. llvm-svn: 261134
* [Hexagon] Replacing reference/dereference with reference cast.Colin LeMahieu2016-02-171-4/+4
| | | | llvm-svn: 261133
* Remove superfluous semicolon.Nico Weber2016-02-171-1/+1
| | | | llvm-svn: 261128
* Revert r261070, it caused PR26652 / PR26653.Nico Weber2016-02-171-126/+0
| | | | llvm-svn: 261127
* [WinEH] Optimize WinEH state storesDavid Majnemer2016-02-171-32/+175
| | | | | | | | | | | | | | | | | | | | | | | | | 32-bit x86 Windows targets use a linked-list of nodes allocated on the stack, referenced to via thread-local storage. The personality routine interprets one of the fields in the node as a 'state number' which indicates where the personality routine should transfer control. State transitions are possible only before call-sites which may throw exceptions. Our previous scheme had us update the state number before all call-sites which may throw. Instead, we can try to minimize the number of times we need to store by reasoning about the nearest store which dominates the current call-site. If the last store agrees with the current call-site, then we know that the state-update is redundant and can be elided. This is largely straightforward: an RPO walk of the blocks allows us to correctly forward propagate the information when the function is a DAG. Currently, loops are not handled optimally and may trigger superfluous state stores. Differential Revision: http://reviews.llvm.org/D16763 llvm-svn: 261122
* Add a profile summary class specific to instrumentation profiles.Easwaran Raman2016-02-173-23/+34
| | | | | | | | | Modify ProfileSummary class to make it not instrumented profile specific. Add a new InstrumentedProfileSummary class that inherits from ProfileSummary. Differential Revision: http://reviews.llvm.org/D17310 llvm-svn: 261119
* [Hexagon] Loop instructions don't need special processing. Extension and ↵Colin LeMahieu2016-02-171-25/+0
| | | | | | fitting is performed by generic code and the comment is incorrect, loops don't have a separate extended opcode. llvm-svn: 261118
* [NVPTX] Annotate convergent intrinsics as convergent.Justin Lebar2016-02-171-0/+2
| | | | | | | | | | | | | | | Summary: Previously the machine instructions for bar.sync &co. were not marked as convergent. This resulted in some MI passes (such as TailDuplication, fixed in an upcoming patch) doing unsafe things to these instructions. Reviewers: jingyue Subscribers: llvm-commits, tra, jholewinski, hfinkel Differential Revision: http://reviews.llvm.org/D17318 llvm-svn: 261115
* [NVPTX] Annotate call machine instructions as calls.Justin Lebar2016-02-171-0/+2
| | | | | | | | | | | | | | | | | Summary: Otherwise we'll try to do unsafe optimizations on these MIs, such as sinking loads below calls. (I suspect that this is not the only bug in the NVPTX instruction tablegen files; I need to comb through them.) Reviewers: jholewinski, tra Subscribers: jingyue, jhen, llvm-commits Differential Revision: http://reviews.llvm.org/D17315 llvm-svn: 261113
* Represent the dynamic table itself with a DynRegionInfo.Rafael Espindola2016-02-171-2/+0
| | | | | | | | | | | | The dynamic table is also an array of a fixed structure, so it can be represented with a DynReginoInfo. No major functionality change. The extra error checking is covered by existing tests with a broken dynamic program header. Idea extracted from r260488. I did the extra cleanups. llvm-svn: 261107
* [Hexagon] Fold object construction into map::insertKrzysztof Parzyszek2016-02-171-2/+2
| | | | llvm-svn: 261096
* AVX512: Fix LowerMSCATTER() return value.Igor Breger2016-02-171-1/+1
| | | | | | | | | | | Bug description: The bug was discovered when test was compiled with -O0. In case scatter result is DAG root , VectorLegalizer failed (assert) due to LowerMSCATTER() return kmask as result. Change LowerMSCATTER() to return chain as original node do. Differential Revision: http://reviews.llvm.org/D17331 llvm-svn: 261090
* [mips] Removed the SHF_ALLOC flag and the SHT_REL flag from the .pdr section.Scott Egerton2016-02-171-2/+1
| | | | | | | | | | | | This section is used for debug information and has no need to be in memory at runtime. This patch also fixes an error when compiling the Linux kernel. The error is that there are relocations within the .pdr section in a VDSO. SHT_REL was removed as it is a section type and not a section flag, therefore it does not make sense for it to be there. With this patch, LLVM now emits the same flags as the GNU assembler. llvm-svn: 261083
* [X86][AVX] Support bit-blend integer shuffles for 256-bit integer vectorsSimon Pilgrim2016-02-171-1/+3
| | | | | | | | | | | | AVX1 doesn't support the shuffling of 256-bit integer vectors. For 32/64-bit elements we get around this by shuffling as float/double but for 8/16-bit elements (assuming they can't widen) we currently just split, shuffle as 128-bit vectors and concatenate the results back. This patch adds the ability to lower using the bit-blend patterns before defaulting to the splitting behaviour. Part 2 of 2 Differential Revision: http://reviews.llvm.org/D17292 llvm-svn: 261082
* [X86][AVX] Support bit-mask integer shuffles for 256-bit integer vectorsSimon Pilgrim2016-02-171-2/+6
| | | | | | | | | | | | AVX1 doesn't support the shuffling of 256-bit integer vectors. For 32/64-bit elements we get around this by shuffling as float/double but for 8/16-bit elements (assuming they can't widen) we currently just split, shuffle as 128-bit vectors and concatenate the results back. This patch adds the ability to lower using the bit-mask patterns before defaulting to the splitting behaviour. In some cases this ends up matching what AVX2 would do anyhow or what AVX1 does on the split vectors. Part 1 of 2 Differential Revision: http://reviews.llvm.org/D17292 llvm-svn: 261081
* [X86][SSE] Tidyup BUILD_VECTOR operand collection. NFCI.Simon Pilgrim2016-02-171-23/+20
| | | | | | | | Avoid reuse of operand variables, keep them local to a particular lowering - the operand collection is unique to each case anyhow. Renamed from V to Ops to more closely match their purpose. llvm-svn: 261078
* [Hexagon] cast<> a reference instead of referencing + dereferencing.Benjamin Kramer2016-02-171-1/+1
| | | | llvm-svn: 261077
* Detecte vector reduction operations just before instruction selection.Cong Hou2016-02-171-0/+126
| | | | | | | | | | | | | | | | | | | | | | | | | This patch detects vector reductions before instruction selection. Vector reductions are vectorized reduction operations, and for such operations we have freedom to reorganize the elements of the result as long as the reduction of them stay unchanged. This will enable some reduction pattern recognition during instruction combine such as SAD/dot-product on X86. A flag is added to SDNodeFlags to mark those vector reduction nodes to be checked during instruction combine. To detect those vector reductions, we search def-use chains starting from the given instruction, and check if all uses fall into two categories: 1. Reduction with another vector. 2. Reduction on all elements. in which 2 is detected by recognizing the pattern that the loop vectorizer generates to reduce all elements in the vector outside of the loop, which includes several ShuffleVector and one ExtractElement instructions. Differential revision: http://reviews.llvm.org/D15250 llvm-svn: 261070
* Revert r260979 "[X86] Enable the LEA optimization pass by default."Hans Wennborg2016-02-171-5/+4
| | | | | | Asserts are still firing in Chromium builds. PR26575. llvm-svn: 261058
* Revert "Query the StringMap only once when creating MDString (NFC)"Mehdi Amini2016-02-171-6/+11
| | | | | | | | | This reverts commit r261030 and r261036. (The revision was marked "approved" on phabricator, but some concerns were raised on the mailing list. Thanks D. Blaikie for notifying me.) From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 261055
* [AliasSetTracker] Teach AliasSetTracker about MemSetInstHaicheng Wu2016-02-171-0/+41
| | | | | | | This change is to fix the problem discussed in http://lists.llvm.org/pipermail/llvm-dev/2016-February/095446.html. llvm-svn: 261052
* WebAssembly: update expected failuresJF Bastien2016-02-171-3/+0
| | | | | | r261050 seems to inadvertently fix the assertion failure. llvm-svn: 261051
* [WebAssembly] Call memcpy for large byval copies.Dan Gohman2016-02-171-1/+1
| | | | | | | | | | This fixes very slow compilation on test/CodeGen/Generic/2010-11-04-BigByval.ll . Note that MaxStoresPerMemcpy and friends are not yet carefully tuned so the cutoff point is currently somewhat arbitrary. However, it's important that there be a cutoff point so that we don't emit unbounded quantities of loads and stores. llvm-svn: 261050
OpenPOWER on IntegriCloud