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* Pass code-model through Module IR to LTO which will use it.Caroline Tice2018-09-212-1/+26
| | | | | | | | | | | Currently the code-model does not get saved in the module IR, so if a code model is specified when compiling with LTO, it gets lost and is not propagated properly to LTO. This patch, along with one for the front end, fixes that. Differential Revision: https://reviews.llvm.org/D52322 llvm-svn: 342760
* [Hexagon] Avoid functions with exception handling in HexagonConstExtendersKrzysztof Parzyszek2018-09-211-0/+5
| | | | | | | The constant-extender optimization does a form of code motion, which is complicated in the presence of exception handling. llvm-svn: 342751
* [tblgen] Fix undefined behaviour when assigning integers to large bits<n>'sDaniel Sanders2018-09-211-1/+1
| | | | | | | | | | | | | | | | | | This code: bits<96> X = 0; was triggering undefined behaviour since it iterates over bits 0..95 and tests them against the IntInit using 1LL << I. This patch resolves the undefined behaviour by continuing to treat the IntInit as a 64-bit value and simply causing all bit tests in excess of 64-bits to report false. As a result, bits<96> X = -1; will be equivalent to: bits<96> X; let X{0-63} = -1; let X{64-95} = 0; llvm-svn: 342744
* revert changes from r342722Sameer Sahasrabuddhe2018-09-212-3/+0
| | | | | | | | | "[AMDGPU] lower-switch in preISel as a workaround for legacy DA" This broke regression tests. The first breakage was noticed here: http://lab.llvm.org:8011/builders/lld-x86_64-freebsd/builds/23549 llvm-svn: 342743
* AArch64FastISel: Abort if we failed to select operand of intrinsicMatthias Braun2018-09-211-0/+3
| | | | | | | | rdar://44642447 Differential Revision: https://reviews.llvm.org/D52335 llvm-svn: 342742
* [X86][Sched] Add zero idiom sched data to the SNB model.Clement Courbet2018-09-211-1/+51
| | | | | | | | | | | | | | | | | | | | Summary: On SNB, renamer-based zeroing does not work for: - 16 and 8-bit GPRs[1]. - MMX [2]. - ANDN variants [3] [1] echo 'sub %ax, %ax' | /tmp/llvm-exegesis -mode=uops -snippets-file=- [2] echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- [3] echo 'andnps %xmm0, %xmm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- Reviewers: RKSimon, andreadb Subscribers: gbedwell, craig.topper, llvm-commits Differential Revision: https://reviews.llvm.org/D52358 llvm-svn: 342736
* [X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms.Andrea Di Biagio2018-09-211-0/+11
| | | | | | | | | | | | | | | | This patch introduces a SchedWriteVariant to describe zero-idiom VXORP(S|D)Yrr and VANDNP(S|D)Yrr. This is a follow-up of r342555. On Jaguar, a VXORPSYrr is 2 macro opcodes. Only one opcode is eliminated at register-renaming stage. The other opcode has to be executed to set the upper half of the destination YMM. Same for VANDNP(S|D)Yrr. Differential Revision: https://reviews.llvm.org/D52347 llvm-svn: 342728
* Ensure that variant part discriminator is read by MetadataLoaderJonas Devlieghere2018-09-211-1/+1
| | | | | | | | | | | | | | | https://reviews.llvm.org/D42082 introduced variant parts to debug info in LLVM. Subsequent work on the Rust compiler has found a bug in that patch; namely, there is a path in MetadataLoader that fails to restore the discriminator. This patch fixes the bug. Patch by: Tom Tromey Differential revision: https://reviews.llvm.org/D52340 llvm-svn: 342725
* [AMDGPU] lower-switch in preISel as a workaround for legacy DASameer Sahasrabuddhe2018-09-212-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The default target of the switch instruction may sometimes be an "unreachable" block, when it is guaranteed that one of the cases is always taken. The dominator tree concludes that such a switch instruction does not have an immediate post dominator. This confuses divergence analysis, which is unable to propagate sync dependence to the targets of the switch instruction. As a workaround, the AMDGPU target now invokes lower-switch as a preISel pass. LowerSwitch is designed to handle the unreachable default target correctly, allowing the divergence analysis to locate the correct immediate dominator of the now-lowered switch. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits, simoll Differential Revision: https://reviews.llvm.org/D52221 llvm-svn: 342722
* [AMDGPU] Divergence driven instruction selection. Part 1.Alexander Timofeev2018-09-216-47/+166
| | | | | | | | | | | | | Summary: This change is the first part of the AMDGPU target description change. The aim of it is the effective splitting the vector and scalar flows at the selection stage. Selection uses predicate functions based on the framework implemented earlier - https://reviews.llvm.org/D35267 Differential revision: https://reviews.llvm.org/D52019 Reviewers: rampitec llvm-svn: 342719
* [dwarfdump] Verify DW_AT_type is set and points to a compatible DIE.Jonas Devlieghere2018-09-211-0/+21
| | | | | | | | | | | | | This extends the verifier to catch three new errors: * Missing DW_AT_type attributes for DW_TAG_formal_parameter, DW_TAG_variable and DW_TAG_array_type. * Valid references for DW_AT_type pointing to a non-type tag. Differential revision: https://reviews.llvm.org/D52223 llvm-svn: 342713
* [dwarfdump] Verify compatibility of attribute TAGs.Jonas Devlieghere2018-09-212-7/+34
| | | | | | | | | Verify that DW_AT_specification and DW_AT_abstract_origin reference a DIE with a compatible tag. Differential revision: https://reviews.llvm.org/D38719 llvm-svn: 342712
* Merge clang's isRepeatedBytePattern with LLVM's isBytewiseValueJF Bastien2018-09-213-33/+73
| | | | | | | | | | | | | Summary: his code was in CGDecl.cpp and really belongs in LLVM's isBytewiseValue. Teach isBytewiseValue the tricks clang's isRepeatedBytePattern had, including merging undef properly, and recursing on more types. clang part of this patch: D51752 Subscribers: dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D51751 llvm-svn: 342709
* [MachineCopyPropagation] Refactor copy tracking into a class. NFCJustin Bogner2018-09-211-99/+133
| | | | | | | | This is a bit easier to follow than handling the copy and src maps directly in the pass, and will make upcoming changes to how this is done easier to follow. llvm-svn: 342703
* [MachineCopyPropagation] Minor clang-formatting. NFCJustin Bogner2018-09-211-37/+37
| | | | llvm-svn: 342700
* Add the ability to register callbacks for removal and insertion of MachineInstrsAditya Nandakumar2018-09-202-1/+17
| | | | | | | | | https://reviews.llvm.org/D52127 This patch adds the ability to watch for insertions/deletions of MachineInstructions similar to MachineRegisterInfo. llvm-svn: 342696
* bpf: check illegal usage of XADD insn return valueYonghong Song2018-09-204-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, BPF has XADD (locked add) insn support and the asm looks like: lock *(u32 *)(r1 + 0) += r2 lock *(u64 *)(r1 + 0) += r2 The instruction itself does not have a return value. At the source code level, users often use __sync_fetch_and_add() which eventually translates to XADD. The return value of __sync_fetch_and_add() is supposed to be the old value in the xadd memory location. Since BPF::XADD insn does not support such a return value, this patch added a PreEmit phase to check such a usage. If such an illegal usage pattern is detected, a fatal error will be reported like line 4: Invalid usage of the XADD return value if compiled with -g, or Invalid usage of the XADD return value if compiled without -g. Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 342692
* [WebAssembly] Add V128 value type to binary formatThomas Lively2018-09-206-23/+16
| | | | | | | | | | | | | | Summary: Adds the necessary support to lib/ObjectYAML and fixes SIMD calls to allow the tests to work. Also removes some dead code that would otherwise have to have been updated. Reviewers: aheejin, dschuff, sbc100 Subscribers: jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52105 llvm-svn: 342689
* [MachineOutliner][NFC] Don't add MBBs with a size < 2 to the search spaceJessica Paquette2018-09-201-1/+5
| | | | | | | | | | | The suffix tree won't ever consider sequences with a length less than 2. Therefore, we really ought to not even consider them in the first place. Also add a FIXME explaining that this should be defined in terms of the size in B of an outlined call versus the size in B of the MBB. llvm-svn: 342688
* [GlobalDCE] AvailableExternal linkage is checked in isDiscardableIfUnused [NFC].Xin Tong2018-09-201-1/+1
| | | | | | | | | | | | | | | | Summary: AvailableExternal was not handled in isDiscardableIfUnused when isDiscardableIfUnused was added in r158476. Till it was handled in r247044. This is a NFC. Reviewers: pcc, tejohnson Reviewed By: tejohnson Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52319 llvm-svn: 342684
* [RegAllocGreedy] Fix crash in tryLocalSplitWalter Lee2018-09-201-1/+5
| | | | | | | | | | tryLocalSplit only handles a single use block, but an interval may have multiple use blocks. So don't crash in that case. This fixes PR38795. Differential revision: https://reviews.llvm.org/D52277 llvm-svn: 342682
* [PDB] Fix -Wcovered-switch-default warning.Zachary Turner2018-09-201-3/+0
| | | | llvm-svn: 342681
* [Bitcode] Address backwards compat bug in r342631Vedant Kumar2018-09-201-2/+2
| | | | | | | | | | | | | | | | | r342631 expanded bitc::METADATA_LOCATION by one element. The bitcode metadata loader was changed in a backwards-incompatible way, leading to crashes when disassembling old bitcode: assertion: empty() && "PlaceholderQueue hasn't been flushed before being destroyed" Assertion failed: (empty() && "PlaceholderQueue hasn't been flushed before being destroyed") This commit teaches the metadata loader to assume that the newly-added IsImplicitCode bit is 'false' when not present in old bitcode. I've added a bitcode compat regression test. rdar://44645820 llvm-svn: 342678
* [MachineOutliner][NFC] Move debug info emission to createOutlinedFunctionJessica Paquette2018-09-201-35/+23
| | | | | | | | | When you create an outlined function, you know everything you need to know to decide if debug info should be created. If we emit debug info in createOutlinedFunction, then we don't need to keep track of every IR function we create. llvm-svn: 342677
* [inline Cost] Don't mark functions accessing varargs as non-inlinableSameer AbuAsal2018-09-201-7/+5
| | | | | | | | | | | | | | | | | | Summary: rL323619 marks functions that are calling va_end as not viable for inlining. This patch reverses that since this va_end doesn't need access to the vriadic arguments list that are saved on the stack, only va_start does. Reviewers: efriedma, fhahn Reviewed By: fhahn Subscribers: eraman, haicheng, llvm-commits Differential Revision: https://reviews.llvm.org/D52067 llvm-svn: 342675
* Fix warnings.Zachary Turner2018-09-201-1/+0
| | | | llvm-svn: 342670
* [SelectionDAG] replace duplicated peekThroughBitcast helper functions; NFCISanjay Patel2018-09-203-51/+31
| | | | | | | | | | | | | | x86 had 2 versions of peekThroughBitcast. DAGCombiner had 1. Plus, it had a 1-off implementation for the one-use variant. Move the x86 versions of the code to SelectionDAG, so we don't have different copies of the code. No functional change intended. I'm putting this next to isBitwiseNot() because I am planning to use it in there. Another option is next to the helpers in the ISD namespace (eg, ISD::isConstantSplatVector()). But if there's no good reason for those to be there, I'd prefer to pull other helpers over to SelectionDAG in follow-up steps. Differential Revision: https://reviews.llvm.org/D52285 llvm-svn: 342669
* [New PM] Introducing PassInstrumentation frameworkFedor Sergeev2018-09-206-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass Execution Instrumentation interface enables customizable instrumentation of pass execution, as per "RFC: Pass Execution Instrumentation interface" posted 06/07/2018 on llvm-dev@ The intent is to provide a common machinery to implement all the pass-execution-debugging features like print-before/after, opt-bisect, time-passes etc. Here we get a basic implementation consisting of: * PassInstrumentationCallbacks class that handles registration of callbacks and access to them. * PassInstrumentation class that handles instrumentation-point interfaces that call into PassInstrumentationCallbacks. * Callbacks accept StringRef which is just a name of the Pass right now. There were some ideas to pass an opaque wrapper for the pointer to pass instance, however it appears that pointer does not actually identify the instance (adaptors and managers might have the same address with the pass they govern). Hence it was decided to go simple for now and then later decide on what the proper mental model of identifying a "pass in a phase of pipeline" is. * Callbacks accept llvm::Any serving as a wrapper for const IRUnit*, to remove direct dependencies on different IRUnits (e.g. Analyses). * PassInstrumentationAnalysis analysis is explicitly requested from PassManager through usual AnalysisManager::getResult. All pass managers were updated to run that to get PassInstrumentation object for instrumentation calls. * Using tuples/index_sequence getAnalysisResult helper to extract generic AnalysisManager's extra args out of a generic PassManager's extra args. This is the only way I was able to explicitly run getResult for PassInstrumentationAnalysis out of a generic code like PassManager::run or RepeatedPass::run. TODO: Upon lengthy discussions we agreed to accept this as an initial implementation and then get rid of getAnalysisResult by improving RepeatedPass implementation. * PassBuilder takes PassInstrumentationCallbacks object to pass it further into PassInstrumentationAnalysis. Callbacks registration should be performed directly through PassInstrumentationCallbacks. * new-pm tests updated to account for PassInstrumentationAnalysis being run * Added PassInstrumentation tests to PassBuilderCallbacks unit tests. Other unit tests updated with registration of the now-required PassInstrumentationAnalysis. Made getName helper to return std::string (instead of StringRef initially) to fix asan builtbot failures on CGSCC tests. Reviewers: chandlerc, philip.pfaffe Differential Revision: https://reviews.llvm.org/D47858 llvm-svn: 342664
* [PDB] Better printing of builtin types when using DIA dumper.Zachary Turner2018-09-203-2/+33
| | | | llvm-svn: 342658
* [gcov] Fix wrong line hit counts when multiple blocks are on the same lineCalixte Denizet2018-09-201-21/+131
| | | | | | | | | | | | | | | | | | | | | Summary: The goal of this patch is to have the same behaviour than gcc-gcov. Currently the hit counts for a line is the sum of the counts for each block on that line. The idea is to detect the cycles in the graph of blocks in using the algorithm by Hawick & James. The count for a cycle is the min of the counts for each edge in the cycle. Once we've the count for each cycle, we can sum them and add the transition counts of those cycles. Fix both https://bugs.llvm.org/show_bug.cgi?id=38065 and https://bugs.llvm.org/show_bug.cgi?id=38066 Reviewers: marco-c, davidxl Reviewed By: marco-c Subscribers: vsk, lebedev.ri, sylvestre.ledru, dblaikie, llvm-commits Differential Revision: https://reviews.llvm.org/D49659 llvm-svn: 342657
* [PDB] Add the ability to map forward references to full decls.Zachary Turner2018-09-202-0/+133
| | | | | | | | | | | | | | | | | | | | | Some records point to an LF_CLASS, LF_UNION, LF_STRUCTURE, or LF_ENUM which is a forward reference and doesn't contain complete debug information. In these cases, we'd like to be able to quickly locate the full record. The TPI stream stores an array of pre-computed record hash values, one for each type record. If we pre-process this on startup, we can build a mapping from hash value -> {list of possible matching type indices}. Since hashes of full records are only based on the name and or unique name and not the full record contents, we can then use forward ref record to compute the hash of what *would* be the full record by just hashing the name, use this to get the list of possible matches, and iterate those looking for a match on name or unique name. llvm-pdbutil is updated to resolve forward references for the purposes of testing (plus it's just useful). Differential Revision: https://reviews.llvm.org/D52283 llvm-svn: 342656
* [IR] add shuffle query for vector concatenationSanjay Patel2018-09-201-0/+17
| | | | | | This can be used for combining and in the vectorizers/cost models. llvm-svn: 342653
* [InstCombine] Handle vector compares in foldGEPIcmp()Jesper Antonsson2018-09-201-1/+1
| | | | | | | | | | | | | | | | Summary: This is to fix PR38984 "InstCombine assertion at vector gep/icmp folding": https://bugs.llvm.org/show_bug.cgi?id=38984 Reviewers: majnemer, spatel, lattner, lebedev.ri Reviewed By: lebedev.ri Subscribers: lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D52263 llvm-svn: 342647
* [X86][SSE] Remove UNPCKL(SHUFFLE)->UNPCKH custom combineSimon Pilgrim2018-09-201-34/+0
| | | | | | This can be achieved more generally by combineX86ShufflesRecursively. llvm-svn: 342645
* [X86][SSE] Remove PSHUFLW/PSHUFHW combineRedundantHalfShuffle combineSimon Pilgrim2018-09-201-71/+0
| | | | | | This can be achieved more generally by combineX86ShufflesRecursively and was causing a fuzz test failure found by Mikael Holmén. llvm-svn: 342642
* [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExprAlex Bradbury2018-09-201-35/+34
| | | | | | | | | | | | | This is a trivial refactoring that I'm committing now as it makes a patch I'm about to post for review easier to follow. There is some overlap between evaluateConstantImm and addExpr in RISCVAsmParser. This patch allows evaluateConstantImm to be reused from addExpr to remove this overlap. The benefit will be greater when a future patch adds extra code to allows immediates to be evaluated from constant symbols (e.g. `.equ CONST, 0x1234`). No functional change intended. llvm-svn: 342641
* [DWARF] - Emit the correct value for DW_AT_addr_base.George Rimar2018-09-205-10/+30
| | | | | | | | | | | | | | Currently, we emit DW_AT_addr_base that points to the beginning of the .debug_addr section. That is not correct for the DWARF5 case because address table contains the header and the attribute should point to the first entry following the header. This is currently the reason why LLDB does not work with such executables correctly. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D52168 llvm-svn: 342635
* [IPSCCP] Fix a problem with removing labels in a switch with undef conditionBjorn Pettersson2018-09-201-25/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before removing basic blocks that ipsccp has considered as dead all uses of the basic block label must be removed. That is done by calling ConstantFoldTerminator on the users. An exception is when the branch condition is an undef value. In such scenarios ipsccp is using some internal assumptions regarding which edge in the control flow that should remain, while ConstantFoldTerminator don't know how to fold the terminator. The problem addressed here is related to ConstantFoldTerminator's ability to rewrite a 'switch' into a conditional 'br'. In such situations ConstantFoldTerminator returns true indicating that the terminator has been rewritten. However, ipsccp treated the true value as if the edge to the dead basic block had been removed. So the code for resolving an undef branch condition did not trigger, and we ended up with assertion that there were uses remaining when deleting the basic block. The solution is to resolve indeterminate branches before the call to ConstantFoldTerminator. Reviewers: efriedma, fhahn, davide Reviewed By: fhahn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52232 llvm-svn: 342632
* [IR] Add a boolean field in DILocation to know if a line must covered or notCalixte Denizet2018-09-209-23/+54
| | | | | | | | | | | | | | | | | | | | | Summary: Some lines have a hit counter where they should not have one. For example, in C++, some cleanup is adding at the end of a scope represented by a '}'. So such a line has a hit counter where a user expects to not have one. The goal of the patch is to add this information in DILocation which is used to get the covered lines in GCOVProfiling.cpp. A following patch in clang will add this information when generating IR (https://reviews.llvm.org/D49916). Reviewers: marco-c, davidxl, vsk, javed.absar, rnk Reviewed By: rnk Subscribers: eraman, xur, danielcdh, aprantl, rnk, dblaikie, #debug-info, vsk, llvm-commits, sylvestre.ledru Tags: #debug-info Differential Revision: https://reviews.llvm.org/D49915 llvm-svn: 342631
* [RISCV][MC] Improve parsing of jal/j operandsAlex Bradbury2018-09-202-9/+31
| | | | | | | | | | | | Examples such as `jal a3`, `j a3` and `jal a3, a3` are accepted by gas but rejected by LLVM MC. This patch rectifies this. I introduce RISCVAsmParser::parseJALOffset to ensure that symbol names that coincide with register names can safely be parsed. This is made a somewhat fiddly due to the single-operand alias form (see the comment in parseJALOffset for more info). Differential Revision: https://reviews.llvm.org/D52029 llvm-svn: 342629
* [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defsBjorn Pettersson2018-09-201-21/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
* Temporarily Revert "[New PM] Introducing PassInstrumentation framework"Eric Christopher2018-09-206-50/+0
| | | | | | | | as it was causing failures in the asan buildbot. This reverts commit r342597. llvm-svn: 342616
* Fix for bug 34002 - label generated before it block is finalized. ↵Maya Madhavan2018-09-202-1/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D52258 llvm-svn: 342615
* [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1QingShan Zhang2018-09-201-1/+2
| | | | | | | | | | Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert. Patch By: wuzish (Zixuan Wu) Differential Revision: https://reviews.llvm.org/D52072 llvm-svn: 342611
* [WebAssembly] Renumber SIMD opsThomas Lively2018-09-201-35/+35
| | | | | | | | | | | | | | | Summary: This change leaves holes in the opcode space where missing instructions could logically be added later if they were found to be useful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D52282 llvm-svn: 342610
* [New PM] Introducing PassInstrumentation frameworkFedor Sergeev2018-09-196-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pass Execution Instrumentation interface enables customizable instrumentation of pass execution, as per "RFC: Pass Execution Instrumentation interface" posted 06/07/2018 on llvm-dev@ The intent is to provide a common machinery to implement all the pass-execution-debugging features like print-before/after, opt-bisect, time-passes etc. Here we get a basic implementation consisting of: * PassInstrumentationCallbacks class that handles registration of callbacks and access to them. * PassInstrumentation class that handles instrumentation-point interfaces that call into PassInstrumentationCallbacks. * Callbacks accept StringRef which is just a name of the Pass right now. There were some ideas to pass an opaque wrapper for the pointer to pass instance, however it appears that pointer does not actually identify the instance (adaptors and managers might have the same address with the pass they govern). Hence it was decided to go simple for now and then later decide on what the proper mental model of identifying a "pass in a phase of pipeline" is. * Callbacks accept llvm::Any serving as a wrapper for const IRUnit*, to remove direct dependencies on different IRUnits (e.g. Analyses). * PassInstrumentationAnalysis analysis is explicitly requested from PassManager through usual AnalysisManager::getResult. All pass managers were updated to run that to get PassInstrumentation object for instrumentation calls. * Using tuples/index_sequence getAnalysisResult helper to extract generic AnalysisManager's extra args out of a generic PassManager's extra args. This is the only way I was able to explicitly run getResult for PassInstrumentationAnalysis out of a generic code like PassManager::run or RepeatedPass::run. TODO: Upon lengthy discussions we agreed to accept this as an initial implementation and then get rid of getAnalysisResult by improving RepeatedPass implementation. * PassBuilder takes PassInstrumentationCallbacks object to pass it further into PassInstrumentationAnalysis. Callbacks registration should be performed directly through PassInstrumentationCallbacks. * new-pm tests updated to account for PassInstrumentationAnalysis being run * Added PassInstrumentation tests to PassBuilderCallbacks unit tests. Other unit tests updated with registration of the now-required PassInstrumentationAnalysis. Reviewers: chandlerc, philip.pfaffe Differential Revision: https://reviews.llvm.org/D47858 llvm-svn: 342597
* [SelectionDAG] allow vector types with isBitwiseNot()Sanjay Patel2018-09-192-4/+5
| | | | | | | The test diff in not-and-simplify.ll is from a use in SimplifyDemandedBits, and the test diff in add.ll is from a DAGCombiner transform. llvm-svn: 342594
* AArch64: Add FuseCryptoEOR fusion rulesMatthias Braun2018-09-193-0/+27
| | | | | | | | There's some additional rules available on newer apple CPUs. rdar://41235346 llvm-svn: 342590
* MachineScheduler: Add -misched-print-dags flagMatthias Braun2018-09-191-1/+6
| | | | | | | | Add a flag to dump the schedule DAG to the debug stream. This will be used in upcoming commits to test schedule DAG mutations such as macro fusion. llvm-svn: 342589
* [ARM] Adjust the feature set for ExynosEvandro Menezes2018-09-191-0/+6
| | | | | | Fine tune the cost model for all Exynos processors. llvm-svn: 342585
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